JP6214846B1 - Semiconductor switch gate drive circuit - Google Patents

Abstract

When the semiconductor switch is turned off, the drive signal generation circuit energizes the inductor element by turning on the fourth switching element (Q4) for a predetermined first period from the state where the first switching element (Q1) is fixed on. Thereafter, the first switching element (Q1) is turned off for a predetermined second period to discharge the accumulated gate charge, the first switching element (Q1) is turned on for a predetermined third period, and the gate accumulated charge is interrupted, The first switching element (Q1) is turned off again for a predetermined fourth period, and then the fourth switching element (Q4) is fixed off, the second switching element (Q2) is fixed on, and the semiconductor switch is fixed off. In this way, the power consumption of the gate drive circuit is reduced.

Description

  The present invention relates to a gate drive circuit that drives on and off of a switching element.

  In the conventional gate drive circuit, it is possible to reduce both the switching loss and the noise, and in addition to reduce the conduction loss in the gate drive circuit, and to provide a gate drive circuit that can be easily controlled. The gate is connected to a driving element unit including an on driving element and an off driving element. When the drive control unit turns on the on-drive element, an on-voltage necessary to turn on the drive target element is applied to the gate of the drive target element via the on-drive element. Further, when the drive control unit turns on the off drive element, an off voltage necessary for turning off the drive target element is applied to the gate of the drive target element via the off drive element. When the drive control unit turns off both the on-drive element and the off-drive element, a resonance circuit is formed by the reactor constituting the auxiliary drive unit and the parasitic capacitance of the gate of the drive target element.

  In a state where the drive target element is on, that is, in a state where the on drive element is on and the off drive element is off, a current flows through the reactor from the gate side of the drive target element toward the reactor. From this state, when the ON drive element is turned off, current flows so that the accumulated charge of the parasitic capacitance of the gate of the drive target element is discharged and becomes zero or is charged with the opposite polarity due to resonance of the resonance circuit. to continue. As a result, the gate voltage rapidly decreases, and at the same time, the voltage across the drive target element (source-drain voltage, collector-emitter voltage) rapidly increases, and the drive element is turned off. When the gate voltage of the drive target element reaches the off voltage and the drive control unit turns on the off drive element, the gate voltage is held at the off voltage, whereby the drive target element is held in the off state.

  On the other hand, when the drive target element is off, that is, when the on drive element is off and the off drive element is on, a current flows through the reactor from the reactor toward the gate side of the drive target element. When the off-drive element is turned off from this state, the accumulated charge in the parasitic capacitance of the gate of the element to be driven is discharged and further charged in the opposite polarity due to resonance of the resonance circuit, or the accumulated charge is zero. Current continues to flow in the direction of charging. As a result, the gate voltage rapidly increases, and at the same time, the voltage across the drive target element rapidly decreases, and the drive target element is turned on. When the gate voltage of the drive target element reaches the on voltage and the drive control unit turns on the on drive element, the gate voltage is held at the on voltage, whereby the drive target element is held in the on state.

  In the auxiliary drive unit, when turning off the drive target element, until the on drive element is turned off, and when turning on the drive target element, the gate voltage is reduced to the off voltage or the on voltage before turning off the off drive element. It is necessary to pass a current of a magnitude necessary for the change to the reactor by resonance. In other words, since it is not necessary to flow more current, the power consumption in the gate drive circuit can be further reduced by controlling the period during which current is passed through the reactor by the auxiliary drive element.

  Further, a first control element that is a switching element for applying an on-voltage to a control end of the reactor (an end on the opposite side of the drive target element to the gate connection side), and a switching for applying an off-voltage A control element unit composed of a second control element, which is an element, is connected. The reactor current control unit turns on the first control element before turning off the off drive element for turning on the drive target element, that is, when the on drive element is off and the off drive element is on. The second control element is turned on before the on-drive element is turned off to turn off the drive target element, that is, when the on-drive element is on and the off drive element is off. As a result, current flows through the first control element, the reactor, and the off drive element before the off drive element is turned off. On the other hand, before the on drive element is turned off, the on drive element, the reactor, and the second control element are turned on. Current flows through. Therefore, by controlling the first and second control elements, the direction of the current flowing through the reactor and the period during which the current flows can be arbitrarily set (for example, Patent Document 1).

JP 2005-039988 A

  In the prior art, it is possible to reduce the capacity of the gate power supply by the recovery function using the reactor, but in the case of the half bridge configuration, it is necessary to set the positive voltage and the negative voltage equal to each other. When the withstand voltage of the positive electrode and the withstand voltage of the negative electrode are different, setting the lower withstand voltage may deteriorate the switching performance, and setting the higher withstand voltage may cause an excess withstand voltage.

  Next, when the drive target element is turned on and off, it is possible to charge and discharge the input capacitance of the drive target element at high speed by exciting the reactor in advance and generating an initial current. Although switching loss can be reduced by this high-speed switching, the problem is that noise increases.

  Accordingly, an object of the present invention is to provide a gate of a semiconductor switch that can simultaneously realize the capacity reduction of the gate power supply, the different setting of the positive voltage and the negative voltage of the gate circuit, and the switching loss reduction and noise reduction of the drive target element. A drive circuit is provided.

  The gate drive circuit disclosed in this specification is a gate drive circuit that drives a semiconductor switch. The gate drive circuit includes a plurality of switches, an inductor element connected to a gate terminal of the semiconductor switch, and a drive signal generation circuit that controls on / off operations of the plurality of switches. The drive signal generation circuit transmits a first excitation period for exciting the inductor element and an excitation power for the first excitation period to the gate terminal of the semiconductor switch at least one of when the semiconductor switch is turned on and when the semiconductor switch is turned off. 1 transmission period, a second excitation period for re-exciting the inductor element after the first transmission period, a second transmission period for transmitting excitation power of the second excitation period to the gate terminal of the semiconductor switch, A plurality of switches are controlled so as to be provided. Preferably, the plurality of switches include first to fourth switches. The first switch is connected between the positive terminal of the DC power supply and the first node. The second switch is connected between the first node and the negative terminal of the DC power supply. The third switch is connected between the positive terminal of the DC power source and the second node. The fourth switch is connected between the second node and the negative terminal of the DC power supply. The inductor element is connected between the first node and the second node. The drive signal generation circuit controls the on / off operation of each of the first to fourth switches.

  The first node is connected to the gate terminal of the semiconductor switch. The negative terminal of the DC power supply is connected to the emitter terminal of the semiconductor switch. The drive signal generation circuit controls the first to fourth switches so that the second switch is fixed on and the first, third, and fourth switches are fixed off when the semiconductor switch is fixed off. When the switch is fixed on, the first to fourth switches are controlled so that the first switch is fixed on and the second, third, and fourth switches are fixed off. When the semiconductor switch is turned off, the drive signal generation circuit starts the first switch after exciting the inductor element for a predetermined first period by turning on the fourth switch from the state in which the first switch is fixed on. Is turned off for a predetermined second period, the gate accumulated charge is discharged, the first switch is turned on for a predetermined third period, the discharge of the gate accumulated charge is interrupted, and the first switch is set again for the fourth period. After that, the fourth switch is fixed off, the second switch is fixed on, and the semiconductor switch is fixed off.

  According to the present invention, at the time of turn-off, the charge of the semiconductor switch that is driven using the exciting power of the inductor is charged and discharged, and at the same time, the exciting power is regenerated to the power source side, thereby greatly reducing the capacity of the power source that drives the gate. It becomes possible to do.

FIG. 3 is a circuit diagram illustrating a first configuration example of the gate drive circuit according to the first embodiment. FIG. 4 is a circuit diagram illustrating a second configuration example of the gate drive circuit according to the first embodiment. FIG. 4 is an operation waveform diagram of the gate drive circuit according to the first embodiment. FIG. 4 is an operation waveform diagram when the control of FIG. 3 is executed in the configuration of FIG. 1. FIG. 6 is a current path diagram (t = tp1) according to the first configuration example. FIG. 6 is a current path diagram (t = tp2) according to the first configuration example. FIG. 6 is a current path diagram (t = tp3) according to the first configuration example. FIG. 6 is a current path diagram (t = tp4) according to the first configuration example. FIG. 6 is a current path diagram (t = tp5) according to the first configuration example. FIG. 6 is a current path diagram (t = tp6) according to the first configuration example. FIG. 6 is a current path diagram (t = tp7) according to the first configuration example. FIG. 6 is a current path diagram (t = tp8) according to the first configuration example. FIG. 6 is a current path diagram (t = tp9) according to the first configuration example. FIG. 6 is a current path diagram (t = tp10) according to the first configuration example. FIG. 6 is a current path diagram (t = tp11) according to the first configuration example. FIG. 6 is a current path diagram (t = tp12) according to the first configuration example. FIG. 4 is an operation waveform diagram when the control of FIG. 3 is executed in the configuration of FIG. 2. FIG. 10 is a current path diagram (t = tp1) according to a second configuration example. FIG. 10 is a current path diagram (t = tp2) according to a second configuration example. FIG. 10 is a current path diagram (t = tp3) according to a second configuration example. FIG. 12 is a current path diagram (t = tp4) according to a second configuration example. FIG. 10 is a current path diagram (t = tp5) according to a second configuration example. FIG. 12 is a current path diagram (t = tp6) according to a second configuration example. FIG. 10 is a current path diagram (t = tp7) according to a second configuration example. FIG. 10 is a current path diagram (t = tp8) according to a second configuration example. FIG. 12 is a current path diagram (t = tp9) according to a second configuration example. FIG. 11 is a current path diagram (t = tp10) according to a second configuration example. FIG. 12 is a current path diagram (t = tp11) according to a second configuration example. FIG. 12 is a current path diagram (t = tp12) according to a second configuration example. FIG. 3 is a circuit diagram showing a configuration of a drive signal generation circuit in FIGS. 1 and 2. It is the figure which defined the period for demonstrating the drive signal generation circuit of FIG. 6 is a diagram illustrating a configuration of a drive signal generation circuit used in Embodiment 2. FIG. It is an operation | movement chart in the case of performing regenerative operation | movement only in turn-off operation | movement. It is an operation | movement chart in the case of performing regenerative operation | movement only in turn-on operation | movement. FIG. 6 is a diagram illustrating an inverter circuit according to a third embodiment. 6 is a diagram showing a converter circuit according to a third embodiment. FIG. It is a figure which shows the structure which applied the gate drive circuit to the chopper circuit.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

Embodiment 1 FIG.
In the first embodiment, a gate driving circuit when a semiconductor switch is turned on and turned off, which is a circuit using a single power supply and a circuit using two power supplies, will be described.

  Hereinafter, the gate drive circuit of the first embodiment will be described with reference to FIGS. FIG. 1 is a circuit diagram showing a first configuration example of the gate drive circuit according to the first embodiment. FIG. 2 is a circuit diagram showing a second configuration example of the gate drive circuit according to the first embodiment. FIG. 3 is an operation waveform diagram of the gate drive circuit according to the first embodiment.

  A gate drive circuit 100 shown in FIG. 1 is turned on / off by a single DC power supply 10 using a voltage-driven semiconductor switch 14 having an input capacitance as a drive semiconductor element. The gate drive circuit 100 includes a DC power supply 10, a clamp circuit 12 that clamps the gate at turn-on and turn-off, a regenerative circuit 11, and a drive signal generation circuit 18.

  The clamp circuit 12 includes a positive-side switching element Q1, a turn-on resistor 5 and a turn-off resistor 6 connected in series between the positive terminal 16 (positive bus) and the negative terminal 17 (negative bus) of the DC power supply 10. And a switching element Q2 on the negative electrode side.

  The regenerative circuit 11 includes a positive side switching element Q3, a negative side switching element Q4, and an inductor 8 (Lg). The switching element Q3 on the positive electrode side and the switching element Q4 on the negative electrode side are connected in series between the positive electrode terminal 16 and the negative electrode terminal 17 of the DC power supply 10, and the connection node is the AC output node 9. Inductor 8 has one end connected to AC output node 9.

  The drive signal generation circuit 18 generates drive signals Q1S to Q4S for the switching elements Q1 to Q4.

  The AC output node 7 of the clamp circuit 12 is connected to the gate terminal of the semiconductor switch 14. The other end of the inductor 8 of the regenerative circuit 11 is connected to the AC output node 7. The emitter terminal 15 of the semiconductor switch 14 is connected to the negative terminal 17 of the DC power supply 10.

  The DC voltage of the DC power supply 10 is Vdc, the current flowing through the inductor 8 constituting the regeneration circuit 11 is iLg, the current flowing through the input capacitor 13 (capacitor Ciss) of the semiconductor switch 14 is ig, and the input capacitor 13 (capacitor Ciss) of the semiconductor switch 14 ) Is Vge, and the voltage applied between the emitter and collector of the semiconductor switch 14 is Vce.

  The driving signal for the switching element Q1 is Q1S, the driving signal for the switching element Q2 is Q2S, the driving signal for the switching element Q3 is Q3S, and the driving signal for the switching element Q4 is Q4S.

  In the circuit configuration of FIG. 1, the switching elements Q1 to Q4 describe IGBTs (Insulated Gate Bipolar Transistors) with built-in diodes as an example. However, IGBTs without built-in diodes and diodes may be connected in parallel. Moreover, MOSFET (metal-oxide-semiconductor field-effect transistor) provided with the parasitic diode may be used. In addition, a thyristor having a diode connected in parallel, a GTO (Gate Turn-Off thyristor), or the like may be used.

  Similarly, in the circuit configuration of FIG. 1, the semiconductor switch 14 is described as an IGBT as an example, but may be a MOSFET, a thyristor, a GTO, or the like. In the present embodiment, the description will be continued assuming that the semiconductor switch 14 is an IGBT.

  The drive signal generation circuit 18 in FIG. 1 receives as input the drive signal DS of the semiconductor switch 14 and the gate current ig, the collector current ic, the gate-emitter voltage Vge, and the collector-emitter voltage Vce representing the state of the semiconductor switch 14. Drive signals Q1S, Q2S, Q3S, Q4S of switching elements Q1-Q4 are output.

  The collector current ic may be the emitter current of the semiconductor switch 14. Further, the collector-emitter voltage Vce may be a voltage between parasitic inductances of the semiconductor switch 14.

  A voltage-driven switching element having an input capacitor 13 may be used as the semiconductor switch 14, and a gate drive circuit may be configured to drive the semiconductor switch 14 on / off with two DC power sources 19 and 20 as shown in FIG. .

  In FIG. 2, unlike FIG. 1, an upper DC power source 19 and a lower DC power source 20 are connected in series, and a positive electrode terminal 16, a neutral point 21, and a negative electrode terminal 17 are provided. Unlike FIG. 1, the emitter terminal 15 of the semiconductor switch 14 is connected to the neutral point 21. Other configurations are the same as those in FIG.

FIG. 3 is a waveform diagram showing the operation of the switching elements Q1 to Q4 in the configuration of FIGS. Assuming that one period of the semiconductor switch 14 is T, the turn-off switching period is periods tp1 to tp6, the turn-on switching period is periods tp7 to tp12, the periods tp1 to tp6 are half periods T / 2, and the periods tp7 to tp12 are also half periods T / 2. In the following, each 12 periods of the periods tp1 to tp12 are defined as follows.
Period tp1: Turn-off initial excitation period tp2: Ciss charge recovery period tp3: Ciss charge recovery interruption period tp4: Ciss charge recovery period tp5: Excitation power regeneration period tp6: Turn-off duration period tp7: Turn-on initial excitation period Period tp8: Ciss charge injection period period tp9: Ciss charge injection interruption period period tp10: Ciss charge reinjection period period tp11: Excitation power regeneration period period tp12: Turn-on duration period

(Description of operation in first configuration example (single power supply))
FIG. 4 is an operation waveform diagram when the control of FIG. 3 is executed in the configuration of FIG. 5 to 16 are diagrams showing current paths in the operation periods tp1 to tp12, respectively.

  As shown in FIG. 5, in the period tp1 (turn-off initial excitation period), the switching element Q1 turns on the switching element Q4 while the turn-on continues. The current iLg flows from the positive terminal 16 of the DC power source 10 into the switching element Q1, flows into the switching element Q4 via the resistor Ron and the reactor Lg, and returns to the negative terminal 17 of the DC power source 10.

  At this time, since the voltage Vdc is applied to the reactor Lg, the reactor Lg is excited and the current iLg increases in the negative direction.

  As shown in FIG. 6, in the period tp2 (Ciss charge recovery period), the switching element Q1 is turned off and only the switching element Q4 is kept on. Since a negative current continues to flow as the current iLg, a current flows in the order of the gate terminal of the semiconductor switch 14, the reactor Lg, the switching element Q4, and the emitter terminal of the semiconductor switch 14, and the charge of the capacitor Ciss is discharged. In this current path, resonance operation occurs between the reactor Lg and the capacitance Ciss, the current iLg increases in the negative direction, and the voltage Vge decreases.

  As shown in FIG. 7, in the period tp3 (Ciss charge recovery interruption period), the switching element Q1 is again turned on, and the switching element Q4 continues to be turned on. The current flows from the positive terminal 16 of the DC power supply 10 into the switching element Q1, flows into the switching element Q4 via the resistor Ron and the reactor Lg, and returns to the negative terminal 17 of the DC power supply 10. On the other hand, current flows from the positive terminal 16 of the DC power supply 10 to the gate terminal of the drive semiconductor switch via the switching element Q1, and returns to the negative terminal 17 of the DC power supply via the emitter terminal 15 of the semiconductor switch 14.

  The current iLg increases in the negative direction with the same slope as that in the period tp1 by the excitation operation. The current ig reverses its polarity when the switching element Q1 is turned on, increases in the direction of charging the capacitor Ciss, and the voltage Vge increases.

  As shown in FIG. 8, in the period tp4 (Ciss charge recollection period), the switching element Q1 is turned off again, while the switching element Q4 continues to be turned on. In order to continuously flow the current iLg, a current flows in the order of the gate terminal of the semiconductor switch 14, the reactor Lg, the switching element Q4, and the emitter terminal of the semiconductor switch 14, and the charge of the capacitor Ciss is discharged. In this current path, resonance occurs between the reactor Lg and the capacitor Ciss, the current iLg increases in the negative direction, the voltage Vge decreases, and when the voltage Vge reaches 0 V, the parasitic diode of the switching element Q2 becomes conductive, so the voltage Vge Is clamped to 0V.

  As shown in FIG. 9, in the period tp5 (excitation power regeneration period), the switching element Q4 is turned off, and all the switching elements Q1 to Q4 are turned off. The exciting power of the reactor Lg is regenerated to the DC power supply 10 by a current path that flows through the parasitic diode of the switching element Q3 and the parasitic diode of the switching element Q2. The current at this time flows in the order of the negative terminal 17 of the DC power supply 10, the parasitic diode of the switching element Q2, the resistor Roff, the reactor Lg, and the parasitic diode of the switching element Q3 as shown in FIG. It flows into 16.

  As shown in FIG. 10, in the period tp6 (turn-off duration), the switching element Q2 is turned on. As a result, a current path is fed back from the capacitor Ciss to the capacitor Ciss via the node 7, the resistor Roff, and the switching element Q2, the capacitor Ciss is clamped to zero voltage, and the semiconductor switch 14 is turned off.

  As shown in FIG. 11, in the period tp7 (turn-on initial excitation period), the switching element Q3 is turned on while the switching element Q2 is kept turned on. While the semiconductor switch 14 is kept off by continuing the turn-on of the switching element Q2, current flows from the positive terminal 16 of the DC power source 10 to the switching element Q2 via the switching element Q3, the reactor Lg, and the resistor Roff. Return to the negative terminal 17 of the DC power supply 10. At this time, since the voltage Vdc is applied to the reactor Lg, the reactor Lg is excited and the current iLg increases in the positive direction.

  As shown in FIG. 12, in the period tp8 (Ciss charge injection period), the switching element Q2 is turned off, while the switching element Q3 continues to be turned on. In order to continuously flow the current iLg, the current flows from the positive terminal 16 of the DC power supply 10 to the capacitor Ciss via the switching element Q3 and the reactor Lg, and flows to the negative terminal 17 of the DC power supply 10. In this current path, resonance operation occurs between reactor Lg and capacitance Ciss, current iLg increases in the positive direction, and voltage Vge increases.

  As shown in FIG. 13, in the period tp9 (Ciss charge injection interruption period), the switching element Q2 is turned on again, while the switching element Q3 continues to be turned on. The current iLg flows back from the positive terminal 16 of the DC power source 10 to the negative terminal 17 via the switching element Q3, the reactor Lg, and the switching element Q2, and the reactor Lg is excited again by the voltage Vdc. On the other hand, the current ig is discharged from the capacitor Ciss via the switching element Q2. The current iLg increases with the same slope as the period tp7 by the excitation operation. The current ig increases in the direction in which the polarity is reversed and the capacitor Ciss is discharged when the switching element Q2 is turned on, and the voltage Vge decreases.

  As shown in FIG. 14, in the period tp10 (Ciss charge reinjection period), the switching element Q2 is turned off again, and the switching element Q3 continues to be turned on. Similar to the period tp8, the current flows from the positive terminal 16 of the DC power supply 10 into the capacitor Ciss via the switching element Q3 and the reactor Lg, and is supplied to the negative terminal 17 of the DC power supply 10. In this current path, resonance operation occurs between reactor Lg and capacitance Ciss, current iLg increases in the positive direction, and voltage Vge increases. When the voltage Vge reaches the voltage Vdc, the parasitic diode of the switching element Q1 becomes conductive and the voltage Vge is clamped to the voltage Vdc.

  As shown in FIG. 15, in the period tp11 (excitation power regeneration period), the switching element Q3 is turned off, and all the switching elements Q1 to Q4 are turned off. At this time, the exciting power of reactor Lg is regenerated to DC power supply 10 by the current flowing through the parasitic diode of switching element Q1 and the parasitic diode of switching element Q4.

  The current flows from the negative terminal 17 of the DC power supply 10 to the positive terminal 16 of the DC power supply 10 via the parasitic diode of the switching element Q4, the reactor Lg, and the parasitic diode of the switching element Q1.

  As shown in FIG. 16, in the period tp12 (turn-on duration), the switching element Q1 is turned on. As a result, a current path is formed that returns from the positive terminal 16 of the DC power supply 10 to the negative terminal 17 of the DC power supply 10 via the switching element Q1 and the capacitor Ciss. At this time, the voltage Vge of the capacitor Ciss is clamped to the voltage Vdc, and the semiconductor switch 14 is turned on.

(Description of operation in second configuration example (dual power supply))
FIG. 17 is an operation waveform diagram when the control of FIG. 3 is executed in the configuration of FIG. 18 to 29 are diagrams showing current paths in the operation periods tp1 to tp12, respectively.

  As shown in FIG. 18, in the period tp1 (turn-off initial excitation period), the switching element Q4 is turned on while the switching element Q1 is kept in the turn-on state. The current iLg flows from the positive terminal 16 of the DC power supply 19 via the switching element Q1, the resistor Ron, the reactor Lg, and the switching element Q4, and returns to the negative terminal 17 of the DC power supply 20.

  At this time, since the voltage (VdcH + VdcL) is applied to the reactor Lg, the reactor Lg is excited and the current iLg increases in the negative direction.

  As shown in FIG. 19, in the period tp2 (Ciss charge recovery period), the switching element Q4 is kept turned on and the switching element Q1 is turned off. In order to continuously flow the current iLg, the current flows from the neutral point 21 via the emitter terminal of the semiconductor switch 14, the gate terminal of the semiconductor switch 14, the reactor Lg, the switching element Q4, and the negative terminal 17 of the DC power source 20. The charge of the capacitor Ciss is discharged. In this current path, resonance operation occurs between reactor Lg and capacitance Ciss, current iLg increases in the negative direction, and voltage Vge decreases.

  As shown in FIG. 20, in the period tp3 (Ciss charge recovery interruption period), the switching element Q1 is turned on again in the state where the switching element Q4 continues to be turned on. The current iLg flows from the positive terminal 16 of the DC power supply 10 into the switching element Q4 via the switching element Q1, the resistor Ron, and the reactor Lg, and returns to the negative terminal 17 of the DC power supply 20. On the other hand, a current flows from the positive electrode terminal 16 of the DC power supply 10 to the gate terminal of the semiconductor switch 14 via the switching element Q1 and returns to the neutral point 21 via the emitter terminal 15 of the semiconductor switch 14. A route is created.

  The current iLg increases with the same slope as the period tp1 by the excitation operation. When the switching element Q1 is turned on, the polarity of the current ig is reversed, and the current ig increases in the direction of charging the capacitor Ciss, and the voltage Vge increases.

  As shown in FIG. 21, in the period tp4 (Ciss charge recovery period), the switching element Q1 is turned off again in a state where the switching element Q4 continues to be turned on. In order to continuously flow the current iLg, from the neutral point 21 to the negative terminal 17 of the DC power supply 20 via the emitter terminal 15 of the semiconductor switch 14, the gate terminal of the semiconductor switch 14, the reactor Lg, and the switching element Q4. A current flows, and the charge in the capacitor Ciss is discharged.

  In this current path, resonance operation occurs between the reactor Lg and the capacitance Ciss, and the current iLg increases in the negative direction. Further, when the voltage Vge decreases and reaches 0 V, the parasitic diode of the switching element Q2 becomes conductive, so that the voltage Vge is clamped to the voltage -VdcL.

  As shown in FIG. 22, in the period tp5 (excitation power regeneration period), the switching element Q4 is turned off, and the switching elements Q1 to Q4 are all turned off. The exciting power of the reactor Lg is regenerated to the DC power source 19 and the DC power source 20 by the current flowing through the parasitic diode of the switching element Q3 and the parasitic diode of the switching element Q2. The current at this time flows from the negative terminal 17 of the DC power source 20 via the parasitic diode of the switching element Q2, the resistor Roff, the reactor Lg, and the parasitic diode of the switching element Q3 as shown in FIG. It flows into the positive terminal 16.

  As shown in FIG. 23, in the period tp6 (turn-off duration), the switching element Q2 is turned on. As a result, the current flows from the negative terminal of the DC power supply 20 to the capacitor Ciss via the switching element Q2, the resistor Roff, and the node 7, and a current path is formed that returns from the emitter terminal 15 of the semiconductor switch 14 to the neutral point 21. Is done. The voltage of the capacitor Ciss is clamped to the voltage −VdcL, and the semiconductor switch 14 is turned off.

  As shown in FIG. 24, in the period tp7 (turn-on initial excitation period), the switching element Q2 is turned on and the switching element Q3 is turned on. While the switching element Q2 continues to be turned on, the semiconductor switch 14 continues to be turned off, but the current flows from the positive terminal 16 of the DC power source 19 to the switching element Q3, and passes through the reactor Lg, the resistor Roff, and the switching element Q2. Return to the negative terminal 17 of the DC power source 20.

  At this time, since the voltage Vdc is applied to the reactor Lg, the reactor Lg is excited and the current iLg increases in the positive direction.

  As shown in FIG. 25, in the period tp8 (Ciss charge injection period), the switching element Q2 is turned off while the switching element Q3 continues to be turned on. In order to continuously flow the current iLg, the current flows from the positive terminal 16 of the DC power source 19 to the neutral point 21 via the switching element Q3, the reactor Lg, and the capacitor Ciss. In this current path, resonance operation occurs between reactor Lg and capacitance Ciss, current iLg increases in the positive direction, and voltage Vge increases.

  As shown in FIG. 26, in the period tp9 (Ciss charge injection interruption period), the switching element Q2 is turned on again in a state where the switching element Q3 continues to be turned on. The current iLg is fed back from the positive terminal 16 of the DC power source 19 to the negative terminal 17 of the DC power source 20 via the switching element Q3, the reactor Lg, and the switching element Q2, and the reactor Lg is excited again by the voltage Vdc. On the other hand, the current ig is discharged from the capacitor Ciss via the switching element Q2. The current iLg increases with the same slope as the period tp7 by the excitation operation. The polarity of the current ig is reversed when the switching element Q2 is turned on, and the current ig increases in the direction of discharging the capacitor Ciss, and the voltage Vge decreases.

  As shown in FIG. 27, in the period tp10 (Ciss charge reinjection period), the switching element Q2 is turned off again while the switching element Q3 continues to be turned on. Similar to the period tp8, the current returns from the positive terminal 16 of the DC power source 19 to the negative terminal 17 of the DC power source 20 via the switching element Q3, the reactor Lg, and the capacitor Ciss. In this current path, resonance operation occurs between reactor Lg and capacitance Ciss, current iLg increases in the positive direction, and voltage Vge increases. When the voltage Vge reaches the voltage VdcH, the parasitic diode of the switching element Q1 becomes conductive, and the voltage Vge is clamped to the voltage VdcH.

  As shown in FIG. 28, in the period tp11 (excitation power regeneration period), the switching element Q3 is turned off, and all the switching elements Q1 to Q4 are turned off. At this time, the exciting power of reactor Lg is regenerated to DC power supply 19 and DC power supply 20 by the parasitic diode of switching element Q1 and the parasitic diode of switching element Q4.

  The current iLg flows from the negative terminal 17 of the DC power supply 20 to the positive terminal 16 of the DC power supply 19 via the parasitic diode of the switching element Q4, the reactor Lg, and the parasitic diode of the switching element Q1.

  As shown in FIG. 29, in the period tp12 (turn-on duration), the switching element Q1 is turned on. As a result, a current path is formed that flows from the positive terminal 16 of the DC power supply 10 into the capacitor Ciss via the switching element Q1 and returns to the negative terminal 17 of the DC power supply 10. The voltage of the capacitor Ciss is clamped to the voltage Vdc, and the semiconductor switch 14 continues to be turned on.

(Summary of operations of Configuration Example 1 and Configuration Example 2)
1 and FIG. 2, the reactor Lg excitation power is supplied to the capacitor Ciss as a reactive power at the time of turn-on, and the remaining reactor Lg excitation power is regenerated to the power source side. All the exciting power of the reactor Lg other than the accumulated charge of the capacitor Ciss is regenerated to the power supply side.

  Similarly, in the configuration of FIGS. 1 and 2, the accumulated charge of the capacitor Ciss is recovered as the exciting power of the reactor Lg at the time of turn-off, and the exciting power of the reactor Lg is regenerated to the power source side.

  Under ideal conditions in which no circuit loss occurs, only the collection and supply of the accumulated charge of the capacitor Ciss operates, and all other power is regenerated to the power supply side, resulting in an operation with a gate recovery efficiency of 100%. On the other hand, when a circuit loss occurs, the power regeneration amount is reduced by the amount of the circuit loss, so the efficiency is 100% or less.

  In the operation of the configuration shown in FIGS. 1 and 2, both current paths are formed via the parasitic diodes of the switching elements Q1 to Q4. For this diode function, parasitic diodes of the semiconductor elements of the switching elements Q1 to Q4 may be used. Alternatively, a diode may be connected in parallel to the switching elements Q1 to Q4. Or it is good also as a rectification | straightening operation | movement which makes a switching element conductive in synchronization with the diode conduction of switching elements Q1-Q4.

  In FIG. 1, the resistor Ron has a function of preventing an inrush current based on a potential difference between the voltage Vge and the voltage Vdc when the voltage Vge is clamped to the voltage Vdc in the period tp12. The resistor Roff has a function of preventing an inrush current based on a potential difference between the voltage Vge and 0 V when the voltage Vge is clamped to zero voltage in the period tp6. The resistor Ron may not be additionally provided, but the internal resistance of the switching element Q1 may be used. Similarly, the internal resistance of the switching element Q2 may be used without providing the resistance Roff additionally.

  Similarly, in FIG. 2, the resistor Ron has a function of preventing an inrush current based on a potential difference between the voltage Vge and the voltage VdcH when the voltage Vge is clamped to the voltage VdcH in the period tp12. The resistor Roff has a function of preventing an inrush current based on a potential difference between the voltage Vge and the voltage VdcL when the voltage Vge is clamped to the voltage VdcL in the period tp6. The resistor Ron may not be additionally provided, but the internal resistance of the switching element Q1 may be used. Further, the internal resistance of the switching element Q2 may be used without providing the resistor Roff additionally.

(Description of drive signal generation circuit)
Here, a calculation method in the drive signal generation circuit 18 will be described. FIG. 30 is a circuit diagram showing a configuration of the drive signal generation circuit used in FIGS. 1 and 2. The drive signal generation circuit 18 receives the drive signal DS and generates drive signals Q1S to Q4S. The drive signal generation circuit 18 shown in FIG. 30 includes circuit blocks 200, 300, 500, 600, and 700, an on / off determination unit 400, a NOT circuit 101, delay circuits 102 and 105, and AND logic circuits 103 and 106. And OR circuits 104 and 107.

  The circuit block 200 is a circuit block that generates a turn-on period of the switching element Q4. The circuit block 300 is a circuit block that generates a turn-on period of the switching element Q3. The circuit block 500 is a circuit block that generates a switching hold signal when the semiconductor switch 14 is turned off. The circuit block 600 is a circuit block that generates a switching hold signal when the semiconductor switch 14 is turned on. The circuit block 700 is a circuit block that selects the switching hold signal created in the circuit blocks 500 and 600.

  Next, the definition of the operation period will be described. FIG. 31 is a diagram defining a period for explaining the drive signal generation circuit of FIG. The waveforms of the switching elements Q1 to Q4 in the operation chart of FIG. 31 are the same as those in FIG. A total period of the period tp1 and the period tp12 in which the switching element Q1 is turned on is defined as a period ton, and a total period of the period tp6 and the period tp7 in which the switching element Q2 is turned on is defined as a period toff. The total period of the periods tp2 to tp5 during the transition to turn-off is defined as the period tf, and the total period of the periods tp8 to tp11 during the transition to the turn-on is defined as the period tr. A period tp5 for regenerating excitation power on the power supply side at turn-off is defined as a period tgoff1, and a period tp11 for regenerating excitation power on the power supply side at turn-on is defined as a period tgon. A period tp1 for exciting the reactor when the turn-off is continued is defined as a period teoff, and a period tp7 for exciting the reactor when the turn-on is continued is defined as a period teon.

  The process of calculating the drive signal Q4S by the circuit block 200 will be described with reference to FIG. The circuit block 200 includes an off period calculator 201, an off regeneration period calculator 202, an off excitation period calculator 203, a subtractor 204, and an adder 205.

  The drive signal Q4S is a signal that outputs H (logic high level) in the period tp1 to tp4 from FIG. The periods tp1 to tp4 are periods obtained by subtracting the period tgoff from the total period of the periods teoff and tf.

  The off period calculator 201 outputs a logic signal (H period is the period tf) that outputs the H level only during the periods tp2 to tp5. The period tf, that is, the period tp2 to tp5 in FIG. 31, is set to be less than half of the inversion period of the period ton, that is, within the period tp2 to tp6. The inversion period of the period ton indicates the period tp2 to tp11, and the half period of the period tp2 to tp11 indicates the period tp2 to tp6. The reason for the half period is that the same operation and calculation are performed during the period tp7 to tp12 in FIG.

  The off regeneration period calculator 202 outputs a signal tgoff1 indicating a period during which the exciting power of the reactor Lg is regenerated to the power supply side. By setting the high period of the signal tgoff1 to be longer than the period when the current iLg reaches 0 A, it is possible to recover all the exciting power of the reactor Lg, and the recovery effect can be maximized.

  The off excitation period calculator 203 determines an initial excitation period of the reactor Lg corresponding to the period tp1. By providing this period, there is an effect of increasing the time for extracting the accumulated charge of the capacitor Ciss in the period tp2 to tp5. The period tp1 needs to be set over the period tp1 from the timing (the boundary between the periods tp1 and tp2 in FIG. 31) at which the switching element Q1 is switched from turn-on to turn-off. Accordingly, the drive signal DS is input to the off excitation period calculator 203, and the period teoff is determined from the drive signal DS. The period teoff is set from the lower limit value zero, and the upper limit value is set in the total period of the period tp1 and the period tp12, which is a continuous turn-on period of the switching element Q1.

  The period tgoff1 is subtracted from the period tf by the subtractor 204 to calculate the period tgoff2. This corresponds to the period tp2 to tp4 in FIG. When the period tgoff2 and the period teoff are added by the adder 205, a signal Q4S that outputs an H level in the periods tp1 to tp4 can be calculated.

  Returning to FIG. 30, the process of calculating the drive signal Q3S by the circuit block 300 will be described. The circuit block 300 includes an on period calculator 301, an on regeneration period calculator 302, an on excitation period calculator 303, a subtractor 304, and an adder 305.

  The drive signal Q3S is a signal that outputs an H level in the period tp7 to tp11 from FIG. Periods tp7 to tp11 are periods obtained by subtracting tgoff from the total period of teoff and tf.

  The ON period calculator 301 outputs a logic signal (H period is the period tr) that outputs an H level only during the period tp8 to tp11. The period tr, that is, the period tp8 to tp11 in FIG. 31, is set to be equal to or less than half of the inversion period of the period ton, that is, within the period tp7 to tp11, as described above.

  The on-regeneration period calculator 302 outputs a signal tgon1 indicating a period during which the exciting power of the reactor Lg is regenerated to the power supply side. By setting the high period of the signal tgon1 to be longer than the period in which the current iLg reaches 0 A, it is possible to recover all the exciting power of the reactor Lg, and the recovery effect can be maximized.

  The ON excitation period calculator 303 determines an initial excitation period of the reactor Lg corresponding to the period tp7. By providing this period, there is an effect of shortening the charging period to the capacitor Ciss in the period tp8 to tp11. The period tp7 needs to be set over the period tp7 from the timing (the boundary between the periods tp7 and tp8 in FIG. 31) at which the switching element Q2 switches from turn-on to turn-off. Accordingly, the drive signal DS is input to the ON excitation period calculator 303, and the period teon is determined from the drive signal DS. The setting range of the period teon is set from the lower limit value zero, and the upper limit value is set in the total period of the period tp6 and the period tp7 which is a continuous turn-on period of the switching element Q2.

  The subtractor 304 subtracts the period tgon1 from the period tr to calculate the period tgon2. The period tgon2 corresponds to the periods tp8 to tp10 in FIG. When the period tgon2 and the period teon are added by the adder 305, a signal Q3S that outputs an H level in the periods tp7 to tp10 can be calculated.

  The on / off determination unit 400 receives the drive signal DS and determines the periods tp1 to tp6 shown in FIG. 31 or the periods tp7 to tp12 shown in FIG. 31 in real time. When it is determined that it exists in the period tp1 to tp6, the signal Judge is set to logic 1, and it is determined that it is the regenerative operation period at the time of turn-off. If it is determined that it exists in the period tp7 to tp12, the signal Judge is set to logic 0, and it is determined that it is a regenerative operation period at turn-on.

  Next, determination of the timings tf1 and tf2 at the time of turn-off will be described. The circuit block 500 outputs a signal for temporarily stopping the turn-off operation based on the result of comparing various waveforms with the reference signal. This corresponds to the period tp3 of the switching element Q1 in FIG.

  In the present embodiment, the various waveforms are the gate current ig, the collector current ic, the gate-emitter voltage Vge, and the collector-emitter voltage Vce of the semiconductor switch 14, which are used as extraction signals. In the present embodiment, a signal for temporarily stopping the turn-off operation is generated using one of the four types of extraction signals.

  The circuit block 500 includes comparators 501 to 504. When detecting the gate current, the gate current ig and the threshold value ig_th are input to the comparator 501. When the turn-off operation starts in the period tp2 in FIG. 31, the current ig gradually decreases. When the current ig falls below the threshold value ig_th, the signal Vig1 becomes H level, and after having held the H level for a certain period, becomes L level. The fixed period during which the signal Vig1 is at the H level is set so as not to be longer than (tf−tgoff1).

  When detecting the collector current, the collector current ic and the threshold value ic_th are input to the comparator 502. When the turn-off operation starts in the period tp2 in FIG. 31, the collector current ic gradually decreases. When the collector current ic falls below the threshold value ic_th, the signal Vic1 becomes H level, and after having held the H level for a certain period, becomes L level. The fixed period during which the signal Vic1 is at the H level is set not to be longer than (tf−tgoff1).

  When detecting the gate-emitter voltage, the gate-emitter voltage Vge and the threshold value Vge_th are input to the comparator 503. When the turn-off operation starts in the period tp2 in FIG. 31, the voltage Vge gradually decreases. When the voltage Vge falls below the threshold value Vge_th, the signal Vvge1 becomes H level, and after having held the H level for a certain period, becomes L level. The fixed period during which the signal Vvge1 is at the H level is set not to be longer than (tf−tgoff1).

  When detecting the collector-emitter voltage, the collector-emitter voltage Vce and the threshold value Vce_th are input to the comparator 504. When the turn-off operation starts in the period tp2 in FIG. 31, the collector-emitter voltage Vce gradually increases. When the collector-emitter voltage Vce exceeds the threshold value Vce_th, the signal Vvce1 becomes H level, and after maintaining the H level for a certain period, becomes L level. The fixed period during which the signal Vvce1 is at the H level is set not to be longer than (tf−tgoff1).

  Note that the time when the output signal Vig1 of the comparator 501, the output signal Vic1 of the comparator 502, the output signal Vvge1 of the comparator 503, and the output signal Vvce1 of the comparator 504 become H level corresponds to the time tf1 in FIG. Then, the time at which the signal becomes the L level again after having been at the H level for a certain period corresponds to the time tf2 in FIG.

  On the other hand, the circuit block 600 outputs a signal for temporarily stopping the turn-on operation. This corresponds to the period tp9 of the switching element Q2 in FIG. Signals (extraction signals) used for detection are a gate current ig, a collector current ic, a gate-emitter voltage Vge, and a collector-emitter voltage Vce as in the turn-off state. Similarly to the turn-off, the circuit block 600 generates a signal for temporarily stopping the turn-off operation using one of the four kinds of extraction signals.

  The circuit block 600 includes comparators 601 to 604. When detecting the gate current, the gate current ig and the threshold value ig_th are input to the comparator 601. When the turn-on operation starts in the period tp8 in FIG. 31, the current ig gradually increases. When the current ig exceeds the threshold value ig_th, the signal Vig2 becomes H level, and after having held the H level for a certain period, becomes L level. The predetermined period during which the signal Vig2 outputs H level is set not to be longer than (tf−tgon1).

  When detecting the collector current, the collector current ic and the threshold value ic_th are input to the comparator 602. When the turn-on operation starts in the period tp8 of FIG. 31, the collector current ic gradually increases. When the collector current ic exceeds the threshold ic_th, the signal Vic2 becomes H level, and after having held the H level for a certain period, becomes L level. The fixed period during which the signal Vic2 outputs H level is set not to be longer than (tf−tgon1).

  When detecting the gate-emitter voltage, the gate-emitter voltage Vge and the threshold value Vge_th are input to the comparator 603. When the turn-on operation starts in the period tp2 in FIG. 31, the voltage Vge gradually increases. When the voltage Vge exceeds the threshold value Vge_th, the signal Vvge2 becomes H level, and becomes L level after maintaining the H level for a certain period. The fixed period during which the signal Vvge2 is at the H level is set not to be longer than (tf−tgon1).

  When the collector-emitter voltage is detected, the collector-emitter voltage Vce and the threshold value Vce_th are input to the comparator 604. When the turn-off operation starts in the period tp2 in FIG. 31, the voltage Vce gradually decreases. When the voltage Vce falls below the threshold value Vce_th, the signal Vvce2 becomes H level, and after having held the H level for a certain period, becomes L level. The fixed period during which the signal Vvce2 outputs H level is set not to be longer than (tf−tgon1).

  Note that the time when the output signal Vig2 of the comparator 601, the output signal Vic2 of the comparator 602, the output signal Vvge2 of the comparator 603, and the output signal Vvce2 of the comparator 604 become H level corresponds to the time tr1 in FIG. The time at which the signal becomes the L level again after having been at the H level for a certain period corresponds to tr2 in FIG.

  Here, the threshold values input to the circuit block 500 and the comparators constituting the circuit block 600 are the same value. This is because the switching hold operation is performed in order to reduce the switching speed at the time of turn-off / turn-on switching, and the threshold value is most effective when both are the same.

  The circuit block 700 selects a switching hold signal at turn-on and a switching hold signal at turn-off. The circuit block 700 includes selectors 701 and 703, multipliers 702 and 704, and a NOT circuit 705.

  The selector 701 receives the output signal Vig1 of the comparator 501, the output signal Vic1 of the comparator 502, the output signal Vvge1 of the comparator 503, and the output signal Vvce1 of the comparator 504, and selects one pending signal. In this embodiment, the selection of four signals Vig1, Vic1, Vvge1, and Vvce1 is arbitrary. The selected signal Q1_tr1 is multiplied by the signal Judge and the multiplier 702 to calculate the signal Q1_tr2. The signal Judge is a logic 1 during the turn-off period, and is valid at the turn-off time. Thereby, a switching hold signal can be generated.

  The selector 703 receives the output signal Vig2 of the comparator 601, the output signal Vic2 of the comparator 602, the output signal Vvge2 of the comparator 603, and the output signal Vvce2 of the comparator 604, and selects one pending signal. In the present embodiment, the selection of four signals Vig2, Vic2, Vvge2, and Vvce2 is arbitrary. The selected signal Q2_tr1 is multiplied by the signal Judge1 obtained by inverting the signal Judge by the NOT circuit 705 by the multiplier 704, and the signal Q2_tr1 is calculated. The signal Judge1 becomes a logic 1 during the turn-on period and is valid at the turn-on time. Thereby, a switching hold signal can be generated.

  Next, generation of the signals Q1S and Q2S will be described. For the drive signal DS, basically, the same polarity signal becomes the drive signal Q1S of the switching element Q1, and the opposite polarity signal becomes the drive signal Q2S of the switching element Q2. The drive signal is generated by delaying the signal having the same polarity and the signal having the opposite polarity as described below.

  The delay of the signal Q1S will be described. The delay circuit 105 and the AND logic circuit 106 generate a signal ton2 obtained by delaying the drive signal DS by the delay time tr only at the rising edge. The AND logic circuit 106 receives the drive signal DS and the signal ton1 obtained by delaying the drive signal DS by the delay circuit 105 by the delay time tr. Thereby, the rising edge of the signal ton2 can be delayed from the rising edge of the drive signal DS by the sum of the periods tp8 to tp11 shown in FIG. 31 (delay time tr). The delay time tr is a value set by the on-period calculator 301 described above.

  The delay of the signal Q2S will be described. The polarity of the drive signal DS is inverted by the NOT circuit 101 to generate a signal toff1. Then, the delay circuit 102 and the AND logic circuit 103 generate a signal toff3 that is delayed only by the delay time tf. The AND logic circuit 103 receives the signal toff1 and the signal toff2 obtained by delaying the signal toff1 by the delay circuit t by the delay time tf. Thereby, the rising edge of the signal toff3 can be delayed from the falling edge of the drive signal DS by the sum of the periods tp2 to tp5 (delay time tf) shown in FIG. Note that the delay time tf is a value set by the off-period calculator 201 described above.

  The signal ton2 calculated by the AND logic circuit 106 and the signal Q1_tr2 described above are input to the OR circuit 107 to generate the signal Q1S. The signal ton2 is a signal for continuing the turn-on, and the signal Q1_tr2 is a signal for adjusting the switching speed when the signal is turned on from the turn-off.

  The signal toff3 calculated by the AND logic circuit 103 and the signal Q2_tr2 described above are input to the OR circuit 104 to generate the signal Q2S. The signal toff3 is a signal for continuing the turn-off, and the signal Q2_tr2 is a signal for adjusting the switching speed when the signal Q2_tr2 is turned off from the turn-on.

  In this way, by delaying the rise of the signal Q1S by the delay time tr from the rise of the drive signal DS, the above-described regenerative operation at the turn-on is realized by providing the periods tp7 to tp11. Further, by delaying the rising edge of the signal Q2S by the delay time tf from the rising edge of the inverted signal toff1 of the drive signal DS, the above-described regenerative operation at the turn-off time is realized by providing the periods tp1 to tp5.

(Summary)
As described above, in this embodiment, when the semiconductor switch 14 is turned on, reactive power is supplied to the reactor, electric charges are accumulated in the input capacitor 13 with the reactive power, and the remaining reactive power is regenerated to the power source.

  Further, when the semiconductor switch 14 is turned off, the charge accumulated in the input capacitor 13 is propagated as reactive power of the reactor and regenerated to the power supply side. As described above, the gate drive capacity can be reduced by supplying the stored charge to the input capacitor 13 and using the regenerative operation to the power source side using the reactive power of the reactor.

  Further, when the semiconductor switch 14 is turned on, the detected signal Vig1, Vic1, Vvge1, Vvce1 is compared with the threshold value of the selected signal, and the switching element Q1 is switched to turn it on. Reduce the switching speed.

  Similarly, when the semiconductor switch 14 is turned off, any one of the signals Vig2, Vic2, Vvge2, and Vvce2 is compared with the threshold value of the selected signal, and the switching at the moment when the switching is performed by switching the switching element Q2. Reduce the speed.

  By reducing the switching speed for a moment only at the time of turn-on / turn-off switching, low noise can be realized due to the influence of soft switching.

  As described above, the gate drive circuit according to the present embodiment can simultaneously realize a reduction in the capacity of the gate power supply by the regenerative operation and a low noise drive by changing the switching speed.

  That is, at the time of turn-on and turn-off, the charge of the semiconductor switch 14 that is driven by using the exciting power of the inductor element 8 is charged and discharged, and at the same time, the exciting power is regenerated to the power source side to Can be significantly reduced.

  Further, since the voltage for exciting the inductor element 8 by turning on the switching elements Q3 and Q4 is arbitrary, the voltages of the DC power supply 19 and the DC power supply 20 can be set to arbitrary voltages.

  Further, the switching elements Q3 and Q4 are turned on to excite the inductor element 8, and the gate capacitance Ciss of the semiconductor switch 14 is charged / discharged using the exciting power of the inductor element 8, thereby enabling high-speed switching and switching loss. To reduce.

  In the turn-off operation period, the switching element Q1 is repeatedly turned on and off in a predetermined period to interrupt the turn-off operation, thereby temporarily reducing the drain-source voltage rising speed of the semiconductor switch 14 and reducing noise. In the turn-on operation period, the switching element Q2 is repeatedly turned on and off in a predetermined period, and the turn-on operation is interrupted to temporarily reduce the falling speed of the drain-source voltage and reduce noise. be able to.

Embodiment 2. FIG.
(Feed forward generation of switching hold signal)
In the first embodiment, the detection signals Vig1, Vic1, Vvge1, and Vvce1 are compared with a predetermined threshold value to switch the turn-off and turn-on of the switching element Q1 in order to temporarily reduce the switching speed when the semiconductor switch 14 is turned on. It was. In addition, the detection signals Vig2, Vic2, Vvge2, and Vvce2 are compared with a predetermined threshold value to switch the turn-off and turn-on of the switching element Q2 in order to temporarily reduce the switching speed when the semiconductor switch 14 is turned off. A feedback method is adopted for generating these signals.

  However, in the feedback method, due to the influence of the delay of the detector, there is a possibility that the timing at which the semiconductor switch 14 is turned on and turned off and the point at which the switching element Q1 or Q2 is turned on and off are shifted. As this error increases, the effect of reducing noise decreases.

  In the present embodiment, switching between turn-on and turn-off of switching element Q1 or Q2 is determined based on a predetermined feedforward amount.

  The operating principle at turn-on and turn-off is the same as that of the first embodiment, and the description is omitted.

  FIG. 32 is a diagram illustrating a configuration of a drive signal generation circuit used in the second embodiment. Compared with the drive signal generation circuit 18 of the first embodiment, the drive signal generation circuit 18A does not include the circuit blocks 500, 600, and 700, and includes a turn-on transient switching generator 801 and a turn-off transient switching generator 802. The point is different.

  In addition, since the control block diagram is the same as that of the first embodiment, the generation process of the signal Q3S and the generation process of the signal Q4S are the same as those of the first embodiment. Hereinafter, generation of signals Q1S and Q2S will be described, and description of generation of signals Q3S and Q4S will be omitted.

(Generation of signal Q1S)
After generating the signal ton2 as in the first embodiment, the signal Q1_tr3 for reducing the switching speed is generated, and the signal ton2 and the signal Q1_tr3 are input to the OR circuit 107 to generate the signal Q1S. The signal Q1_tr3 is generated by a turn-on transient switching generator 801.

  The turn-on transient switching generator 801 receives a signal indicating the period tf, and sets a period (period tp3) during which the switching element Q1 is turned on in the period tf, that is, the period tp2 to tp4 in FIG. The timing for switching the signal Q1S to the H level (tf1 in FIG. 31) is generated based on the threshold voltage of the gate-emitter voltage of the driving semiconductor switch, and the H level output period is an arbitrary value within a range not exceeding the period tf. To do.

(Generation of signal Q2S)
After generating the signal toff3 as in the first embodiment, the signal Q2_tr3 for reducing the switching speed is generated, and the signal toff3 and the signal Q2_tr3 are input to the OR circuit 104 to generate the signal Q2S. Signal Q2_tr3 is generated by a turn-off transient switching generator 802.

  The turn-off transient switching generator 802 receives a signal indicating the period tr, and sets a period (period tp9) during which the switching element Q2 is turned on in the period tr, that is, the period tp8 to tp10 in FIG. The timing for switching the signal Q2S to the H level (tr1 in FIG. 31) is generated based on the threshold voltage of the gate-emitter voltage of the driving semiconductor switch, and the H level output period is an arbitrary value within a range not exceeding the period tr. To do.

  As described above, in the second embodiment, based on the control system shown in FIG. 32, the transient switching timings and periods of the switching elements Q1 and Q2 are determined according to the predetermined feedforward amount, and the signals Q1S, Q2S, Q3S, Q4S is generated to drive the gate circuit.

  In the present embodiment, similarly to the first embodiment, it is possible to simultaneously realize the reduction in the capacity of the gate power supply by the regenerative operation and the low noise driving by changing the switching speed.

  In the second embodiment, in addition to the effects of the first embodiment, switching from the feedback control method of the first embodiment to the feedforward control, the switching timing of the turn-on and turn-off of the semiconductor switch 14, the switching element Q1, and the switching element The transient switching timing of Q2 can be ideally matched. That is, the influence of detection delay can be reduced.

Embodiment 3 FIG.
(Regenerative operation at turn-off / turn-on only)
In Embodiments 1 and 2, the regenerative operation is performed both at turn-on and at turn-off, but the regenerative operation may be performed only for the turn-off operation. In this embodiment, the case where the regenerative operation is performed only in the turn-off operation will be described.

  Since the circuit configuration is the same as that of the first embodiment, description thereof is omitted. The single power supply configuration is the configuration shown in FIG. 2, and the dual power supply configuration is the configuration shown in FIG.

  FIG. 33 is an operation chart when the regenerative operation is performed only in the turn-off operation. At the turn-on time, the operation in the periods tp8 to tp12 described in the first embodiment is omitted and only the period tp8 is provided. The switching element Q3 is always turned off because the excitation of the inductor 8 and the charging operation to the input capacitor 13 are not required when the switching element Q3 is turned on.

  The regenerative operation at the time of turn-off and the switching hold operation, that is, the operation principle in the period tp1 to tp6 in FIG.

  The turn-on operation is only a switching operation from the period tp7 to the period tp8. After the switching element Q2 is turned off, the switching element Q1 is turned on. At this time, in the single power supply configuration of FIG. 2, the voltage Vdc is clamped to the gate voltage, and in the dual power supply configuration of FIG. 3, the voltage VdcH is clamped to the gate voltage. Since the power supplied at this time is consumed by the turn-on resistor 5, the gate drive capacity increases as compared with the first embodiment.

  That is, the difference from Embodiment 1 is that the period tr (FIG. 31) in the turn-on period is omitted.

  In the first embodiment, the drive signal generation circuit applied in this case eliminates the delay of the signal ton2 in the AND logic circuit 106 by setting the period tr to 0 in the ON period calculator 301 in FIG. In the circuit block 600, the signals Vig2, Vic2, Vvge2, and Vvce2 are all 0, and the signal Q2_tr2 is 0. In this case, the signal Q2S can ignore the delay of the period tr and the influence of the switching hold signal, and realizes the operation chart shown in FIG.

  In the present embodiment, the turn-on operation is described as constant voltage driving, which is a known technique. However, the switching element Q1 and the resistor Ron that contribute to the turn-on are, for example, a constant current circuit (International Publication WO2014 / 123046) or a soft gate circuit ( (Japanese Patent Laid-Open No. 2007-116900). Thereby, the switching characteristic at the time of turn-on can be improved, and the low loss and the low noise effect at the time of turn-on can be enhanced.

  It is also possible to perform a regenerative operation only in the turn-on operation. FIG. 34 is an operation chart when the regenerative operation is performed only in the turn-on operation. At the turn-off time, the operation in the periods tp2 to tp5 described in the first embodiment is omitted and only the period tp6 is provided. In order to coincide with the description of the first embodiment, FIG. 34 is represented by omitting the periods tp2 to tp5. The switching element Q4 is always turned off because the discharge operation of the input capacitor 13 due to the excitation of the inductor 8 is not required at the time of turn-off.

  The regenerative operation at the time of turn-on and the switching hold operation, that is, the operation principle in the period tp7 to tp12 in FIG.

  The turn-off operation is only a switching operation from the period tp1 to the period tp6. The switching element Q2 is turned on after the switching element Q1 is turned off. At this time, in the single power supply configuration of FIG. 2, 0V is clamped to the gate voltage, and in the dual power supply configuration of FIG. 3, the voltage -VdcL is clamped to the gate voltage. Since the power supplied at this time is consumed by the turn-off resistor 6, the gate drive capacity increases as compared with the first embodiment.

  In this case, the difference from the first embodiment is that the period tf (FIG. 31) in the turn-off period is omitted.

  In the first embodiment, the drive signal generation circuit applied in this case eliminates the delay in the AND logic circuit 103 of the signal toff1 by setting the period tf to 0 in the off period calculator 201. In the circuit block 500, the signals Vig1, Vic1, Vvge1, and Vvce1 are all 0, and the signal Q1_tr2 is 0. In this case, the signal Q1S can ignore the delay of the period tf and the influence of the switching suspension signal, and realizes the operation chart shown in FIG.

  In this embodiment, the turn-off operation has been described as a constant voltage drive that is a known technique. However, the switching element Q2 and the resistor Roff that contribute to the turn-off are configured by, for example, a soft turn-off circuit (Japanese Patent Laid-Open No. 2010-109545). You may do it. Thereby, the switching characteristic at the time of turn-off can be improved, and the low loss and the low noise effect at the time of turn-off can be enhanced.

  As described above, in the present embodiment, the mode of performing the regenerative operation only in the turn-on operation or the regenerative operation only in the turn-off operation has been described.

  Although the capacity of the gate power supply is increased as compared with the first embodiment by not performing the regenerative operation of either the turn-on or the turn-off, it can be combined with another driving method for improving the switching performance. As a result, the entire gate circuit can be designed to achieve both a reduction in gate capacitance and a low loss and low noise in the driving semiconductor switch.

Embodiment 4 FIG.
In the above first to third embodiments, the gate drive circuit has been described. In this embodiment, a power conversion device to which the above gate drive circuit is applied is described. Here, an inverter circuit will be described as an example of the power conversion device.

  FIG. 35 is a diagram illustrating an inverter circuit according to the third embodiment. 35, an inverter circuit 900 includes a U-phase leg composed of an arm Q-U1 and an arm Q-U2, a V-phase leg composed of an arm Q-V1 and an arm Q-V2, and an arm Q- W1 and W phase leg composed of the arm Q-W2. Inverter circuit 900 converts the power of DC power supply 901 into AC power and transmits the AC power to AC load 902. In FIG. 35, a motor is described as an example of the AC load 902, but other loads may be used.

  Here, the switching elements of the arms Q-U1, Q-U2, Q-V1, Q-V2, Q-W1, Q-W2 are voltage-driven semiconductor switching elements (semiconductor elements to be driven), respectively. The gate drive circuits GDU1, GDU2, GDV1, GDV2, GDW1, and GDW2 perform the on / off operation. Each of the gate drive circuits GDU1, GDU2, GDV1, GDV2, GDW1, and GDW2 has the same configuration as the gate drive circuit 100 shown in FIG. The gate drive circuits GDU1, GDU2, GDV1, GDV2, GDW1, GDW2 receive the drive signals DSU1, DSU2, DSV1, DSV2, DSW1, DSW2 from the control circuit 903 as the drive signals DS in FIG. Drive the switch.

  Next, the operation will be described. Each operation of the gate driving circuit is the same as that shown in the first embodiment, and a description thereof is omitted. The arms Q-U1, Q-U2, Q-V1, Q-V2, Q-W1, and Q-W2 are driven by the voltages output from the corresponding gate drive circuits, and operate as inverters. A conventional inverter circuit control method (for example, a control method described in JP 2010-154582 A) can be applied to the inverter circuit used here.

  Here, an example in which the gate drive circuit shown in FIG. 1 is used as the gate drive circuit is shown, but the gate drive circuit shown in FIG. 2 may be used.

  Here, an inverter circuit as an example of a power conversion device is shown, but the present invention is not limited to this, and any power conversion device that performs on / off drive by a gate drive circuit may be used.

  For example, the gate drive circuit may be mounted on a power converter that converts an AC voltage of an AC power source into a DC voltage and controls the current of the AC power source at a high power factor. FIG. 36 is a diagram illustrating a converter circuit according to the third embodiment.

  36, converter circuit 900A includes a U-phase leg composed of arm Q-U1 and arm Q-U2, a V-phase leg composed of arm Q-V1 and arm Q-V2, and arm Q- A W-phase leg composed of W1 and arm Q-W2, a reactor U, a reactor V, and a reactor W are included. Converter circuit 900 </ b> A converts the power of AC power supply 904 into DC power and transmits the DC power to DC load 905. Converter circuit 900A adjusts the voltage applied to reactor U, reactor V, and reactor W, and controls the current of AC power supply 904 to a high power factor with respect to the AC voltage.

  The gate drive circuits GDU1, GDU2, GDV1, GDV2, GDW1, GDW2 receive the drive signals DSU1, DSU2, DSV1, DSV2, DSW1, DSW2 from the control circuit 903 as the drive signals DS in FIG. Drive the switch.

  Similar to the inverter circuit 900, the other operations of the converter circuit 900A used here are general operations, and a description thereof will be omitted. A conventional inverter circuit control method (for example, a control method described in International Publication No. WO2015 / 045485) can be applied to the operation.

  Further, a gate drive circuit may be mounted on a chopper circuit that converts a DC voltage into a DC voltage. FIG. 37 is a diagram showing a configuration in which a gate drive circuit is applied to a chopper circuit.

  In FIG. 37, chopper circuit 900B includes a leg composed of arm Q1B and arm Q2B, and a reactor 908. The chopper circuit 900B is a boost chopper circuit that boosts a voltage from a DC power supply 906 to a DC load 907 to transmit electric power.

  The gate drive circuits GDQ1 and GDQ2 receive the drive signals DSQ1 and DSQ2 from the control circuit 903B as the drive signals DS in FIG. 1, respectively, and drive the respective semiconductor switches accordingly.

  Although FIG. 37 shows a step-up chopper circuit as an example, a step-down chopper circuit, a step-up / step-down chopper circuit, or the like may be used.

  Like the inverter circuit 900 and the converter circuit 900A, the operation of the chopper circuit 900B used here is a general operation and will not be described. The conventional chopper circuit control method (for example, the control method described in International Publication WO2016 / 075996) can be applied to the operation.

(Summary of embodiment)
(1) The gate drive circuit 100 shown in the first to third embodiments and FIGS. 1-10, 30, 31, and 32 includes switching elements Q1 to Q4, an inductor element 8, and a drive signal generation circuit 18. Switching element Q1 is connected between the positive terminal of DC power supply 10 and the first node. Switching element Q2 is connected between the first node and the negative terminal of DC power supply 10. Switching element Q3 is connected between the positive terminal of DC power supply 10 and the second node. Switching element Q4 is connected between the second node and the negative terminal of DC power supply 10. The inductor element 8 is connected between the first node and the second node. The drive signal generation circuit 18 controls the on / off operation of each of the switching elements Q1 to Q4.

  The first node 7 is connected to the gate terminal of the semiconductor switch 14. The negative terminal 17 of the DC power supply 10 is connected to the emitter terminal of the semiconductor switch 14. The drive signal generation circuit 18 controls the switching elements Q1 to Q4 so that the switching element Q2 is fixed on and the switching elements Q1, Q3, and Q4 are fixed off when the semiconductor switch 14 is fixed to OFF. At the time of fixing, the switching elements Q1 to Q4 are controlled so that the switching element Q1 is fixed on and the switching elements Q2, Q3, Q4 are fixed off. When the semiconductor switch 14 is turned off, the drive signal generating circuit 18 turns on the switching element Q4 and excites the inductor element 8 for a predetermined first period from the state where the switching element Q1 is fixed, and then the switching element Q1. Is turned off for a predetermined second period, the gate accumulated charge is discharged, the switching element Q1 is turned on for a predetermined third period, the gate accumulated charge is interrupted, and the switching element Q1 is turned off again for a predetermined fourth period. Thereafter, the switching element Q4 is fixed off, the switching element Q2 is fixed on, and the semiconductor switch 14 is fixed off.

  With such a configuration, there are obtained effects such as 1) power recovery effect at turn-off, 2) reduction of switching loss due to high-speed switching, and 3) noise reduction due to low-speed switching near the threshold Vth of the semiconductor switch. It is done.

  (2) Gate drive circuit 100 shown in the first to third embodiments and FIGS. 1-4, 11-16, 30, 31, and 32 is connected between the positive terminal of DC power supply 10 and the first node. Switching element Q1, switching element Q2 connected between the first node and the negative terminal of DC power supply 10, and switching element Q3 connected between the positive terminal of DC power supply 10 and the second node A switching element Q4 connected between the second node and the negative terminal of the DC power supply 10, an inductor element 8 connected between the first node and the second node, and switching elements Q1 to Q1. And a drive signal generation circuit 18 for controlling each on / off operation of Q4. The first node is connected to the gate terminal of the semiconductor switch 14. The negative terminal of the DC power supply 10 is connected to the emitter terminal of the semiconductor switch 14. The drive signal generation circuit 18 controls the switching elements Q1 to Q4 so that the switching element Q2 is fixed on and the switching elements Q1, Q3, and Q4 are fixed off when the semiconductor switch 14 is fixed to OFF. At the time of fixing, the switching elements Q1 to Q4 are controlled so that the switching element Q1 is fixed on and the switching elements Q2, Q3, Q4 are fixed off. When the semiconductor switch 14 is turned on, the drive signal generation circuit 18 turns on the switching element Q3 from the state in which the switching element Q2 is fixed and then excites the inductor element 8 for a predetermined first period. Is turned off for a predetermined second period, the gate is charged, the switching element Q2 is turned on for a predetermined third period, charging of the gate is interrupted, and the switching element Q2 is turned off again for a predetermined fourth period, Thereafter, the switching element Q3 is fixed off, the switching element Q1 is fixed on, and the semiconductor switch 14 is fixed on.

  With such a configuration, there are obtained effects such as 1) power recovery effect at turn-off, 2) reduction of switching loss due to high-speed switching, and 3) noise reduction due to low-speed switching near the threshold Vth of the semiconductor switch. It is done.

  (3) The gate drive circuit 100 shown in the first to third embodiments and FIGS. 1, 2, 3, 17, 18-23, 30, 31, and 32 is provided between the positive electrode of the DC power supply 19 and the first node. The switching element Q1 connected to the switching element Q2, the switching element Q2 connected between the first node and the negative terminal of the DC power supply 20, and the switching connected between the positive terminal of the DC power supply 19 and the second node. Element Q3, switching element Q4 connected between the second node and the negative terminal of DC power supply 20, inductor element 8 connected between the first node and the second node, and switching element Q1 Drive signal generating circuit 18 for controlling each on / off operation of .about.Q4. The DC power supply 19 and the DC power supply 20 are connected in series, the first node is connected to the gate terminal of the semiconductor switch 14, and the negative terminal of the DC power supply 19 and the positive terminal of the DC power supply 20 are both emitter terminals of the semiconductor switch 14. Connected to. When the semiconductor switch 14 is fixed to OFF, the drive signal generation circuit 18 controls the switching elements Q1 to Q4 so that the switching element Q2 is fixed to ON and the switching elements Q1, Q3, and Q4 are fixed to OFF. When the on state is fixed, the switching elements Q1 to Q4 are controlled so that the switching element Q1 is fixed on and the switching elements Q2, Q3, and Q4 are fixed off. When the semiconductor switch 14 is turned off, the drive signal generating circuit 18 turns on the switching element Q4 and excites the inductor element 8 for a predetermined first period from the state where the switching element Q1 is fixed, and then the switching element Q1. Is turned off for a predetermined second period, the gate accumulated charge is discharged, the switching element Q1 is turned on for a predetermined third period, the gate accumulated charge is interrupted, and the switching element Q1 is turned off again for a predetermined fourth period. Thereafter, the switching element Q4 is fixed off, the switching element Q2 is fixed on, and the semiconductor switch 14 is fixed off.

  With such a configuration, there are obtained effects such as 1) power recovery effect at turn-off, 2) reduction of switching loss due to high-speed switching, and 3) noise reduction due to low-speed switching near the threshold Vth of the semiconductor switch. It is done.

  (4) The gate drive circuit 100 shown in the first to third embodiments and FIGS. 1, 2, 3, 17, 24-29, 30, 31, and 32 is provided between the positive electrode of the DC power supply 19 and the first node. The switching element Q1 connected to the switching element Q2, the switching element Q2 connected between the first node and the negative terminal of the DC power supply 20, and the switching connected between the positive terminal of the DC power supply 19 and the second node. Element Q3, switching element Q4 connected between the second node and the negative terminal of DC power supply 20, inductor element 8 connected between the first node and the second node, and switching element Q1 Drive signal generating circuit 18 for controlling each on / off operation of .about.Q4. The DC power supply 19 and the DC power supply 20 are connected in series, the first node is connected to the gate terminal of the semiconductor switch 14, and the negative terminal of the DC power supply 19 and the positive terminal of the DC power supply 20 are both emitter terminals of the semiconductor switch 14. Connected to. The drive signal generation circuit 18 controls the switching elements Q1 to Q4 so that the switching element Q2 is fixed on and the switching elements Q1, Q3, and Q4 are fixed off when the semiconductor switch 14 is fixed to OFF. At the time of fixing, the switching elements Q1 to Q4 are controlled so that the switching element Q1 is fixed on and the switching elements Q2, Q3, Q4 are fixed off. When the semiconductor switch 14 is turned on, the drive signal generation circuit 18 turns on the switching element Q3 from the state in which the switching element Q2 is fixed and then excites the inductor element 8 for a predetermined first period. Is turned off for a predetermined second period, the gate is charged, the switching element Q2 is turned on for a predetermined third period, charging of the gate is interrupted, and the switching element Q2 is turned off again for a predetermined fourth period, Thereafter, the switching element Q3 is fixed off, the switching element Q1 is fixed on, and the semiconductor switch 14 is fixed on.

  With such a configuration, there are obtained effects such as 1) power recovery effect at turn-off, 2) reduction of switching loss due to high-speed switching, and 3) noise reduction due to low-speed switching near the threshold Vth of the semiconductor switch. It is done.

  (5) Switching elements Q1 to Q4 shown in the first to third embodiments and FIGS. 1 and 2 are semiconductor elements having parasitic diodes.

  With such a configuration, an effect of increasing the power recovery effect can be obtained by generating a return path that bypasses the exciting current of the inductor.

  (6) The gate drive circuit 100 shown in the first to third embodiments and FIGS. 1 and 2 includes the first resistor connected between the switching element Q1 and the first node, the switching element Q2, and the first And a second resistor connected between the nodes and having a resistance value different from that of the first resistor.

  With such a configuration, an inrush current when the switching element Q1 is turned on when the semiconductor switch is turned on can be prevented without connecting a resistor to the regenerative path. Similarly, the switching element Q2 is turned on when the semiconductor switch is turned off. The effect that the inrush current when turning on can be prevented can be obtained.

  (7) The drive signal generation circuit 18 shown in the first and third embodiments and FIGS. 1, 2, 30, and 32 includes a gate-source voltage, a gate current, a gate voltage, a drain current, a source current of the semiconductor switch 14. The switching elements Q1 to Q4 are controlled based on at least one detection value of the drain-source voltage.

  By adopting such a configuration, it is possible to obtain an effect that a regenerative operation in consideration of robustness is possible by adding a feedback function.

  (8) As shown in the first and third embodiments and FIGS. 30, 31, and 32, the drive signal generation circuit 18 ends the second period before the discharge current of the gate accumulated charge becomes zero.

  By adopting such a configuration, by limiting the time until the semiconductor switch is completely turned off, when the switching element Q1 is turned off again, the speed can be reduced and noise can be reduced. Is obtained.

  (9) The drive signal generation circuit 18 shown in the first and third embodiments and FIGS. 30, 31, and 32 has the second period before the gate voltage of the semiconductor switch 14 drops to the threshold voltage of the semiconductor switch 14. To finish.

  By adopting such a configuration, by limiting the time until the semiconductor switch is completely turned off, when the switching element Q1 is turned off again, the speed can be reduced and noise can be reduced. Is obtained.

  (10) In the first period (tp7) shown in the first to third embodiments and FIGS. 30, 31, and 32, the exciting power of the inductor element 8 is equal to or higher than the gate capacity charging power necessary for turning on the semiconductor switch 14. Set to

  With such a configuration, the turn-on can be realized only with the reactive power of the inductor, so that the power source capacity can be reduced (active gate function).

  (11) The drive signal generation circuit 18 shown in the first and third embodiments and FIGS. 30, 31, and 32 ends the second period (tp8) before the gate charging current becomes zero.

  By adopting such a configuration, an effect of reducing noise (active gate function) can be obtained by reducing the speed before the semiconductor switch is turned on.

  (12) In the drive signal generation circuit 18 shown in the first and third embodiments and FIGS. 30, 31, and 32, the gate voltage of the semiconductor switch 14 is set to the threshold voltage of the semiconductor switch 14 during the second period (tp8). End by reaching.

  By adopting such a configuration, an effect of reducing noise (active gate function) can be obtained by reducing the speed before the semiconductor switch is turned on.

  (13) The starting point of the first period (tp1) shown in the first to third embodiments and FIGS. 30, 31, and 32 is a predetermined period from the turn-off timing of the semiconductor switch 14 that is predetermined as the control signal. Is set.

  With such a configuration, an effect is obtained that the switching speed can be adjusted without changing the turn-off period.

  (14) The starting point of the first period (tp7) shown in the first to third embodiments and FIGS. 30, 31, and 32 is a predetermined period from the turn-on timing of the semiconductor switch 14 that is predetermined as a control signal. Is set.

  With such a configuration, it is possible to obtain an effect that the switching speed can be adjusted without changing the turn-on period.

  (15) The drive signal generation circuit 18 shown in the first and third embodiments and FIGS. 30, 31, and 32 determines the start timing and end timing of the third period, the gate-source voltage of the semiconductor switch 14, the gate current, the gate The calculation is performed by comparing at least one value of the voltage, drain current, source current, and drain-source voltage with a corresponding threshold value.

  With such a configuration, it is possible to obtain an effect that the switching speed can be adjusted without changing the turn-on period.

  (16) The start timing and end timing of the third period (tp9) shown in the second embodiment and FIG. 32 are determined in advance based on the threshold voltage of the gate-source voltage of the semiconductor switch 14.

  With such a configuration, it is possible to obtain an effect that the switching speed can be adjusted without changing the turn-on period.

  (17) The drive signal generation circuit 18 shown in the first and third embodiments and FIGS. 30 and 31 sets the start timing and end timing of the third period (tp9) as the gate-source voltage of the semiconductor switch 14, the gate current, The calculation is performed by comparing at least one of gate charge, drain current, source current, drain-source voltage, and parasitic inductance voltage of the semiconductor switch 14 with a corresponding threshold value.

  With such a configuration, it is possible to obtain an effect that the switching speed can be adjusted without changing the turn-on period.

  (18) The start timing and end timing of the third period (tp9) shown in the second embodiment and FIG. 32 are determined in advance based on the threshold voltage of the gate-source voltage of the semiconductor switch 14.

  With such a configuration, it is possible to obtain an effect that the switching speed can be adjusted without changing the turn-on period.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

  10, 19, 20, 901, 906 DC power supply, 5 turn-on resistance, 6 turn-off resistance, 7, 9 AC output node, 8 inductor, 11 regeneration circuit, 12 clamp circuit, 13 input capacitance, 14 semiconductor switch, 15 emitter terminal, 16 positive terminal, 17 negative terminal, 18, 18A drive signal generation circuit, 21 neutral point, 100, GDQ1, GDQ2, GDU1, GDU2, GDV1, GDV2, GDW1, GDW2 gate drive circuit, 101, 705 NOT circuit, 104, 107 OR circuit, 102, 105 delay circuit, 103, 106 AND logic circuit, 200, 300, 500, 600, 700 circuit block, 201 off period calculator, 202 off regeneration period calculator, 203 off excitation period calculator, 204 304 subtractor 205 30 Adder, 301 ON period calculator, 302 ON regeneration period calculator, 303 ON excitation period calculator, 400 ON / OFF determiner, 501, 502, 503, 504, 601, 602, 603, 604 comparator, 701 703 selector, 702, 704 multiplier, 801, 802 generator, 900 inverter circuit, 900A converter circuit, 900B chopper circuit, 902 AC load, 903, 903B control circuit, 904 AC power supply, 905, 907 DC load, 908, Lg, U, V, W reactor, Ciss capacity, Q1-Q4 switching element.

Claims (18)

A gate drive circuit for driving a semiconductor switch,
Multiple switches,
An inductor element connected to the gate terminal of the semiconductor switch;
A drive signal generation circuit for controlling on / off operations of the plurality of switches,
The plurality of switches are:
A first switch connected between the positive terminal of the DC power source and the first node;
A second switch connected between the first node and a negative terminal of the DC power source;
A third switch connected between a positive terminal of the DC power source and a second node;
A fourth switch connected between the second node and a negative terminal of the DC power source;
The inductor element is connected between the first node and the second node;
The drive signal generation circuit controls the on / off operation of each of the first to fourth switches,
The first node is connected to the gate terminal of the semiconductor switch, the negative terminal of the DC power supply is connected to the emitter terminal of the semiconductor switch,
The drive signal generation circuit is at least one of when the semiconductor switch is turned on and turned off.
A first excitation period for exciting the inductor element;
A first transmission period for transmitting the excitation power of the first excitation period to the gate terminal of the semiconductor switch;
A second excitation period for re-exciting the inductor element after the first transmission period;
The first to fourth switches are controlled so as to provide a second transmission period for transmitting excitation power during the second excitation period to the gate terminal of the semiconductor switch. Gate drive circuit. Before Symbol drive signal generating circuit,
When the semiconductor switch is fixed to OFF, the first to fourth switches are controlled so that the second switch is fixed to ON and the first, third, and fourth switches are fixed to OFF,
When the semiconductor switch is fixed on, the first to fourth switches are controlled so that the first switch is fixed on, and the second, third, and fourth switches are fixed off;
When the semiconductor switch is turned off, from the state in which the first switch is fixed to ON, the fourth switch is turned on to excite the inductor element for a predetermined first period, and then the first switch is turned on. The gate accumulated charge is discharged by turning off the second period for a predetermined period, the discharge of the gate accumulated charge is interrupted by turning on the first switch for the third period set in advance, and the first switch is again set to the fourth fourth period. 2. The gate drive circuit of a semiconductor switch according to claim 1, wherein the semiconductor switch is fixed off by setting the period off and then fixing the fourth switch off and fixing the second switch on. 3. Before Symbol drive signal generating circuit,
When the semiconductor switch is fixed to OFF, the first to fourth switches are controlled so that the second switch is fixed to ON and the first, third, and fourth switches are fixed to OFF,
When the semiconductor switch is fixed on, the first to fourth switches are controlled so that the first switch is fixed on, and the second, third, and fourth switches are fixed off;
When the semiconductor switch is turned on, from the state in which the second switch is fixed on, the third switch is turned on and the inductor element is excited for a predetermined fifth period, and then the second switch is turned on. The gate is charged by turning off only for a predetermined sixth period, the second switch is turned on only for a predetermined seventh period, charging to the gate is interrupted, and the second switch is set again for an eighth period. 2. The gate drive circuit for a semiconductor switch according to claim 1, wherein the semiconductor switch is fixed on by turning off and then fixing the third switch off and fixing the first switch on. 3. The DC power source includes a first DC power source and a second DC power source connected in series,
The first switch is connected between a positive electrode of the first DC power source and the first node;
The second switch is connected between the first node and a negative terminal of the second DC power source,
The third switch is connected between a positive terminal of the first DC power source and the second node;
The fourth switch is connected between the second node and a negative terminal of the second DC power supply;
4. The gate of the semiconductor switch according to claim 2, wherein a negative terminal of the first DC power source and a positive terminal of the second DC power source are both connected to an emitter terminal of the semiconductor switch. 5. Driving circuit.   4. The gate drive circuit for a semiconductor switch according to claim 2, wherein each of the first to fourth switches is a semiconductor element having a parasitic diode. 5. A first resistor connected between the first switch and the first node;
4. The gate drive circuit for a semiconductor switch according to claim 2, further comprising a second resistor connected between the second switch and the first node and having a resistance value different from that of the first resistor. 5. .   The drive signal generation circuit includes the first to first voltages based on at least one detection value among a gate-source voltage, a gate current, a gate voltage, a drain current, a source current, and a drain-source voltage of the semiconductor switch. The gate drive circuit of the semiconductor switch according to claim 2 or 3, which controls the fourth switch.   The semiconductor drive gate drive circuit according to claim 2, wherein the drive signal generation circuit ends the second period before the discharge current of the gate accumulated charge becomes zero.   3. The gate drive circuit for a semiconductor switch according to claim 2, wherein the drive signal generation circuit ends the second period before the gate voltage of the semiconductor switch drops to a threshold voltage of the semiconductor switch.   4. The gate drive circuit for a semiconductor switch according to claim 3, wherein in the fifth period, the exciting power of the inductor element is set to be equal to or higher than a gate capacity charging power required for turning on the semiconductor switch. 5.   The gate drive circuit for a semiconductor switch according to claim 3, wherein the drive signal generation circuit ends the sixth period before the charge current of the gate becomes zero.   4. The gate drive circuit for a semiconductor switch according to claim 3, wherein the drive signal generation circuit ends the sixth period until a gate voltage of the semiconductor switch reaches a threshold voltage of the semiconductor switch. 5.   3. The gate drive circuit for a semiconductor switch according to claim 2, wherein a start point of the first period is set over a predetermined period from a turn-off timing of the semiconductor switch that is predetermined as a control signal.   4. The semiconductor switch gate drive circuit according to claim 3, wherein a start point of the fifth period is set over a predetermined period from a turn-on timing of the semiconductor switch predetermined as a control signal. 5.   The drive signal generation circuit sets the start timing and end timing of the third period at least one of a gate-source voltage, a gate current, a gate voltage, a drain current, a source current, and a drain-source voltage of the semiconductor switch. 3. The gate drive circuit for a semiconductor switch according to claim 2, wherein calculation is performed by comparing one value with a corresponding threshold value.   The drive signal generation circuit determines the start timing and end timing of the seventh period according to the gate-source voltage, gate current, gate charge, drain current, source current, drain-source voltage of the semiconductor switch, and parasitic of the semiconductor switch. 4. The gate drive circuit for a semiconductor switch according to claim 3, wherein calculation is performed by comparing at least one value of the inter-inductance voltage with a corresponding threshold value.   3. The gate drive circuit for a semiconductor switch according to claim 2, wherein a start timing and an end timing of the third period are predetermined based on a threshold voltage of a gate-source voltage of the semiconductor switch.   4. The gate drive circuit for a semiconductor switch according to claim 3, wherein the start timing and end timing of the seventh period are predetermined based on a threshold voltage of a gate-source voltage of the semiconductor switch.

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