JP4873317B2 - Inverter device - Google Patents

Description

  The present invention relates to an inverter device that converts and outputs a DC voltage to an AC voltage having an arbitrary voltage and an arbitrary frequency by performing pulse width modulation control, and more particularly to an inverter device having a function of reducing generated noise at the time of zero voltage output. is there.

  In an inverter device in which semiconductor switching elements such as IGBT transistors are connected in series in the upper and lower directions to constitute each output phase, direct current is controlled by so-called pulse width modulation (hereinafter referred to as PWM) control in which the upper and lower transistors are alternately turned on and off. The bus voltage is converted into an AC voltage with an arbitrary voltage and frequency. As the upper and lower transistors are turned on and off, each phase output terminal voltage of the inverter device is between the positive potential (hereinafter referred to as P potential) and the negative potential (hereinafter referred to as N potential) of the DC bus voltage. Move alternately. As each phase output terminal voltage moves, the winding terminal voltage of the motor connected to the output terminal and the cable line voltage connecting both terminals also move.

  By the way, a large stray capacitance exists between each phase winding of the motor and the motor frame (usually the frame is grounded). In addition, there is a non-negligible level of stray capacitance between the output terminal of the inverter device and each phase cable line connecting between the winding terminals of the motor and between the ground. When a shielded cable line is used, the stray capacitance is particularly large. For this reason, in the inverter device, as the fluctuation amount of the total value of the U-phase, V-phase, and W-phase three-phase output terminal voltages increases, the potential fluctuation of the entire motor winding increases and the potential fluctuation of the entire cable line also increases. . The electric potential fluctuation of the entire motor winding and the electric potential fluctuation of the entire cable line become noise generation sources as they are, and the magnitude of the fluctuation amount also leads to the magnitude of the generated noise. Further, the larger the potential fluctuation amount, the larger the output current (hereinafter referred to as leakage current) charged / discharged from the inverter device to the stray capacitance. Recently, in order to reduce noise emitted from the inverter device by PWM control, the number of cases where shielded cable wires are applied to output cable wires is increasing. Is also evident.

  In order to suppress such leakage current and generated noise, a method using a common mode choke or an active filter is usually employed between the input and output of the inverter device. This is because the overall size of the inverter device system is reduced. This hinders cost reduction.

  In order to solve this problem, the configuration shown in FIGS. 3 and 4 is given as a first conventional example. This is an example of a three-level inverter device, but paying attention to the fact that the total sum of the three phases of the three-phase sine wave voltage vector is always zero, the three-phase total sum is zero in the PWM conversion output voltage. It shows that it can be a point voltage, and shows a specific method for generating such a gate signal (an ON / OFF drive signal of an IGBT transistor). As a result, the three-phase total sum of the output voltages of each phase is always fixed to zero, in other words, the neutral point voltage, and the occurrence of leakage current can be suppressed (see, for example, Patent Document 1).

Further, as a second conventional example, this is also an example of a three-level inverter device, but two output terminals of the three-level inverter device 101 as shown in FIG. 5 are connected to the motor 102, and the remaining one output terminal. Is connected to an output line 104 not connected to a load, and the output line 104 is bundled together with the other two output lines connected to the electric motor 102, insulated near the electric motor 102, and fixed to the ground. . Each phase output terminal of the three-level inverter device has a + E state that outputs a P potential, a 0 state that outputs an intermediate potential of a DC bus voltage, and a -E state that outputs an N potential. The voltage is controlled. Since this embodiment is an example of a single phase output, only the U phase and the V phase are connected to the winding terminals of the motor 102. And the W-phase output terminal that is not connected to the motor 102 is controlled to an output voltage value that suppresses fluctuations in the total voltage value of the U-phase, V-phase, and W-phase, and the fluctuation amount is suppressed, This is to reduce generated noise and leakage current. FIG. 6 shows the switching patterns of the U phase, the V phase, and the W phase. In FIG. 6, V1, V2, and V3 indicate the output terminal voltages of the U phase, V phase, and W phase, and V12 indicates the UV line voltage of the output terminal with respect to the V phase output terminal, V Reference _{numeral 123} denotes the total value of the three-phase output terminal voltages (see, for example, Patent Document 2).

Japanese Patent Laid-Open No. 10-23760 (FIGS. 1 and 2) JP 2004-56882 A (FIGS. 1 and 3)

However, since the first conventional example is a technique based on a three-level inverter device, there is a problem that it cannot be applied to a two-level inverter device that does not have three potential output functions.
In the second conventional example, an extra output terminal for one phase is required, so if it is a three-phase inverter device, it is necessary to prepare a four-phase inverter device, and the inverter device itself is special and expensive. There is a problem. In addition, since there are individual variations in switching operation delay time in the semiconductor switching elements constituting each phase, it is difficult to completely match the on / off timing between the phase connected to the motor and the phase not connected. There is also a problem that the effect of suppressing noise is halved due to a shift in on-off timing.

  As another problem, when the inverter device itself or a peripheral device is concerned about malfunction, the object to be suppressed is not the average amount of generated noise and leakage current, but the instantaneous value. In each embodiment, the suppression of instantaneous values may not be targeted. The instantaneous value increases when the output terminal voltages of the U-phase, V-phase, and W-phase simultaneously move in the same direction between both PN potentials. Noise and leakage current generated at the moment of simultaneous movement The value is the largest value. Each phase output terminal voltage of the inverter device is obtained by control based on each phase PWM voltage command value obtained by comparing the sine wave voltage command value for each phase and the triangular wave (common to each phase). When the amplitude value of the voltage command is zero (hereinafter referred to as zero voltage command), the PWM voltage command values of the respective phases coincide with each other, so that the output terminal voltages of the respective phases simultaneously move in the same direction between the PN potentials. It will be. Therefore, particularly at the time of zero voltage command, there arises a problem that the value of generated noise and leakage current becomes large.

An object of the present invention is to provide a two-level PWM inverter device that suppresses generation of noise and leakage current, and in particular, to provide an inverter device that can suppress instantaneous values of noise and leakage current at the time of zero voltage output. There is.

In order to solve the above-mentioned problem, in the inverter device according to claim 1, two semiconductor switching elements are connected in series, and both the semiconductor switching elements are complementarily controlled (if one is turned on, the other is turned off). An inverter device having two or more output phases for converting and outputting a DC bus voltage to an arbitrary voltage and an AC voltage having an arbitrary frequency, the PWM signal generating means for outputting a PWM signal according to a voltage command, and both the semiconductors An on-delay time setting means for setting an on-delay time, which is a period during which both switching elements are turned off (hereinafter referred to as on-delay time), to the PWM signal and outputting it as an on-off command signal for each of the semiconductor switching elements. in the inverter device, when an oN command of the upper stage-side semiconductor switching elements of the on-off command signal Setting a time difference when the difference between the on-instruction time of lower-side semiconductor switching elements of each phase same, every upper side ON command start time of the semiconductor switching ON command start time of the element and the lower-side semiconductor switching elements between the phases mutually and The time difference is characterized in that there is no time period during which the upper semiconductor switching element of any phase and the lower semiconductor switching element of any other phase are simultaneously turned on.
In order to prevent each phase output terminal voltage from moving simultaneously between PN potentials in the same direction at the time of zero voltage command in which each phase voltage command value matches, the on command time of the upper semiconductor switching element of the on / off command signal If the phase of the ON / OFF command signal is shifted relative to each other while maintaining the difference between the ON command time of the semiconductor switching element and the lower semiconductor switching element at the same value for each phase (in other words, each phase Set a time difference between them). In this case, since the output terminal voltage for each phase is the same value for all three phases, the line voltage value is zero, and the phase voltage is also considered to be zero when viewed as a three-phase AC voltage (the DC component of the phase voltage is the common mode value for all phases). So it can be ignored). In this way, it is possible to suppress the generated noise and the leakage current at the time of zero voltage command.
However, while maintaining the difference between the ON command time of the upper semiconductor switching element and the ON command time of the lower semiconductor switching element at the same value for each phase, simply shifting the phase of the ON / OFF command signal, An interval occurs in which both the semiconductor switching element and the lower semiconductor switching element of the other phase are turned on. During this period, since a DC bus voltage is applied between the arbitrary phase and the other phase, a steep increase / decrease current is generated. In this case, since the zero voltage command is used, it is ideal that the output current is zero, but a large ripple current (however, the DC component is zero) is generated. Therefore, by setting the set time difference as a time difference that does not cause a period in which the upper semiconductor switching element of an arbitrary phase and the lower semiconductor switching element of another arbitrary phase are simultaneously turned on, generation of ripple current is also prevented. ing.

According to a second aspect of the present invention, in the inverter device, the means for setting the time difference includes the timing of starting the off command of the upper semiconductor switching element in the phase in which the upper semiconductor switching element is turned off the latest and the lower semiconductor switching the earliest. It is characterized in that a time difference equal to or longer than the OFF operation delay time of the semiconductor switching element is provided between the turn-on command start time of the lower semiconductor switching element in the phase where the element is turned on.
By providing a time difference more than the OFF operation delay time of the semiconductor switching element, it prevents the lower stage semiconductor switching element from turning on before the upper stage semiconductor switching element is turned off, thereby preventing the generation of ripple current. It is to do.
Further, when the output current exists and flows through the upper semiconductor switching element, when the upper semiconductor switching element is turned off, the output terminal voltage of the phase moves from the P-side potential to the N-side potential. To do. On the other hand, when the lower semiconductor switching element is turned on in the phase where the lower semiconductor switching element is turned on earliest, the output terminal voltage of the phase also moves from the P side potential to the N side potential. Therefore, a time difference larger than the OFF operation delay time of the semiconductor switching element is provided to prevent both phases from moving from the P-side potential to the N-side potential at the same time.

In the inverter device according to claim 3, the means for setting the time difference includes a timing of starting an off command of the lower semiconductor switching element in a phase in which the lower semiconductor switching element is turned off latest and an upper semiconductor switching earlier. It is characterized in that a time difference equal to or longer than the OFF operation delay time of the semiconductor switching element is provided between the turn-on command start time of the upper semiconductor switching element in the phase in which the element is turned on. This is based on the assumption that the output terminal voltage shifts from the N potential to the P potential.

5. The inverter device according to claim 4, wherein two semiconductor switching elements are connected in series, and both semiconductor switching elements are complementarily turned on / off to convert and output a DC bus voltage to an arbitrary voltage and an AC voltage having an arbitrary frequency. In the inverter device having two or more phases, only when the PWM signal generating means for outputting the PWM signal according to the voltage command and the timing phases of the rise and fall of the PWM signal of each phase all match, Rising and falling timing phases of the PWM signals of other phases are shifted with reference to the rising and falling timing phases of one of the phases of the PWM signal, and the rising edges of the PWM signals between the phases And time difference setting means for outputting a new PWM signal whose falling timing phase does not match , Selects the PWM signal in the case of the electric motor to the driving state, or a switch for selecting the new PWM signal in the case of the stop state of the motor, the semiconductor switching elements connected in series are both An on-delay time setting means for setting an on-delay time, which is an off-period, to the PWM signal or the new PWM signal and outputting it as an on-off command signal for the semiconductor switching element .

According to the present invention, using the two-level inverter device, there is an effect that the instantaneous value of noise and leakage current generated in PWM control can be suppressed, and the malfunction of the inverter device itself or peripheral devices can be suppressed. Further, in the present invention, a difficult operation of matching the timing at which the output terminal voltage of the inverter device changes to the P potential or the N potential between the phases is unnecessary.
In addition, according to the present invention, no special equipment is required to suppress the instantaneous values of noise and leakage current, and there is an effect that can be realized within the equipment of the existing inverter device.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is an overall configuration diagram of an inverter device corresponding to the first embodiment of the present invention. In FIG. 1, 1 is an AC power source, 2 is a rectifier, 3 is a smoothing capacitor (DC bus voltage source), 4 is a controller, 5 to 10 are IGBT transistors, 11 to 16 are freewheeling diodes, 17 is an electric motor, and 18 is a triangular wave. Generators 19 to 21 are comparators, 22 to 24 are time difference setting units for setting a time difference between the respective phases at the on-command start timing of each phase upper stage IGBT transistor and each phase lower stage IGBT transistor, 25 to 27 Is an on-delay time setting device, U * is a U-phase voltage command, V * is a V-phase voltage command, and W * is a W-phase voltage command.

  The controller 4 outputs sinusoidal voltage commands U *, V * and W * for each phase. At the time of zero voltage command, U *, V * and W * all have the same value. The phase voltage command values U *, V * and W * are respectively compared in magnitude with the triangular wave output from the triangular wave generator 18 in the comparators 19 to 21. The output from each comparator becomes each phase PWM signal (U **, V **, W **), but these PWM signals are input to the on-delay time setting devices 28 to 30 as they are during normal operation. In the on-delay time setting device, the PWM signal (U **, V **, W **) and the inverted PWM signal (/ U **, / V **, / W **) After a predetermined on-delay time (on-delay time) is set for each PWM signal, an on-off command signal (Ud **, Vd **, Wd **, / Ud **) is assigned to each IGBT transistor. , / Vd **, / Wd **).

On the other hand, at the time of zero voltage command, the time difference between the respective phases with respect to the ON command start timing of each phase upper stage IGBT transistor and each phase lower stage IGBT transistor from the controller 4 to the time difference setting units 22 to 24. Is instructed. In accordance with the instruction value from the controller 4, the time difference setting units 22 to 24 perform processing to shift the phase of the PWM signal input from the comparator. Then, the PWM signals (U ′ **, V ′ **, W ′ **) output from the time difference setting device and shifted in phase are turned on as they are in response to a switching command from the controller 4 to the switching devices 25 to 27. Input to delay time setting units 28 to 30. The controller 4 instructs the on-delay time setter to set the on-delay time (on-delay time) to be larger than the value in the normal operation, and the on-delay time corresponding to this is set to the on-delay time. Set by the setting device. Then, it is output to each IGBT transistor as an on / off command signal (Ud ′ **, Vd ′ **, Wd ′ **, / Ud ′ **, / Vd ′ **, / Wd ′ **).
If the on-delay time during normal operation can be extended to some extent, the PWM signal output from the time difference setting units 22 to 24 is always input to the on-delay time setting units 28 to 30. become.
The time difference between the phases is set according to the ON operation characteristics of the IGBT transistor to be used. For example, in the case of an on-pulse transmission system using two high voltage FETs (on-signal transmission and off-signal transmission FETs) as means for transmitting an on / off command signal, this is coupled with the characteristics of an IGBT transistor having a fast on operation. From the transmission of the ON command signal to the ON operation of the IGBT transistor can be completed in about 0.1 μs. Therefore, if a time difference of 0.1 μs or more is set between the phases, simultaneous ON between the phases can be prevented.

FIG. 2 shows a timing chart of each phase operation at the time of zero voltage command. Since each phase voltage command (U *, V *, W *) is a zero voltage command, the result of comparison with the triangular wave is a PWM signal (U **, V **, W **). U ′ **, V ′ **, and W ′ ** are obtained by shifting the phases of the PWM signals (U **, V **, and W **). In this example, U ** is left as it is, V ** is shifted backward by Δt, and W ** is shifted backward by 2 × Δt, but it is not limited to this example. On / off command signals (Ud ′ **, Vd ′ **, Wd ′ **) are obtained by setting an on-delay time td with respect to U ′ **, V ′ **, W ′ **. The ON / OFF command signals (/ Ud '**, / Vd' **, / Wd '**) are obtained by inverting' **, V '**, W' ** and setting the ON delay time td. is there. The on-delay time td in this example is obtained by adding 2 × Δt to the delay time td0 during normal operation (turn-off time toff <td0 of the IGBT transistor). Uo, Vo, Wo indicate the output terminal voltage of each phase. According to the on / off command signal, the on operation substantially coincides with the on command, but the off operation is delayed by toff from the off command. The hatched portion is a period in which both the upper and lower IGBT transistors are off. When the output current is zero, there is no voltage output during this period. Therefore, if Tp is the ON period of the upper IGBT transistor, Tn is the ON period of the lower IGBT transistor, and the triangular wave period is T, each of the output terminal voltages (average values) is equal to the DC bus voltage · (Tp −Tn) / T, the line output voltage value is zero, and the phase output voltage value is also zero.
In the above-described embodiment, all three phases have a duty of 50%. For example, even when the same offset amount is added to all three phases and all three phases have the same duty but not 50%, the line The inter-phase output voltage value can be set to zero and the phase output voltage value can be set to zero to obtain zero voltage output.

The W-phase has the slowest off command to the upper-stage IGBT transistor, and the U-phase has the earliest turn-on command to the lower-stage IGBT transistor. However, since there is a time difference td0 (delay time during normal operation) between the two command signals, the U-phase lower IGBT transistor is always turned on after the W-phase upper IGBT transistor is turned off. Similarly, the slowest turn-off command to the lower-stage IGBT transistor is the W-phase, and the fastest turn-on command to the upper-stage IGBT transistor is the U-phase. Later, the U-phase upper stage IGBT transistor is turned on. Accordingly, since no DC bus voltage is applied between the lines, the generation of ripple current can be prevented.
In this example, td = td0 + 2 × Δt, but it goes without saying that if td is larger than (td0 + 2 × Δt), the generation of ripple current can be prevented.

According to the present invention, in the two-level inverter device, the instantaneous value of noise and leakage current generated by PWM control can be suppressed, and no special equipment is required for suppressing the instantaneous value of noise and leakage current. The two-level inverter device can be applied as it is.

It is a schematic block diagram of the inverter apparatus which is embodiment of this invention. It is an operation | movement timing chart figure which is embodiment of this invention. It is a schematic block diagram of the 3 level inverter apparatus which is a 1st prior art example. It is the figure which showed the implementation flow of the 3 level inverter apparatus which is a 1st prior art example. It is a schematic block diagram of the 3 level inverter apparatus which is a 2nd prior art example. It is a switching pattern figure of the 3 level inverter apparatus which is a 2nd prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 AC power supply 2 Rectifier 3 Smoothing capacitor 4 Controllers 5-10 IGBT transistors 11-16 Freewheeling diode 17 Electric motor 18 Triangular wave generator 19-21 Comparator 22-24 Time difference setting device 25-27 Switching device 28-30 On-delay time setting Unit 101 Three-level inverter device 102 Motor 103 Floating capacitance 104 Output line 401 not connected to load Commercial power supply 402 Rectifier diode module 403, 404 Smoothing capacitor 405 Voltage type PWM converter 406 Induction motor 407 PWM control circuit 501 to 504 IGBT transistor 505 508 Free wheel diodes 509 and 510 Clamp diode 701 Voltage command selection unit 702 Gate pulse generation unit 703 Gate pulse processing unit 704 Pulse distribution unit

Claims (4)

An inverter device comprising two or more output phases in which two semiconductor switching elements are connected in series and the two semiconductor switching elements are complementarily controlled on and off to convert a DC bus voltage into an arbitrary voltage and an AC voltage of an arbitrary frequency. A PWM signal generating means for outputting a PWM signal in accordance with a voltage command, and an on-delay command for each of the semiconductor switching elements by setting an on-delay time, which is a period during which both the semiconductor switching elements are turned off, to the PWM signal. In an inverter device comprising on-delay time setting means for outputting as a signal,
When the difference between the ON command time of the upper semiconductor switching element of the ON / OFF command signal and the ON command time of the lower semiconductor switching element is the same for each phase, the ON command start time of the upper semiconductor switching element and the lower semiconductor switching element Means for setting a time difference between each phase for the ON command start time of
The inverter apparatus according to claim 1, wherein the time difference is a time difference without a period in which the upper semiconductor switching element of any phase and the lower semiconductor switching element of another arbitrary phase are simultaneously turned on. The means for setting the time difference includes the timing of starting the turn-off command of the upper semiconductor switching element in the phase in which the upper semiconductor switching element is turned off the latest and the lower semiconductor switching in the phase in which the lower semiconductor switching element is turned on earliest. 2. The inverter device according to claim 1, wherein a time difference equal to or longer than a delay time of turning off the semiconductor switching element is provided between the start time of the element and an on command. The means for setting the time difference includes the timing of starting the turn-off command of the lower semiconductor switching element in the phase in which the lower semiconductor switching element is turned off latest and the upper semiconductor switching in the phase in which the upper semiconductor switching element is turned on earliest. 2. The inverter device according to claim 1, wherein a time difference equal to or longer than a delay time of turning off the semiconductor switching element is provided between the start time of the element and an on command. An inverter device comprising two or more output phases in which two semiconductor switching elements are connected in series and the two semiconductor switching elements are complementarily controlled on and off to convert a DC bus voltage into an arbitrary voltage and an AC voltage of an arbitrary frequency. There,
PWM signal generating means for outputting a PWM signal according to the voltage command ;
Only when the rising and falling timing phases of the PWM signal of each phase are all the same, the rising and falling timing phases of one phase of the PWM signal of each phase are used as a reference, and the PWM signals of the other phases A time difference setting means for shifting the rising and falling timing phases of the PWM signal and outputting a new PWM signal in which the rising and falling timing phases of the PWM signals between the phases do not match;
A switch for selecting the PWM signal when the motor is in a driving state , or for selecting the new PWM signal when the motor is in a stop state ;
An on-delay time setting means for setting an on-delay time, which is a period in which both of the semiconductor switching elements connected in series are turned off, to the PWM signal or the new PWM signal and outputting it as an on-off command signal for the semiconductor switching element; , an inverter apparatus comprising: a.

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