JP2009060708A - Control method for double converter device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress surge voltage at the time of switching of the switching elements comprising a power conversion device and make it possible to use an element of low breakdown voltage. <P>SOLUTION: At Step S1, it is determined whether or not a turn-off command has been generated within a certain set time to a converter-side IGBT and an inverter-side IGBT. At Step S2, it is determined whether or not a turn-on command has been generated within a certain set time to the converter-side IGBT and the inverter-side IGBT. When a turn-off command or a turn-on command is generated within a certain set time, a command signal, whichever is later in rising or falling, is delayed by a certain time at Step S3. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a switch element control system applied to a double converter conversion device for converting from AC to DC and further to AC.

FIG. 5 shows a general example of a power conversion device for converting from alternating current to direct current, and further to alternating current, and its control block. 1 is a three-phase AC power supply (R phase, S phase, T phase), 2 is a conversion circuit (converter) that converts AC to DC, and IGBT (insulated gate bipolar transistor) Tr and diode Di are connected in reverse parallel. 6 arms. The conversion circuit 2 can control the DC voltage Ed and the AC currents (i _R , i _S , i _T ) by applying a switching element such as IGBT. Reference numeral 4 in FIG. 5 is a large-capacity capacitor constituting a DC circuit, and generally an electrolytic capacitor is applied. Reference numeral 3 denotes a conversion circuit (inverter) that converts direct current to alternating current, and controls the output voltage and output current (i _U , i _V , i _W ) together with the conversion circuit 2. The outputs U, V, W of the conversion circuit 3 are connected to a load such as a motor.

  Reference numeral 5 denotes a gate drive circuit for driving the IGBT, which is converted into a signal for actually driving the IGBT based on an ON / OFF command S output from the control circuit block 10. Similarly, an ON / OFF command S for each IGBT is generated from the control circuit 10 here for 12 signals (R1 to W2). Inside the control circuit 10, the signal (modulation signal) from the AC voltage (or AC current) command circuit 6 and the signal (carrier wave) from the triangular wave generation circuit 7 for PWM (pulse width modulation) are sent to the comparison circuit 8. The signal S is generated according to the magnitude relationship. Further, the inverted signal S (−) of the opposite arm side IGBT is generated by the inverting circuit 9.

  Fig. 6 shows a case where a power semiconductor module (2-in-1 module) with a built-in IGBT and diode for one phase is applied, and a one-phase structure of the converter-side module and the inverter-side module for one phase Indicates. 6A is a top view and FIG. 6B is a side view. MC is a module on the converter side, and MI is a module on the inverter side. The positive side terminals (C1 terminals) T1 and T2 and the positive side terminal T3 of the electrolytic capacitor 4 of the DC circuit are connected by a conductor 11. Further, the negative side terminals (E2 terminals) T4 and T5 of MI and the negative side terminal T6 of the electrolytic capacitor 4 of the DC circuit are connected by a conductor 12. The output terminals (E1C2 terminals) T7 and T8 of each module are connected to the R-phase power supply and the U-phase load, respectively. Further, a radiator 13 and a fan 14 are installed at the lower part of the module.

  FIG. 7 shows an example of a circuit in which the three stacks 15A, 15B, and 15C as described above form three phases. In this case, since the electrolytic capacitors in the DC circuit section are connected to each stack, three sets of 4A, 4B, and 4C are required, and the positive terminals and the negative terminals are connected to each other. Also, L1 to L6 in the figure represent wiring inductances between the electrolytic capacitors 4A, 4B, and 4C and the inverter modules MIa, MIb, and MIc. That is, the wiring inductance between the terminals T2 and T3 of the conductor 11 and the terminals T5 and T6 of the conductor 12 in FIG. Further, although there is a wiring inductance corresponding to the actual length between the terminals T1 and T2 and between T4 and T5, this inductance value is ignored as being zero for explanation.

The PWM control circuit of the power conversion circuit as shown in FIG. 5 is disclosed in, for example, Patent Document 1, and the wiring structure as in FIG. 6 is disclosed in, for example, Patent Document 2.
JP 2006-217776 A Japanese Patent Laid-Open No. 06-327266

FIG. 8 shows an operation example of a certain stack (R, U phase). This figure shows the state (b) after the commutation after the R2 IGBT and the U1 IGBT are turned on (a) after the R2 IGBT is turned off.
Now, when R2 is turned off, the current ic _R2 flowing therethrough is commutated to the diode of R1 and flows into the electrolytic capacitor 4A. At this time, a voltage is generated in the “+” direction of FIG. 8B in the wiring inductances L1 and L2 due to di / dt at the time of IGBT turn-off.

FIG. 9 shows waveforms of the voltage V _CE applied to R 2 and the IGBT current ic _R 2 at that time.
Here, the jumping voltage ΔV1 with respect to the DC voltage Ed of the electrolytic capacitor 4A is expressed by the following equation.
ΔV1 ＝ （L1 ＋ L2） ・ d ic _R2 / dt (1)

FIG. 10 shows another operation example. Here, a state (b) after commutation after the R2 IGBT and the U1 IGBT are turned off simultaneously from the R2 IGBT and the U1 IGBT is shown. When R2 is turned off, the current ic _R2 flowing therethrough is commutated to the diode R1 and flows into the electrolytic capacitor 4A. Further, at the turn-off of U1, the current i _CU1 flowing there is commutated to the diode of U2. At this time, due to di / dt at the time of IGBT turn-off, a voltage is generated in the “+” direction of FIG. 10B in the wiring inductances L1 and L2.

FIG. 11 shows waveforms of the voltage V _CE applied to R2 and the IGBT current ic _R2 at that time.
Here, the jumping voltage ΔV2 with respect to the DC voltage Ed of the electrolytic capacitor 4A is expressed by the following equation.
ΔV2 ＝ （L1 ＋ L2） ・ (dic _R2 / dt + di _CU1 / dt) (2)

That is, when i _CU1 ≈ ic _{R2 due to} the simultaneous interruption phenomenon as shown in FIG.
ΔV2 ≒ 2ΔV1
Thus, a jumping voltage that is about twice as large as that when the switching operation is performed independently in FIG. 8 is generated. As an example, if L1 = L2 = 50 nH, di / dt = 2000 A / μs, and Ed = 900 V, V _CEmax = 1300 V from the above equation (2), and a device with a withstand voltage of 1700 V class is required.

That is, unless a special restriction is provided at the time of control, the above-described simultaneous interruption phenomenon occurs, the surge voltage at the time of switching increases, and an element with a high breakdown voltage is required.
Therefore, an object of the present invention is to suppress a surge voltage at the time of switching and to apply a low withstand voltage element.

In order to solve such a problem, the present invention provides a power conversion device for converting from AC to DC, and further from DC to AC, and a capacitor is connected to the DC section to convert from AC to DC and from DC to AC. A second power conversion circuit for converting the capacitor and the direct current to the alternating current between the capacitor and the active switch element of the first power conversion circuit for converting the direct current to the direct current. In the control system of the double converter conversion device for controlling the power conversion device in which the common wiring section exists in the wiring between the active switch element of
A signal for turning on each active switch element of the first power conversion circuit and the second power conversion circuit is simultaneously generated within a set time, or each active switch of the first power conversion circuit and the second power conversion circuit A delay circuit for delaying one of the signals when a signal for turning off the element is simultaneously generated within a certain set time is provided.

  According to the present invention, since a surge voltage value generated at the time of switching is lowered, an IGBT or FWD chip having a low voltage rating can be applied, and a small and inexpensive system can be constructed.

FIG. 1 is a flowchart for explaining an embodiment of the present invention.
First, in step S1, it is determined whether or not a turn-off command is generated within a certain set time for the converter side IGBT and the inverter side IGBT. If not (N), the process proceeds to step S2. If it occurs (in the case of Y), the process proceeds to step S3. In step S2, it is determined whether a turn-on command is generated within a certain set time for the converter side IGBT and the inverter side IGBT. If Y, the process proceeds to step S3. If N, the process ends. In step S3, the signal with the later rising or falling timing is delayed by a certain set time.

  That is, in the double converter conversion system as shown in FIG. 6 in which the converter module and the inverter module are connected by common wiring between the electrolytic capacitors, the converter side IGBT and the inverter side IGBT in the same stack are simultaneously switched within a predetermined time ( When it is determined that the turn-off or turn-on) is performed, one of the signals is delayed so that the simultaneous interruption phenomenon does not occur and the surge voltage at the time of switching is suppressed.

  FIG. 2A delays the control signal U when the control signal U of the inverter side IGBT rises or falls within a set time T with respect to the rise or fall timing of the control signal R of the converter side IGBT. An example circuit is shown. 2B shows that when the control signal R of the converter side IGBT rises or falls within a certain set time T with respect to the rise or fall timing of the control signal U ′ of the inverter side IGBT. The circuit example which delays is shown.

  In FIG. 2A, 20A is a one-shot circuit, which outputs an H (high) level signal at the rising edge of the R-phase signal (R). Here, the switch 21A is a switch that is turned on when the U-phase signal (U) is at the H level. That is, when the U-phase signal (U) is in the H state and the R-phase signal (R) changes from L (low) to H, a one-shot signal for time T is output and input to the OR circuit 22. The Similarly, an H-level one-shot signal is output and input to the OR circuit 22 at the falling timing of the R-phase signal (R) (the timing at which the R-phase signal (R) changes from H to L) by the circuit 20B. The

  On the other hand, the one-shot circuit 23A operates by rising and outputs an L level signal. Here, the switch 24A is a switch that is turned on when the U-phase signal (U) is at the L level. That is, a one-shot signal for time T is output and input to the OR circuit 25 at a timing when the R-phase signal (R) changes from L to H while the U-phase signal (U) is in the L state. Similarly, an L-level one-shot signal is output by the circuit 23B at the falling timing of the R-phase signal (R) (the timing at which the R-phase signal (R) changes from H to L) and input to the OR circuit 25. The

Here, the OR circuit 25 outputs the U-phase signal (U) to the circuit 23A or the circuit 23B when the U-phase signal (U) rises from L to H while the circuits 23A and 23B are L. It is connected for the purpose of forcibly delaying rising to H until the output becomes H.
Similarly, the OR circuit 22 also outputs the U-phase signal (U) to the circuit 20A or the circuit 20B when the U-phase signal (U) falls from H to L while the circuits 20A and 20B are H. Are connected for the purpose of forcibly delaying falling to L until the output of L becomes low.

  26A and 26B are pull-down resistors provided to force the outputs of the circuits 20A and 20B to L when the input of the switch circuits 21A and 21B is open (when the U-phase signal (U) is L). ing. Also, 27A and 27B are pull-up resistors, for forcibly setting the outputs of the circuits 23A and 23B to H when the inputs of the switch circuits 24A and 24B are open (when the U-phase signal (U) is H). Is provided.

FIG. 2A shows a signal processing circuit when the change of the R-phase signal (R) is earlier in timing than the change of the U-phase signal (U). On the other hand, FIG. 2B shows a signal processing circuit when the change of the U-phase signal (U) from FIG. 2A is earlier in timing than the change of the R-phase signal (R), and the relationship between the U-phase and the R-phase is shown. The circuit configuration is exactly the same only by reversing.
Finally, the circuit of FIG. 2A and the circuit of FIG. 2B are configured to be connected in series, and the U-phase signal (U ′) and the R-phase signal (R ′) are supplied to the buffer circuits 28A and 28B and the inverter circuit 29A By 29B, the upper arm side IGBT drive signal (U1 ′, R1 ′) and the lower arm side IGBT drive signal (U2 ′, R2 ′) of each phase are obtained.

FIG. 3 shows time charts of FIGS. 2A and 2B.
When the R phase signal (R) falls at time t0 and the U phase signal (U) falls at time t1 within the period T, the fall of the U phase signal (U) is delayed until time t2. (Signal U '). Similarly, when the U-phase signal (U) rises at time t3 and the R-phase signal (R) rises at time t4 within the period T, the rise of the R-phase signal (R) is delayed until time t5. (Signal R ′). In addition, at time t6 and t7, the target signal does not exist within the period T, so the signal remains as it is.

FIG. 4 shows a system configuration diagram according to the present invention.
Reference numerals 31, 32, and 33 in the figure indicate a delay circuit in which the circuit of FIG. 2A and the circuit of FIG. 2B are connected in series, and this point is only different from the conventional example shown in FIG. Here, 10A, 10A ′, 10A ″ are inverter module control circuits, and 10B, 10B ′, 10B ″ are converter module control circuits.
In the above description, signal delay is realized by hardware, but it goes without saying that it may be realized by software.

Flowchart explaining the embodiment of the present invention Circuit diagram showing an example of a signal delay circuit according to the present invention. Circuit diagram showing another example of a signal delay circuit according to the present invention Time chart explaining circuit operation of FIGS. 2A and 2B System configuration diagram of double converter according to the present invention System diagram of conventional double converter Switching element module arrangement of FIG. 5 and its wiring structure diagram Main circuit configuration diagram of FIG. FIG. 7 is an operation explanatory diagram when a certain switching element is cut off in a certain phase. Current and voltage waveform diagrams for explaining the operation of FIG. Explanation of operation when switching elements are simultaneously shut off in a certain phase in FIG. Current and voltage waveform diagrams for explaining the operation of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... AC power source, 2 ... Conversion circuit (converter), 3 ... Conversion circuit (inverter), 4 ... Electrolytic capacitor, 5 ... Gate drive circuit, 6 ... Command circuit, 7 ... Triangle wave generation circuit, 8 ... Comparison circuit, 9, 29A, 29B ... Inverting circuit, 10-10B "... Control circuit, 20A, 20B, 23A, 23B ... One-shot circuit, 21A, 21B, 24A, 24B ... Switch, 22, 25 ... OR circuit, 26A, 26B ... Pull-down resistor 27A, 27B ... pull-up resistors, 28A, 28B ... buffer circuits, 31-33 ... delay circuits.

Claims (1)

A power converter for converting from AC to DC, and further from DC to AC, with a capacitor connected to the DC section, and using an active switch element for each power conversion circuit for converting from AC to DC and from DC to AC, Common wiring between the capacitor and the active switch element of the first power conversion circuit that converts AC to DC, and between the capacitor and the active switch element of the second power conversion circuit that converts DC to AC In the control system of the double converter conversion device that controls the power conversion device in which the section exists,
A signal for turning on each active switch element of the first power conversion circuit and the second power conversion circuit is simultaneously generated within a set time, or each active switch of the first power conversion circuit and the second power conversion circuit A control system for a double converter conversion device, comprising a delay circuit for delaying one signal when signals for turning off an element are simultaneously generated within a set time.

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