JP6705234B2 - Inverter control method - Google Patents

Description

The present invention relates to a control method for an inverter device, and more particularly to a control method for reducing dead time in an inverter device configured by a plurality of single-phase full bridge circuits using switching elements.

FIG. 7 is a waveform diagram at the time of turn-on and turn-off when an IGBT element is used as a switching element. VGE is the gate-emitter voltage, VCE is the collector-emitter voltage, and IC is the collector current. As a characteristic of most of the IGBT devices, the time relationship between the turn-on time ton and the turn-off time toff has a relationship of turn-on time ton<turn-off time toff. For example, in the case of an IGBT element having a rated voltage of 1200 V and a rated current of 300 A, when an IGBT element having a time difference of about toff-ton=200 ns is used in the inverter device, the inverter top and bottom are based on this time difference. The dead time is set by considering the turn-on time, turn-off time, temperature dependence, etc. that prevent a short circuit, and by appropriately determining the safety factor.

Inverter devices used for induction heating devices, etc., are connected to a DC power supply with a plurality of single-phase inverters (section units A to D), and the drive order is set to section units A to D for each inverter. It is known from Patent Document 1 that it is possible to cope with a high frequency by sequentially driving.

Patent No. 4761696

FIG. 8 shows an inverter circuit of a single-phase full bridge configuration, which is a single-phase full bridge including a U-phase arm in which IGBT elements Tu1 and Tu2 are connected in series and a V-phase arm in which IGBT elements Tv1 and Tv2 are connected in series. It is composed. In addition to IGBTs, power semiconductors such as FETs and SiC are used as switching elements used in the inverter circuit, but in the following, IGBT elements will be taken as an example.

In the circuit configuration shown in FIG. 8, in order to prevent the IGBT element short circuit between the upper and lower sides in each phase arm, it is necessary to provide a sufficient dead time for driving the IGBT elements so as not to short the arms. For this reason, there is a problem that both the upper and lower IGBT elements are off, and a period during which no electric power is supplied to the load side occurs and the output voltage drops. This effect is particularly large in an inverter device driven at high frequency. Note that Patent Document 1 does not mention reduction of dead time.

An object of the present invention is to provide a control method of an inverter device that reduces dead time and shortens a non-conduction period of a switching I element.

The present invention relates to a single-phase full-bridge inverter device in which three inverter circuits that output U-phase and V-phase voltages are connected in parallel to a forward conversion circuit.
Among the three inverter circuits connected in parallel, the first inverter circuit is controlled to output a voltage from the U phase to the V phase, and the second inverter circuit is controlled to output the voltage from the V phase to the U phase. Is controlled so that the third inverter circuit outputs a voltage from the U phase to the V phase, whereby each inverter circuit is controlled to sequentially output different phase voltages. Control method for the inverter device.

The present invention is characterized in that each phase of the AC output of each inverter circuit is provided with an inductance.

Further, according to the present invention, at the time of commutation from the inverter circuit outputting the voltage to the inverter circuit outputting the next phase voltage, the [turn-off time toff-turn-on time ton] of the switching element characteristic of each inverter circuit is It is characterized in that a gate signal is applied to a switching element on the commutation side in dead time.

Further, according to the present invention, in each of the three inverter circuits, a smoothing capacitor is connected to the DC side, and a reactor is separately connected between each smoothing capacitor and the forward conversion circuit to suppress a short circuit current. It is characterized by.

As described above, according to the present invention, by controlling each inverter circuit to sequentially output different phase voltages, a high frequency drive inverter device can be realized. At that time, even if the dead time of the inverter device falls short, the dead time can be shortened while preventing a short circuit between the inverter circuits by the reactor connected to the output side of the single-phase inverter circuit. Therefore, the non-conduction period of the switching element is reduced, and the maximum output voltage can be generated with respect to the DC voltage. In addition, the output current is not affected under normal conditions, and only the short-circuit current when the upper and lower arms are short-circuited can be suppressed, and the dead time is minimized while suppressing excessive current and voltage responsibilities of switching elements and increased loss. Is possible.

The block diagram which shows embodiment of this invention. Voltage wave diagram for explanation. FIG. 4 is a relational diagram of gate voltage and collector-emitter voltage. Explanatory output voltage waveform diagram. The block diagram which shows embodiment of this invention. Voltage wave diagram for explanation. The characteristic view of an IGBT element. The block diagram of a single-phase inverter circuit.

The present invention has a single-phase full-bridge inverter device configuration in which three inverter circuits that output U-phase and V-phase voltages are connected in parallel to the forward conversion circuit. Of the three inverter circuits connected in parallel, the first inverter circuit is controlled to output the U-phase voltage, and the second inverter circuit is controlled to output the V-phase voltage. The inverter circuit is controlled to output the U-phase voltage so that each inverter circuit sequentially outputs the voltages of different phases, which will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an inverter device applied to the present invention. Three single-phase full-bridge inverter circuits IV-1 to IV-3 configured in the same manner as in FIG. 6 are connected in parallel to a forward conversion circuit Cov, which is a common DC power source, and a DC voltage Edc is applied to each of them. Is applied. L is a reactor connected to each output terminal of each inverter circuit IV-1 to IV-3, and U and V are U-phase and V-phase output terminals. Reference numerals 1 to 6 show the order of applying gate signals to the respective IGBT elements forming the respective inverter circuits IV-1 to IV-3, and the IGBT elements of the respective inverter circuits IV-1 to IV-3 are 1 to The ON control is performed in the order of 6, and the voltages corresponding to the control order are output as shown in FIG.

That is, in the ON control sequence 1, the first IGBT element Tu1-1 in the U-phase arm and the second IGBT element Tv1-2 in the V-phase arm of the inverter circuit IV-1 are simultaneously turned on. The current flows through the route of P→Tu1-1→U→V→Tv1-2→N.
In the order 2, the first IGBT element Tv2-1 in the V-phase arm of the inverter circuit IV-2 and the second IGBT element Tu2-2 in the U-phase arm are simultaneously turned on. The current flows through the route of P→Tv2-1→V→U→Tu2-2→N.
In the order 3, the first IGBT element Tu3-1 in the U-phase arm of the inverter circuit IV-3 and the second IGBT element Tv3-2 in the V-phase arm are simultaneously turned on. The current flows through the route of P→Tu3-1→U→V→Tv3-2→N.

Next, in order 4, the first IGBT element Tv1-1 in the V-phase arm of the inverter circuit IV-1 and the second IGBT element Tu1-2 in the U-phase arm are simultaneously turned on. The current flows through the route of P→Tv1-1→V→U→Tu1-2→N.
In the same manner, the IGBT elements corresponding to the order 5 and 6 are driven, respectively, and the control is repeated from the order 1 to the order 6 → the order 1 →.

FIG. 3 shows the relationship between the gate voltage of the IGBT element and the collector-emitter voltage. (a) is the gate voltage of the IGBT element Tu1-1 in the inverter circuit IV-1, and (b) is the IGBT element Tu1-1. Is the gate voltage of the IGBT element Tu2-2 in the inverter circuit IV-2, and (c) is the collector-emitter voltage of the IGBT element Tu2-2.

The waveform at the time of turn-on and turn-off of the IGBT element does not operate linearly as shown in FIG. 5, but is shown as linear operation in FIG. In FIG. 3A, the gate voltage for Tu1-1 rises, and after the turn-on (ton) of Tu1-1, the collector-emitter voltage of Tu1-1 drops to a substantially steady forward voltage. At time t3 when the gate voltage for Tu1-1 disappears from time t1 at which the gate voltage is turned off (toff), the collector-emitter voltage recovers to a substantially steady off voltage.

When the inverter device shown in FIG. 1 is driven, Tu1-1 and Tu2-2 are connected in series from the time when the IGBT element in the order 1 is driven to the time when commutation to the IGBT element is performed in the order 2. At the time of this commutation, as shown in FIG. 3, it conducts from time t1 when the gate voltage of Tu1-1 disappears to time t3 when it turns off, and then turns off immediately thereafter. In the present invention, during commutation from Tu1-1 to Tu2-2, a dead time period is shortened by applying a gate signal to Tu2-2 at time t2 before time t3. That is, the dead time is toff-ton.
The same applies to the relationship between Tv2-1 and Tv3-2, Tu3-1 and Tu1-2.

In the example of FIG. 3, the time t1 of commutation from the positive electrode side IGBT element Tu1-1, which is first in the control order, to the next controlled negative electrode side IGBT element Tu2-2, which is in the same phase as Tu1-1. During t3, if "the collector-emitter voltage CE of Tu1-1+the collector-emitter voltage CE of Tu2-2=DC voltage Edc" is satisfied, the short-circuit current from Tu1-1 to Tu2-2 does not flow. However, depending on the actual waveform, there is a possibility that “the collector-emitter voltage CE of Tu1-1+the collector-emitter voltage CE of Tu2-2<DC voltage Edc” as shown in FIG.

When there is a period in which the expression "Collector-emitter voltage CE of Tu1-1+CE-DC voltage Edc of Tu2-2<DC voltage Edc" is satisfied, the DC voltage Edc-(Tu1-1 collector-emitter voltage CE+Tu2 The voltage of -2 collector-emitter voltage CE) (=v) acts as a power source, and a short-circuit current flows from the P side through the reactor L to the N side. A reactor L is inserted to suppress this current to a predetermined value ΔI. The predetermined value ΔI is approximately calculated by the equation (1).

According to the first embodiment described above, the dead time can be shortened. Also, even if the dead time of the inverter device falls short due to the on/off switching speed of the IGBT element, the reactor connected to the output side of the single-phase inverter circuit prevents the short circuit between the inverter circuits and shortens the dead time. Is possible. Therefore, the non-conduction period of the IGBT element is reduced, and the maximum output voltage can be generated with respect to the DC voltage.

FIG. 5 shows a configuration diagram of an inverter device according to the second embodiment. The same parts as those of the first embodiment shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. That is, in this embodiment, the reactors L1 to L6 are connected between the smoothing capacitors C1 to C3 provided in the inverter circuits IV-1 to IV-3 and the forward conversion circuit Cov, respectively. The reactors L1' to L6' are wiring inductances.

The IGBT elements of the inverter circuits IV-1 to IV-3 are ON-controlled in the order of 1 to 6 and the voltages corresponding to the control order are output as shown in FIG. Similar to FIG. 1, in the turn-on control sequence 1, the first IGBT element Tu1-1 in the U-phase arm and the second IGBT element Tv1-2 in the V-phase arm of the inverter circuit IV-1 are simultaneously turned on. Further, in the order 2, the first IGBT element Tv2-1 in the V-phase arm of the inverter circuit IV-2 and the second IGBT element Tu2-2 in the U-phase arm are simultaneously turned on.

The load current flowing from the U phase to the V phase during the operation from the order 1 to 2 is mainly supplied from the smoothing capacitor C1, and the load current flowing from the V phase to the U phase during the operation from the order 2 to 3 is mainly Is supplied from the smoothing capacitor C2. The current path from the U phase to the V phase in the normal operation flows through a route of C1(P)→Tu1-1→U→load→V→Tv1-2→C1(N). The current path from the V phase to the U phase flows through the route of C2(P)→Tv2-1→V→load→U→Tu2-2→C2(N).

Next, when a short circuit occurs during the commutation operation from the order 1 to 2, the short-circuit current path and the current supplied to Tu1-1 and Tu2-2 are as follows.
(C1(P)→Tu1-1→Tu2-2→L4′→L4→L2→L2′→C1(N))+
(C2(P)→L3′→L3→L1→L1′→Tu1-1→Tu2-2→C2(N))
It flows on the route.

Similarly, the short-circuit current path and the current that are applied to Tv2-1 and Tv1-2 are
(C2(P)→Tv2-1→Tv1-2→L2′→L2→L4→L4′→C2(N))+
(C1(P)→L1′→L1→L3→L3′→Tv2-1→Tv1-2→C1(N))
It flows on the route.

As described above, in the case where the inverter is operated in a time-division manner, the reactors L1 to L6 are connected between the smoothing capacitors C1 to C3 and the forward conversion circuit Cov, respectively, so that the smoothing capacitors C1 to C3 are connected normally. When the load current at the time of short-circuiting and the short-circuit current at the time of short-circuiting the upper and lower arms have different conduction paths, the output current is not affected under normal conditions, and the reactors L1 to L6 can suppress only the short-circuit current at the time of short-circuiting the upper and lower arms. it can.

Therefore, according to this embodiment, it is possible to minimize the dead time provided to prevent the current and voltage duty of the IGBT element from becoming excessive and increasing the loss.

IV (IV-1 to IV-3)... Inverter circuit Cov... Forward conversion circuit Cov
Tu, Tv... IGBT element L1-L6... Reactor C1-C3... Smoothing capacitor

Claims (2)

In a method of controlling an inverter device having a single-phase full bridge configuration, in which three inverter circuits that output U-phase and V-phase voltages are connected in parallel to a forward conversion circuit,
Among the three inverter circuits connected in parallel, the first inverter circuit is controlled to output a voltage from the U phase to the V phase, and the second inverter circuit is controlled to output the voltage from the V phase to the U phase. To output a voltage from the U-phase to the V-phase for the third inverter circuit, so that each inverter circuit sequentially outputs a voltage of a different phase,
At the time of commutation from the inverter circuit that outputs the voltage to the inverter circuit that outputs the next phase voltage, the commutation occurs with the dead time of [turn-off time toff-turn-on time ton] of the switching element characteristics of each inverter circuit. A method for controlling an inverter device, characterized in that a gate signal is applied to a switching element on the side. In each of the three inverter circuits, a smoothing capacitor is connected to the DC side, and a reactor is separately connected between each smoothing capacitor and the forward conversion circuit to suppress a short circuit current. Item 2. A control method for an inverter device according to Item 1.

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