JP2017070179A - Control method for inverter device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the following problem: A single-phase inverter requires prevention of an element short circuit between the top and bottom by setting a dead time much enough to generate no arm short circuit for element driving.SOLUTION: An inverter device of single-phase full bridge is constructed by connecting three inverter circuits outputting U-phase and V-phase voltages in parallel to a forward conversion circuit, and controls to output a U-phase voltage to the first inverter circuit, of the three inverter circuits connected in parallel, to output a V-phase voltage to the second inverter circuit and to output a U-phase voltage to the third inverter circuit, thereby making each inverter circuit control to sequentially output voltages of different phases.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a control method for an inverter device, and more particularly to a control method for reducing dead time in an inverter device configured with a plurality of single-phase full bridge circuits using switching elements.

  FIG. 7 shows a waveform diagram at turn-on and turn-off when an IGBT element is used as the switching element. VGE is a gate-emitter voltage, VCE is a collector-emitter voltage, and IC is a collector current. As a characteristic of most IGBT elements, the time relationship between the turn-on time ton and the turn-off time toff is the relationship of turn-on time ton <turn-off time toff. For example, in the case of an IGBT element having a rated voltage of 1200 V and a rated current of 300 A, when an IGBT element having a time difference of about toff−ton = 200 ns is used in the inverter device, the upper and lower sides of the inverter are changed based on the time difference. Considering the turn-on time, turn-off time, temperature dependency, etc. to prevent a short circuit, the dead time is set by appropriately determining the safety factor.

  Inverter devices used for induction heating devices, etc., connect a plurality of single-phase inverters (section units A to D) to a DC power source, and drive them to section units A to D for each inverter. It is known from Patent Document 1 that high frequency is supported by sequentially driving.

Patent No. 4761696

  FIG. 8 shows an inverter circuit having a single-phase full-bridge configuration. A single-phase full-bridge using a U-phase arm in which IGBT elements Tu1 and Tu2 are connected in series and a V-phase arm in which IGBT elements Tv1 and Tv2 are connected in series. It has a configuration. In addition, as a switching element used for an inverter circuit, power semiconductors such as FET and SiC are used in addition to the IGBT. In the following, an IGBT element is taken as an example.

  In the circuit configuration shown in FIG. 8, in order to prevent the IGBT element short circuit between the upper and lower sides in each phase arm, it is necessary to provide a sufficient dead time to prevent the arm short circuit in driving the IGBT element. For this reason, there is a period in which both the upper and lower IGBT elements are off, and there is a problem that a period in which power is not supplied to the load side occurs and the output voltage decreases. In particular, this influence becomes large in an inverter device driven at a high frequency. Note that Patent Document 1 does not mention reducing dead time.

  An object of the present invention is to provide a method for controlling an inverter device that reduces dead time and shortens the non-conducting period of a switching I element.

The present invention relates to an inverter device having a single-phase full-bridge configuration in which three inverter circuits that output U-phase and V-phase voltages are connected in parallel to a forward conversion circuit.
Of the three inverter circuits connected in parallel, the first inverter circuit is controlled to output a voltage from the U phase to the V phase, and the second inverter circuit is controlled from the V phase to the U phase. And the third inverter circuit is controlled to output a voltage from the U phase to the V phase, so that each inverter circuit is controlled to sequentially output a voltage of a different phase. Method for controlling the inverter device.

  The present invention is characterized in that each phase of the AC output of each inverter circuit has an inductance.

  Further, according to the present invention, at the time of commutation from an inverter circuit that outputs a voltage to an inverter circuit that outputs a next phase voltage, [turn-off time toff-turn-on time ton] of the switching element characteristics of each inverter circuit A gate signal is applied to the switching element on the side commutated with the dead time.

  Further, according to the present invention, each of the three inverter circuits has a smoothing capacitor connected to the DC side, and a separate reactor is connected between each smoothing capacitor and the forward conversion circuit to suppress a short circuit current. It is characterized by.

  As described above, according to the present invention, each inverter circuit is controlled so as to sequentially output voltages of different phases, thereby enabling a high-frequency drive inverter device. At that time, even when the dead time of the inverter device falls short, the reactor connected to the output side of the single-phase inverter circuit can reduce the dead time while preventing a short circuit between the inverter circuits. Therefore, the non-conduction period of the switching element is reduced, and the maximum output voltage can be generated with respect to the DC voltage. In addition, the output current is not affected under normal conditions, and only the short-circuit current when the upper and lower arms are short-circuited can be suppressed, and the switching element current, voltage duty excess, and loss increase are suppressed while minimizing the dead time. Is possible.

The block diagram which shows embodiment of this invention. Voltage wave diagram for explanation. The relationship diagram of gate voltage and collector-emitter voltage. Output voltage waveform diagram for explanation. The block diagram which shows embodiment of this invention. Voltage wave diagram for explanation. The characteristic view of an IGBT element. The block diagram of a single phase inverter circuit.

  According to the present invention, three inverter circuits that output U-phase and V-phase voltages are connected in parallel to a forward conversion circuit to form a single-phase full-bridge inverter device configuration. Of the three inverter circuits connected in parallel, the first inverter circuit is controlled to output a U-phase voltage, and the second inverter circuit is controlled to output a V-phase voltage. By controlling the inverter circuit to output a U-phase voltage, each inverter circuit is controlled so as to sequentially output a voltage of a different phase, which will be described in detail below with reference to the drawings.

  FIG. 1 shows a configuration diagram of an inverter device applied to the present invention. Three inverter circuits IV-1 to IV-3 having a single-phase full-bridge configuration configured in the same way as in FIG. Is applied. L is a reactor connected to each output terminal of each inverter circuit IV-1 to IV-3, U and V are U-phase and V-phase output terminals. Reference numerals 1 to 6 denote gate signal application orders to the IGBT elements constituting the inverter circuits IV-1 to IV-3. The IGBT elements of the inverter circuits IV-1 to IV-3 are 1 to 6, respectively. 6 is turned on in the order of 6, and a voltage corresponding to the control order is output as shown in FIG.

That is, in the turn-on control sequence 1, the first IGBT element Tu1-1 in the U-phase arm of the inverter circuit IV-1 and the second IGBT element Tv1-2 in the V-phase arm are simultaneously turned on. The current flows through the route of P → Tu1-1 → U → V → Tv1-2 → N.
In order 2, the first IGBT element Tv2-1 in the V-phase arm of the inverter circuit IV-2 and the second IGBT element Tu2-2 in the U-phase arm are simultaneously turned on. The current flows through a route of P → Tv2-1 → V → U → Tu2-2 → N.
In order 3, the first IGBT element Tu3-1 in the U-phase arm of the inverter circuit IV-3 and the second IGBT element Tv3-2 in the V-phase arm are simultaneously turned on. The current flows through a route of P → Tu3-1 → U → V → Tv3-2 → N.

Next, in order 4, the first IGBT element Tv1-1 in the V-phase arm of the inverter circuit IV-1 and the second IGBT element Tu1-2 in the U-phase arm are simultaneously turned on. The current flows through a route of P → Tv1-1 → V → U → Tu1-2 → N.
In the same manner, the IGBT elements corresponding to the orders 5 and 6 are respectively driven, and the repetition control is performed in the order of the order 1 to the order 6 → the order 1 →.

  FIG. 3 shows the relationship between the gate voltage of the IGBT element and the collector-emitter voltage. (A) is the gate voltage of the IGBT element Tu1-1 in the inverter circuit IV-1, and (b) is the IGBT element Tu1-1. (C) is the gate voltage of the IGBT element Tu2-2 in the inverter circuit IV-2, and (c) is the collector-emitter voltage of the IGBT element Tu2-2.

  The waveform at the turn-on / turn-off of the IGBT element does not operate linearly as shown in FIG. 5, but is shown as a linear operation in FIG. In FIG. 3A, the gate voltage with respect to Tu1-1 rises, and after Tu1-1 is turned on, the voltage between the collector and emitter of Tu1-1 decreases to a substantially steady forward voltage. At time t3 when the gate voltage with respect to Tu1-1 disappears from time t1 to turn off (toff), the collector-emitter voltage recovers to a substantially steady off voltage.

When the inverter device shown in FIG. 1 is driven, Tu1-1 and Tu2-2 are connected in series at the time of commutation from the driving of the IGBT element of order 1 to the IGBT element of order 2. At the time of this commutation, as shown in FIG. 3, it conducts from time t1 when the gate voltage of Tu1-1 ceases to time t3 when it turns off, and turns off immediately thereafter. In the present invention, at the time of commutation from Tu1-1 to Tu2-2, a dead time period is shortened by applying a gate signal to Tu2-2 at time t2 before time t3. That is, the dead time is toff−ton.
The same applies to the relationship between Tv2-1 and Tv3-2, Tu3-1 and Tu1-2.

  In the example of FIG. 3, from the positive-side IGBT element Tu1-1 whose control order comes first to the negative-phase IGBT element Tu2-2 controlled in the next phase in phase with this Tu1-1, t1 If “Tu1-1 collector-emitter voltage CE + Tu2-2 collector-emitter voltage CE = DC voltage Edc” is established during t3, a short-circuit current from Tu1-1 to Tu2-2 does not flow. However, depending on the actual waveform, as shown in FIG. 4, there is a possibility that “the collector-emitter voltage CE of Tu1-1 + the collector-emitter voltage CE of Tu2-2 <the DC voltage Edc”.

  When a period in which the expression “Tu1-1 collector-emitter voltage CE + Tu2-2 collector-emitter voltage CE <DC voltage Edc” is established, DC voltage Edc− (Tu1-1 collector-emitter voltage CE + Tu2 The voltage of −2 collector-emitter voltage CE) (= v) becomes the power source, and a short-circuit current flows from the P side to the N side through the reactor L. In order to suppress this current to a predetermined value ΔI, a reactor L is inserted. The predetermined value ΔI is approximately calculated by equation (1).

  As described above, according to the first embodiment, the dead time can be shortened. In addition, even if the dead time of the inverter device falls short due to the on / off switch speed of the IGBT element, the reactor connected to the output side of the single-phase inverter circuit reduces the dead time while preventing a short circuit between the inverter circuits. Is possible. Therefore, the non-conduction period of the IGBT element is reduced, and the maximum output voltage can be generated with respect to the DC voltage.

  FIG. 5 shows a configuration diagram of the inverter device according to the second embodiment. The same reference numerals are given to the same portions as those of the first embodiment shown in FIG. That is, in this embodiment, reactors L1 to L6 are connected between the smoothing capacitors C1 to C3 provided in the inverter circuits IV-1 to IV-3 and the forward conversion circuit Cov, respectively. Reactors L1 ′ to L6 ′ are wiring inductances.

  The IGBT elements of the respective inverter circuits IV-1 to IV-3 are turned on in the order of 1 to 6, and a voltage corresponding to the control order is output as shown in FIG. As in FIG. 1, in the ON control order 1, the first IGBT element Tu1-1 in the U-phase arm of the inverter circuit IV-1 and the second IGBT element Tv1-2 in the V-phase arm are simultaneously turned on. In order 2, the first IGBT element Tv2-1 in the V-phase arm of the inverter circuit IV-2 and the second IGBT element Tu2-2 in the U-phase arm are simultaneously turned on.

  The load current that flows from the U phase to the V phase during the operation from the order 1 to 2 is mainly supplied from the smoothing capacitor C1, and the load current that flows from the V phase to the U phase during the operation from the order 2 to 3 is the main current. Is supplied from the smoothing capacitor C2. The current path from the U phase to the V phase in normal operation flows in the route of C1 (P) → Tu1-1 → U → load → V → Tv1-2 → C1 (N). Further, the current path from the V phase to the U phase flows through a route of C2 (P) → Tv2-1 → V → load → U → Tu2-2 → C2 (N).

Next, when a short circuit occurs during the commutation operation from order 1 to 2, the short-circuit current path and current that are passed through Tu1-1 and Tu2-2 are:
(C1 (P) → Tu1-1 → Tu2-2 → L4 ′ → L4 → L2 → L2 ′ → C1 (N)) +
(C2 (P) → L3 ′ → L3 → L1 → L1 ′ → Tu1-1 → Tu2-2 → C2 (N))
Flowing in the route.

Similarly, the short-circuit current path and current passed through Tv2-1 and Tv1-2 are:
(C2 (P) → Tv2-1 → Tv1-2 → L2 ′ → L2 → L4 → L4 ′ → C2 (N)) +
(C1 (P) → L1 ′ → L1 → L3 → L3 ′ → Tv2-1 → Tv1-2 → C1 (N))
Flowing in the route.

  As described above, when the inverter is operated in a time-sharing manner, the reactors L1 to L6 are connected between the smoothing capacitors C1 to C3 and the forward conversion circuit Cov, respectively. The difference between the load current at the time and the short-circuit current at the time when the upper and lower arms are short-circuited is established, and the output current is not affected when normal, and each reactor L1 to L6 can suppress only the short-circuit current when the upper and lower arms are short-circuited it can.

  Therefore, according to this embodiment, it is possible to minimize the dead time provided to prevent the IGBT element current and voltage duty from being excessively increased and loss.

IV (IV-1 to IV-3) ... Inverter circuit Cov ... Forward conversion circuit Cov
Tu, Tv ... IGBT elements L1-L6 ... Reactors C1-C3 ... Smoothing capacitors

Claims (4)

In a control method of an inverter device having a single-phase full-bridge configuration in which three inverter circuits that output U-phase and V-phase voltages are connected in parallel to a forward conversion circuit,
Of the three inverter circuits connected in parallel, the first inverter circuit is controlled to output a voltage from the U phase to the V phase, and the second inverter circuit is controlled from the V phase to the U phase. And controlling the third inverter circuit to output a voltage from the U-phase to the V-phase so that each inverter circuit sequentially outputs a voltage of a different phase. Method for controlling the inverter device. 2. The method for controlling an inverter device according to claim 1, wherein each phase of the AC output of each inverter circuit has an inductance. At the time of commutation from the inverter circuit outputting the voltage to the inverter circuit outputting the next phase voltage, the commutation is performed with a dead time of [turn-off time toff-turn-on time ton] of the switching element characteristic of each inverter circuit. 3. The method of controlling an inverter device according to claim 1, wherein a gate signal is applied to the switching element on the side. Each of the three inverter circuits has a smoothing capacitor connected to the DC side, and a separate reactor is connected between each smoothing capacitor and the forward conversion circuit to suppress a short circuit current. Item 4. A method for controlling an inverter device according to Item 1 or 3.

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