JP5260957B2 - Power converter - Google Patents

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JP5260957B2
JP5260957B2 JP2007340126A JP2007340126A JP5260957B2 JP 5260957 B2 JP5260957 B2 JP 5260957B2 JP 2007340126 A JP2007340126 A JP 2007340126A JP 2007340126 A JP2007340126 A JP 2007340126A JP 5260957 B2 JP5260957 B2 JP 5260957B2
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single
pwm
phase inverter
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JP2009165222A (en
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賢司 藤原
明彦 岩田
知之 川上
寛 伊藤
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三菱電機株式会社
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Abstract

<P>PROBLEM TO BE SOLVED: To obtain a power conversion device which can suppress voltage variations of DC bus bars of single-phase inverters, can suppress a surge voltage by decelerating switching speed, and can reduce loss and cost. <P>SOLUTION: In the power conversion device which is connected with the two or more single-phase inverters in series, and feeds AC outputs which are composed from the two or more single-phase inverters to a load, at least one single-phase inverter out of the single-phase inverters having arms connected to the load out of the two or more single-phase inverters is constituted of a one-pulse arm which performs switching when output polarities are switched, and a PWM arm which performs constant PWM switching, and is a PWM inverter which is applied with PWM control. The PWM arms are connected to the load, and the one-pulse arm is connected to the single-phase inverter other than the PWM inverter. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a power conversion device that converts DC power to AC power using a plurality of semiconductor switching elements such as MOSFETs and IGBTs.

  This type of conventional power conversion device uses a DC voltage obtained by boosting an input DC power supply voltage by a chopper circuit as a DC power supply, a first single-phase inverter that outputs a pulse waveform only for a predetermined period, and a pulse width modulation method (hereinafter referred to as a pulse width modulation method) The AC side of the second and third single-phase inverters that are output in PWM is connected in series, and the output voltage is determined by the sum of the generated voltages by a predetermined combination selected from the plurality of single-phase inverters. In some cases, the power conversion device is configured so that the bus voltage of the inverter that outputs PWM is lowered, thereby reducing the switching loss and improving the conversion efficiency (see, for example, Patent Document 1).

International Publication WO2006 / 090674

  However, the plurality of single-phase inverters used in the conventional power conversion apparatus as shown in Patent Document 1 are full-bridge inverters, and among the single-phase inverters, 2 constitutes a single-phase inverter that outputs in PWM. Each of the arms was switched at a high switching frequency. In a power conversion device configured using a semiconductor switching element, a surge voltage is generated when the semiconductor switching element is switched. When the current changes at a change rate di / dt during switching, an induced voltage (L · di / dt) is generated in a spike shape with respect to the floating inductance L of the wiring itself.

  With recent technological advances, the switching speed of the semiconductor switching element has been increased. However, since the current change rate is increased, the surge voltage generated may be increased, leading to destruction. In order to increase the power conversion efficiency of the power conversion device, it is necessary to speed up the above switching and reduce the switching loss. However, since the switching is fast, the surge voltage increases, and for all the semiconductor switching elements constituting the inverter. There is a problem that it is necessary to add a snubber circuit or a high voltage product is required. However, if this is done, the snubber loss will increase, and the conduction loss due to the on-resistance will increase, leading to a decrease in power conversion efficiency and increasing the cost.

  In addition, since the single-phase inverter that outputs the pulse waveform and the single-phase inverter that outputs PWM are connected in series at the AC output terminal of the inverter, the potential of that terminal is the same, so switching of the single-phase inverter that outputs PWM The potential fluctuation accompanying the fluctuation also changes the potential of the single-phase inverter that outputs the pulse waveform. The fluctuation in the voltage of the DC bus of the single-phase inverter increases, generating a lot of noise or static including floating. There has been a problem that the charge / discharge loss due to the capacitance component increases.

  The present invention has been made to solve such a problem, and can suppress the voltage fluctuation of the DC bus of the single-phase inverter and can suppress the surge voltage by slowing the switching speed, thereby reducing the loss and cost. An object of the present invention is to realize a power conversion device that can reduce power consumption.

The power conversion device according to the present invention is a power conversion device in which two or more single-phase inverters are connected in series, and the combined AC output from the two or more single-phase inverters is supplied to a load. the single-phase inverter having an arm connected to the load of the above single-phase inverter, performs one pulse arm and constantly PWM switching for switching when the output polarity of the single-phase inverter is switched to said load A PWM inverter configured with a PWM arm and performing PWM control, wherein the PWM arm is connected to the load, and the one-pulse arm is connected to a single-phase inverter other than the PWM inverter It is.

  A single-phase inverter that outputs a pulse waveform by connecting the AC-side output terminal of a 1-pulse arm with an extremely small number of switching in one cycle of the output AC waveform to the AC-side output terminal of the single-phase inverter that outputs the pulse waveform The voltage fluctuation of the DC bus can be suppressed. Further, since the switching loss on the one-pulse switching side with a small number of switchings has little influence on the power conversion efficiency, the surge voltage can be suppressed by slowing the switching speed.

Embodiment 1.
Hereinafter, the power converter by Embodiment 1 of this invention is demonstrated according to a figure. 1 is a circuit diagram showing a configuration of a power conversion device according to Embodiment 1 of the present invention. In FIG. 1, 1 is a DC power source, 2 is a buck-boost converter, 3 is an input capacitor of a first single-phase inverter described later, 4 is an input capacitor of a second single-phase inverter described later, DC power supply for the second single-phase inverter, 6 is a first single-phase inverter, 7 is a second single-phase inverter, 8 is a filter reactor, 9 is a filter capacitor, 10 is a load, 11 is a control device, The control signal 12 for the single-phase inverter, the control signal 13 for the second single-phase inverter, and the control signal 14 for the buck-boost converter are output. The second single-phase inverter 7 has an arm connected to the load 10 and is composed of a one-pulse arm 15 that switches only when the output polarity is switched and a PWM arm 16 that always switches at PWM. PWM inverter. The PWM arm 16 is connected to the load 10, and the 1-pulse arm 15 is connected to the first single-phase inverter 6 that is a single-phase inverter other than the PWM inverter. The second single-phase inverter 7 is a single-phase inverter other than the single-phase inverter connected to the buck-boost converter 2.

  As shown in FIG. 1, the DC voltage obtained by the DC power source 1 is boosted or stepped down to a predetermined voltage by the buck-boost converter 2, and the input capacitor 3 of the first single-phase inverter serving as the first DC power source is charged. Thus, the DC bus voltage of the first single-phase inverter 6 is obtained. One of the AC side output terminals of the first single-phase inverter 6 that receives the DC power of the input capacitor 3 of the first single-phase inverter is the AC side of the 1-pulse arm 15 of the second single-phase inverter 7. The other AC side output terminal is connected to the output reactor, and the other AC side output terminal is connected to the filter reactor 8, and an inverter unit is configured by series multiplexing of the two single-phase inverters 6 and 7.

  Each of the single-phase inverters 6 and 7 has a plurality of self-extinguishing semiconductor switching elements Q1 such as a plurality of MOS-FETs and IGBTs, each having a diode connected in antiparallel (or may be a parasitic diode of a self-extinguishing semiconductor switching element). ~ Q4, Q5 ~ Q8, and the sum of these generated voltages is output as an inverter unit. FIG. 8 shows a simplified enlarged view of a MOS-FET, which is a well-known configuration having a drain D, a source S, and a gate G electrode, and a diode 20 connected in reverse parallel between D-S.

  The second single-phase inverter 7 secures a DC bus voltage by the second single-phase inverter DC power supply 5 and the input capacitor 4 of the second single-phase inverter, and the bus voltage is the same as that of the first single-phase inverter 6. Below the DC bus voltage. Instead of the DC power supply 5 for the second single-phase inverter, a DC / DC converter having the input capacitor 3 of the first single-phase inverter as an input is used as the input capacitor 4 of the second single-phase inverter. It is also possible to charge the voltage. The output AC voltage and current from each single-phase inverter unit 6, 7 are smoothed by the filter reactor 8 and the filter capacitor 9 and supplied to the load 10.

  The single-phase inverters 6 and 7 and the step-up / step-down converter 2 described above are controlled by control signals 12 to 14 (details will be described later) output from the control device 11. The control device 11 includes, for example, a known circuit such as a CPU (Central Processing Unit), a DSP (Digital Signal Processor), a PLD (Programmable Logic Device), or an FPGA (Field Programmable Gate Array).

Next, the operation will be described with reference to the operation waveform of each part in FIG.
As is apparent from the figure, the output of the first single-phase inverter 6 pulses the voltage only during a period when the absolute value of the output AC voltage is higher than a predetermined voltage, and the output of the second single-phase inverter 7 Is output by PWM control so as to compensate for the difference between the target output voltage and the output voltage of the first single-phase inverter 6. These combined waveforms are output to the load 10 as the inverter output. During the period when the output voltage of the first single-phase inverter 6 is 0, two semiconductors Q2 and Q4 on the low-voltage bridge side (N side) of each arm among the semiconductor switching elements of the first single-phase inverter 6 The switching element is turned on, and the first single-phase inverter 6 is output through.

  Since the second single-phase inverter 7 needs to output a difference between the target output voltage and the output voltage of the first single-phase inverter 6, a positive and negative voltage is appropriately output to the AC output. In the first embodiment, the second single-phase inverter 7 is completely divided into a 1-pulse arm 15 that switches only when the positive and negative output polarities are switched and a PWM arm 16 that constantly performs PWM switching and adjusts the output. .

  For example, when the second single-phase inverter 7 outputs a positive voltage, Q6 is turned on, Q7 and Q8 are switched by PWM, and a predetermined voltage is output. Similarly, when outputting a negative voltage, Q5 is turned on, Q7 and Q8 are switched by PWM, and a predetermined voltage is output. As a result, the second single-phase inverter 7 outputs positive, zero, and negative voltages.

  FIG. 3 shows the control signals 12, 13 of the single-phase inverters for controlling the semiconductor switching elements constituting the single-phase inverters 6, 7 shown in FIG. It is the example of a waveform which showed simply. In the figure, the contents of the control signal 12 of the first single-phase inverter and the control signal 13 of the second single-phase inverter corresponding to the semiconductor switching elements Q1 to Q4 and Q5 to Q8 are shown.

  In the present embodiment, the second single-phase inverter 7 outputs PWM by using a control that performs switching only when the one-pulse arm 15 switches between positive and negative output polarities. Since the fluctuation of the potential of the output terminal is small, the potential on the P side or N side of the input capacitor 3 of the first single-phase inverter can be set by connecting the terminal to the AC-side output terminal of the first single-phase inverter 6. Since stabilization is possible, there is an effect of reducing voltage ripple.

In addition, the number of times of switching of the one-pulse arm 15 of the second single-phase inverter 7 is 5 on / off times in one cycle of the AC output sine wave. Assuming that the PWM switching frequency of the PWM arm 16 is 20 kHz and the output AC frequency is 50 Hz, the ratio of the number of times of switching is as follows:
[Formula 1] 1-pulse arm switching frequency: PWM arm switching frequency = 1:80
The ratio of the switching loss caused by the two semiconductor switching elements Q5 and Q6 constituting the one-pulse arm 15 to the total switching loss caused by the second single-phase inverter 7 is very small at 1.25%. Even if the switching speed is lowered, the influence on the power conversion efficiency of the power converter is very small.

FIG. 4 is a circuit diagram showing the second single-phase inverter and its gate resistance. The switching speed of the semiconductor switching element can be changed by changing the gate resistance and adjusting the gate charging speed. Since the current change rate (di / dt) changes depending on the switching speed, the surge voltage generated in the semiconductor switching element can be reduced if the switching speed is slowed down.
Therefore, if the gate resistance 17 of the gate drive unit of the semiconductor switching element of the one-pulse arm 15 shown in FIG. 4 is made larger than the gate resistance 18 of the PWM arm 16, the power conversion efficiency is not affected. The surge voltage generated in the semiconductor switching elements Q5 and Q6 can be reduced more than the surge voltage generated in the semiconductor switching elements Q7 and Q8 of the PWM arm 16.

  As described above, since the effect of the switching loss of the semiconductor switching element of one pulse arm on the power conversion efficiency is very small, the switching speed of the semiconductor switching element of one pulse arm is made slower than the switching speed of the PWM arm. Suppressing the surge voltage generated when switching a semiconductor switching element of one pulse arm, and thereby eliminating the snubber circuit used for suppressing the surge or reducing the capacity, and having a low breakdown voltage The advantage of being able to use a semiconductor switching element is born, and a reduction in loss and cost can be expected.

  By eliminating the snubber circuit, there is an advantage that the loss caused by the snubber is eliminated and the number of circuit components is reduced, and it is possible to expect higher efficiency of power conversion efficiency, cost reduction, and circuit miniaturization. Also, MOSFETs, which are semiconductor switching elements used in this embodiment, tend to have a lower resistance component when they are turned on as the breakdown voltage is lower, except in special cases. By doing so, the conduction loss is reduced and the power conversion efficiency becomes high.

  FIG. 9 shows a basic drive circuit of the semiconductor switching element Q. In the figure, 21 is a power source for driving a gate, 22 is a photocoupler or transistor, 23 is a gate resistance, 24 is a gate-source capacitance of the MOSFET, and 25 is a gate control unit. If the gate resistance 23 is large, the peak value of the gate charging current is lowered. Therefore, when selecting an element of the gate control unit 25 such as the photocoupler or the transistor 22 that controls the supply of the power supply 21 for gate drive, It is possible to select an element with a low current.

Embodiment 2.
The power conversion device according to the second embodiment is obtained by further improving the gate drive unit of the second single-phase inverter 7 in the power conversion device shown in FIG. 1 of the first embodiment. FIG. 5 shows the second single-phase inverter 7 and the gate drive unit 19 used in the present embodiment. The switching resistance of the semiconductor switching elements Q5 and Q6 of the one-pulse arm 15 is determined by the gate resistor 17 which is the first gate driving circuit, and the semiconductor of the PWM arm 16 is determined by the gate driving unit 19 which is the second gate driving circuit. The switching speed of the switching elements Q7 and Q8 is determined. In the gate drive unit 19, the switching speed of the semiconductor switching element of the PWM arm 16 is individually set for each of turn-on and turn-off of the semiconductor switching element of the PWM arm 16.

  The gate drive unit 19 is a circuit in which a diode D1 is inserted in parallel with the resistor R1 in the direction shown in FIG. 5 and connected in series with the low resistor R2, and when the switching speed of the semiconductor switching elements Q7 and Q8 is turned on. And the speed when turning off can be selected respectively. In this circuit, the gate charging current is determined by the total value of the resistors R1 and R2 when turned on, and the discharging current from the gate is determined by the value of the resistor R2 when turned off. The higher the resistance value, the slower the switching.

  Here, the surge voltage generated in the second single-phase inverter 7 will be described. When the second single-phase inverter 7 outputs a positive voltage, the semiconductor switching element Q6 is turned on, and the semiconductor switching elements Q7 and Q8 are switched by PWM to output a predetermined voltage. Similarly, when outputting a negative voltage, the semiconductor switching element Q5 is turned on, Q7 and Q8 are switched by PWM, and a predetermined voltage is output. With this operation, the inverter converts DC power into AC power. When outputting positive alternating current, the semiconductor switching element Q7 passes through the semiconductor switching element Q8 or the free wheel diode (hereinafter referred to as FWD) connected in antiparallel and the semiconductor switching element Q6 in the on state while the semiconductor switching element Q7 is off. Current flows in reflux mode. A short-circuit prevention period called dead time is provided between the two semiconductor switching elements of the bridged arm so as not to cause a short circuit when switching, and both elements of the arm are turned off. The current always flows through the FWD before the semiconductor switching element Q7 is turned on.

  Therefore, diode recovery occurs in the FWD of the semiconductor switching element Q8, and the recovery current is a short-circuit current that flows along a path in which the DC bus is short-circuited with the semiconductor switching element Q7 and the diode. A surge voltage Vsg1 as shown in FIG. 6 is generated between the drain and source terminals of the semiconductor switching element Q8, and this surge voltage often has a very high voltage change rate (dV / dt) and peak value. In the semiconductor switching element Q7, a turn-off surge Vsg2 generated at its own switching speed as shown in FIG. 7 is generated.

  Similarly, when the inverter outputs negative alternating current, current flows in the reflux mode through the semiconductor switching element Q7 or FWD and the semiconductor switching element Q5 while the semiconductor switching element Q8 is off. Therefore, a surge voltage due to diode recovery as shown in FIG. 6 is generated in the semiconductor switching element Q7, and a turn-off surge generated due to its own switching speed as shown in FIG. 7 is generated in the semiconductor switching element Q8.

The surge voltage Vsg1 generated by the diode recovery shown in FIG. 6 is obtained by the following equation.
[Formula 2] Vsg1 = L · d (irr) / dt
The turn-off surge voltage Vsg2 shown in FIG. 7 is obtained by the following equation.
[Formula 3] Vsg2 = L · −d (ioff) / dt
In the above equation, L is the value of stray inductance of the inverter circuit wiring, irr is the recovery current, and ioff is the turn-off current.

  In the present embodiment, in order to suppress a surge voltage due to diode recovery having a very high voltage change rate (dV / dt) and a peak value, the on-speed of the semiconductor switching element of the PWM arm 16 is reduced. If diode recovery occurs in Q8 when Q7 is turned on, if the switching speed of Q7 is slow, the resistance component in the path that shorts the bus will increase, so the current change rate (d (irr) / dt) of the recovery current is As a result, the surge voltage Vsg1 can be lowered as expressed by the following equation (2). As a result, the turn-on loss of the semiconductor switching element to be switched increases, but the recovery loss due to the diode recovery decreases, so the influence on the power conversion efficiency of the power conversion device is small.

  As described above, in the second embodiment of the present invention, the one-pulse arm side does not increase the number of parts of the gate circuit portion by suppressing the surge generated by slowing both the on and off switching speeds. The PWM arm can reduce the surge voltage due to diode recovery, which becomes an excessive surge voltage, by reducing the on-speed of the semiconductor switching element, eliminating the snubber circuit used for surge suppression or reducing the capacity. In addition, an advantage that an element having a low withstand voltage can be used is born, and cost reduction can be expected. Further, the turn-off speed can be maintained, and with respect to the turn-on, although the turn-on loss increases, the recovery loss decreases, so that an increase in switching loss can be suppressed.

  In all the embodiments, a Si (silicon) MOSFET may be used as the switching element, but a SiC (silicon carbide) MOSFET having a smaller on-resistance than the Si (silicon) MOSFET may be used. By using SiC MOSFETs as switching elements, current loss is also reduced, so it is possible to achieve low loss and circuit miniaturization.

It is a whole circuit block diagram of the power converter device by Embodiment 1 of this invention. It is the inverter sum total of the power converter device by Embodiment 1-2 of this invention, and the output waveform of each single phase inverter. FIG. 3 is a control signal for driving each semiconductor switching element showing the control method before applying the present invention shown in the first embodiment. FIG. FIG. 3 is a circuit diagram showing a second single-phase inverter and its gate resistance shown in the first embodiment. FIG. 5 is a circuit diagram showing a second single-phase inverter and its gate drive unit shown in the second embodiment. FIG. 6 is a waveform diagram showing a relationship between a surge voltage and a recovery current that are generated during recovery of a diode. It is a wave form diagram which shows the relationship between the voltage at the time of turn-off of a semiconductor switching element, and an electric current. FIG. 3 is a terminal explanatory diagram of a semiconductor switching element MOSFET in the first and second embodiments of the present invention. 2 shows a basic driving circuit of a semiconductor switching element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 DC power supply, 2 Buck-boost converter, 3 Input capacitor of 1st single phase inverter, 4 Input capacitor of 2nd single phase inverter, 5 DC power supply for 2nd single phase inverter, 6 1st single phase inverter, 7 second single-phase inverter, 8 filter reactor, 9 filter capacitor, 10 load, 11 control device, 12 first single-phase inverter control signal, 13 second single-phase inverter control signal, 14 step-up / down converter Control signal, 15 1 pulse arm, 16 PWM arm, 17 1 pulse arm gate resistance, 18 PWM arm gate resistance, 19 gate drive, 20 diode, 21 gate drive power supply, 22 transistor, 23 gate resistance, 24 MOSFET Gate-source capacitance of 25 gate control section.

Claims (4)

  1. Two or more single-phase inverters are connected in series, and in the power conversion device that supplies a combined AC output from the two or more single-phase inverters to a load, the power converter of the two or more single-phase inverters single-phase inverter having an arm that is connected to the load is constituted by a PWM arm performing one pulse arm and constantly PWM switching for switching when the output polarity of the single-phase inverter for the load is switched, PWM control Wherein the PWM arm is connected to the load, and the one-pulse arm is connected to a single-phase inverter other than the PWM inverter.
  2.   One single-phase inverter of the two or more single-phase inverters is connected to a buck-boost converter that steps up and down a DC power supply voltage, and a DC bus voltage is secured by the buck-boost converter and a capacitor. The single-phase inverter other than the single-phase inverter connected to the DC power supply and the capacitor secures the DC bus voltage, and the DC bus voltage of the single-phase inverter other than the single-phase inverter connected to the buck-boost converter is The power converter according to claim 1, wherein the power converter is set to be equal to or lower than a DC bus voltage of a single-phase inverter connected to the step-up / step-down converter.
  3.   3. The power conversion according to claim 1, wherein a gate resistance connected to the semiconductor switching element of the one-pulse arm is set to a value larger than a gate resistance connected to the semiconductor switching element of the PWM arm. apparatus.
  4. The PWM inverter includes a first gate driving circuit having a gate resistance that determines a switching speed of the semiconductor switching element of the one-pulse arm, a switching speed of the semiconductor switching element of the PWM arm, and a semiconductor switching element of the PWM arm. The power conversion device according to claim 1, further comprising: a second gate driving circuit that is individually set for each of the turn-on and turn-off.
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