JP2008125178A - Motor controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely avoid an excessive surge current which is possibly generated by simultaneously turning on two-phase IGBTs at a certain timing in a three-phase motor controller. <P>SOLUTION: When a U-phase high-side PWM driving signal SUH has the turn-on timing the same as that of a V-phase high-side PWM driving signal SVH, a timing correcting circuit allows a V-phase high-side PWM driving signal DVH to be a signal to which an on-delay time "Ton" for a delay time of one clock CLK to a U-phase high-side PWM driving signal DUH, so that the U-phase and V-phase high-side IGBTs are controlled so as not to be turned on simultaneously. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a motor control device that reduces a surge current generated in an inverter circuit that drives a motor by switching the conduction of a supplied direct current to a switching element configured in a bridge circuit to convert the direct current to alternating current.

  Conventionally, a motor driven by an inverter circuit has been frequently used. This inverter circuit drives a motor by converting a direct current supplied from a direct current power source such as a battery into an alternating current by switching an energized phase by turning on / off (conducting / cutting off) a switching element constituting a bridge circuit.

  The switching element is turned on and off by a PWM (pulse width modulation) drive signal supplied to the gate terminal in the case of a control terminal of the switching element, for example, an IGBT (insulated gate transistor) or a MOSFET.

  When determining the on / off timing (phase) of the PWM drive signal of each phase, for example, in the case of a three-phase motor, phase currents flowing in the coils of the U, V, and W phases are detected, and vector control (field weakening control) or 120 ° Determined by adopting an energization control method such as energization control.

  In general, in a bridge circuit type inverter circuit, a high-side (upper arm side) switching element and a low-side (lower arm side) switching element on the same phase are not turned on at the same time, in other words, so-called arm short circuit is prevented. In addition, the timing of the PWM drive signal for each phase is controlled.

  For this reason, an on-delay time is added to guarantee that the high-side switching element and the low-side switching element are simultaneously turned off with respect to the PWM driving signal for the high-side switching element or the PWM driving signal for the low-side switching element on the same phase. A motor control device that drives a high-side switching element and a low-side switching element has been proposed (Patent Document 1).

JP-A-9-56176 (paragraphs [0003] and [0025], FIG. 1)

  By the way, the above-described additional control of the on-delay time is for preventing a short circuit between the high-side switching element and the low-side switching element connected in series, that is, preventing the arm short circuit on the same phase. Thus, an excessive short-circuit current is generated, and as a result, the DC power supply and / or the inverter circuit is prevented from failing.

  The inventors of this application may drive an excessive surge current to the DC power supply in addition to the arm short circuit on the same phase described above when driving a multi-phase (including not only three phases but also five phases) motors. I found something.

  Hereinafter, in order to facilitate understanding of the present invention, the above-described conventional technique for adding an on-delay time for avoiding an arm short circuit on the same phase according to the related art will not be mentioned. The present invention can be applied to a motor control device regardless of whether or not this well-known technique (arm short-circuit prevention technique on the same phase) is adopted.

  FIG. 6 shows a motor control device 2 according to the prior art for explaining that an excessive surge current may flow on the DC power supply 4 and its supply line, although the operation is normal but not an arm short circuit. The example of a structure is shown.

  The motor control device 2 basically includes a DC power source 4, an U-phase arm 11, a V-phase arm 12 and a W-phase arm 13, and a motor driven by the inverter circuit 6. 14 and the motor control which detects the electric current which flows into each phase of motor 14 with current sensor 16, and generates PWM drive signal SUH, SUL, SVH, SVL, SWH, SWL of each phase, each high side low side switching element The amplitudes of the ECU (motor control circuit) 18 and the PWM drive signals SUH, SUL, SVH, SVL, SWH, SWL are respectively amplified, and the PWM drive signals UH, UL of each corresponding phase, each high-side / low-side switching element , VH, VL, WH, WL are generated, and the high side and low side scans of the UVW phase arms 11, 12, 13 are respectively generated. A switching element IGBT21uh, composed 21ul, 21vh, 21vl, 21wh, the gate drive circuit 20 which supplies to the gate terminal of 21Wl.

  In this case, the motor control ECU 18 compares the voltages of the triangular wave 22 and the sine wave 24 shown in FIG. 7A by a comparator (not shown), and creates a PWM drive signal shown in FIG. 7B.

  By the way, as shown in FIG. 8A, for example, when a three-phase motor is to be driven, a U-phase sine wave 24u, a V-phase sine wave 24v, and a W-phase sine wave 24w are shown in FIG. A U-phase high-side PWM drive signal SUH, a V-phase high-side PWM drive signal SVH shown in FIG. 8C, and a W-phase high-side PWM drive signal SWH shown in FIG. 8C are created.

  However, when a three-phase waveform is handled, timings (time points) t1, t2, etc. at which the sine wave of two phases and the triangular wave 22 intersect among the U-phase sine wave 24u, the V-phase sine wave 24v, and the W-phase sine wave 24w. appear.

  In this case, at the timing t1, the U-phase high side IGBT 21uh driven by the PWM drive signal SUH and the W-phase high side IGBT 21vh driven by the PWM drive signal SWH are turned on simultaneously. At timing t1, the U-phase high side IGBT 21uh driven by the PWM drive signal SUH and the V-phase high side IGBT vh driven by the PWM drive signal SVH are simultaneously turned off.

  As shown at time points t1 and t2, when two IGBTs on the high side of different phases or the low side of different phases are turned on or off at the same time, the coil that is an inductive load is driven. It was found that a surge current larger than usual flows at this timing. In particular, at the time of turn-on, a large surge current flows, and as the collector current Ic, for example, the value of the collector current Ic at the time of stabilization (at the time of settling) is 250 [A] (this is the same value for each turned-on phase). When the value of the stable power supply current Ia flowing out from the DC power supply 4 side is 500 [A] for two phases), when the two-phase surge currents do not overlap, Although each phase was 50 [A], when two-phase surge currents overlap, as shown in FIG. 9, the value of the surge current Ip in the power source current Ia flowing out from the DC power source 4 side is about 100. It turned out to be about twice as large as [A]. In FIG. 9, the time for which the surge current Ip decays to about 10% is referred to as a delay time (attenuation time) Td. The value of the power supply current Ia at the stable time after the delay time Td has elapsed is 500 [A].

  In this case, the excessive surge current Ip may cause damage to the DC power supply 4 or the smoothing capacitor 5, and the DC power supply 4 or the smoothing capacitor 5 that can withstand such a surge current Ip has a high frequency / broadband. Therefore, it is required to have a low output impedance, and it becomes complicated and expensive. In addition, since the surge current Ip also flows through the power supply line and the ground, it is necessary to improve the noise resistance of the device in which the motor control device 2 is mounted, for example, in a welding machine, a hybrid vehicle, a fuel cell vehicle, particularly the control device. There is.

  That is, the generation of a large surge current makes the design conditions of electrical devices, electrical equipment, and electronic equipment more stringent.

  The present invention has been made in consideration of such a problem, and in a multi-phase motor control device, an excessive amount that may occur when a plurality of phase switching elements are simultaneously turned on or turned off at a certain timing. An object of the present invention is to provide a motor control device capable of reliably avoiding generation of a surge current.

  In the motor control device according to the present invention, each of the high-side switching element and the low-side switching element of an inverter circuit configured by connecting a plurality of series circuits of a high-side switching element and a low-side switching element between DC power supplies to form a bridge circuit. A motor for driving the motor by supplying an alternating current to the coil by connecting a coil of each phase of the motor to a middle point and applying a PWM drive signal to the high-side switching element and the low-side switching element to turn it on or off The control device has the following features (1) to (5).

  (1) The timing of the PWM drive signal is manipulated so that the turn-on timing of one phase and the turn-on timing of another phase are shifted with respect to each of the high-side switching elements or the low-side switching elements. A timing correction circuit is provided.

  According to the invention having this feature (1), simultaneous turn-on between the high-side and low-side phases is reliably avoided, and in a multi-phase (two or more phases, three phases, five phases, etc.) motor control device at a certain timing. It is possible to reliably avoid the occurrence of an excessive surge current that may be generated by simultaneously turning on switching elements of a plurality of phases.

  Needless to say, the present invention is applied to avoiding simultaneous turn-off. In this case, the PWM drive signal is set so that the timing correction circuit shifts the turn-off timing of one phase from the turn-off timing of another phase with respect to each of the high-side switching elements or each of the low-side switching elements. The timing may be changed to be operated.

  (2) The timing of the PWM drive signal is manipulated so that the turn-on timing of one phase and the turn-on timing of another phase are shifted with respect to each of the high-side switching element and the low-side switching element. A timing correction circuit is provided.

  According to the invention having this feature (2), simultaneous turn-on between the high-side and low-side phases is reliably avoided, and in a multi-phase (three-phase, five-phase, etc.) motor control device, It is possible to reliably avoid the occurrence of an excessive surge current that may be generated by simultaneously turning on the switching elements.

  Needless to say, the present invention is applied to avoiding simultaneous turn-off.

  That is, the start point and end point of the PWM signal (switching waveform) of the high-side switching element and the low-side switching element are monitored, and when they overlap with the timings of the other phases, the operation is performed to shift one timing.

  (3) In the invention having the above feature (1) or (2), the timing correction circuit is a signal for simultaneously turning on a PWM drive signal of a certain phase and a PWM drive signal of another phase supplied to the timing correction circuit. If it is detected, the on-delay time is added to the PWM drive signal of one phase to shift the timing.

  According to the invention having the feature (3), the design guideline of the timing correction circuit becomes clearer and the circuit configuration can be simplified.

  (4) In the invention having the above feature (3), the on-delay time is set in accordance with a generation time of a surge current that flows when the high-side switching element or the low-side switching element is turned on.

  Since the surge current has a waveform with overshoot and attenuation ringing, for example, it can be set to a time until the overshoot attenuates to a predetermined percentage. Since the generation time of the surge current differs depending on the individual motor control device, it is set to a time suitable for the time (for example, in the case of FIG. 9, time Td).

  (5) In the invention having the above feature (3) or (4), the on-delay time corresponds to a time delayed by one clock when the timing correction circuit is composed of a logic circuit operating with a reference clock. As described above, the period of the reference clock is determined.

  According to the invention having the feature (5), the design guideline of the timing correction circuit becomes clearer and the circuit configuration can be simplified. It is preferable that one clock is set to a time corresponding to the generation time of the surge current. When the clock cycle does not correspond to the surge current generation time, a delay time corresponding to the clock corresponding to the surge current generation time may be set.

  According to the present invention, the timing of the PWM drive signal is shifted so that the switching elements of the phases do not turn on at the same time. Therefore, in the multi-phase motor control device, the switching elements of a plurality of phases are turned on simultaneously or at a certain timing. It is possible to reliably avoid the occurrence of an excessive surge current that may be generated by turning off.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings to be referred to below, the same or corresponding reference numerals are given to those corresponding to those shown in FIGS. 6 to 9 and detailed description thereof will be omitted. Moreover, in order to avoid complexity, it demonstrates with reference to the said FIGS. 6-9 as needed.

  FIG. 1 is a circuit block diagram showing a configuration of a motor control device 50 according to an embodiment of the present invention. The motor control device 50 includes a high-side timing correction circuit 30H and a low-side timing correction circuit 30L, a motor control ECU (motor control circuit) 18 and a gate drive circuit 20 as compared with the motor control device 2 shown in FIG. The point inserted between is different.

  The high-side timing correction circuit 30H and the low-side timing correction circuit 30L are respectively turn-on timings of the PWM drive signals SUH, SUL, SVH, SVL, SWH, and SWL for each phase and each high-side and low-side supplied from the motor control ECU 18. Has been modified in accordance with a predetermined rule (the rule of shifting so that the turn-on timing of one phase and the turn-on timing of another phase do not overlap in the high-side IGBT 21uh, 21vh, 21wh or the low-side IGBT 21ul, 21vl, 21wl) The PWM drive signals DUH, DUL, DVH, DVL, DWH, DWL for each phase and each of the high side and the low side (the waveform timing is manipulated) are supplied to the gate drive circuit 20.

  The motor control device 50 includes the following components in addition to the high side timing correction circuit 30H and the low side timing correction circuit 30L.

  That is, an inverter circuit 6 including a DC power source 4 having a smoothing capacitor 5 connected in parallel, a U-phase arm 11, a V-phase arm 12, and a W-phase arm 13, and a UVW phase driven by the inverter circuit 6. The motor 14 having each coil 51u, 51v, 51w and each internal resistance connected in series, and the current flowing through each phase of the motor 14 is detected by the current sensor 16, and each phase, each high side / low side Each phase in which the timing of the waveform is manipulated by the motor control ECU 18 that generates the PWM drive signals SUH, SUL, SVH, SVL, SWH, SWL, and the high side timing correction circuit 30H and the low side timing correction circuit 30L, The amplitude of the low-side PWM drive signals DUH, DUL, DVH, DVL, DWH, DWL The PWM drive signals UHd, ULd, VHd, VLd, WHd, WLd for each phase and each high-side / low-side are generated, and the high-side / low-side of the UVW-phase arms 11, 12, 13 are respectively generated. The gate drive circuit 20 supplies the gate terminals of IGBTs 21uh, 21ul, 21vh, 21vl, 21wh, and 21wl, which are switching elements.

  Since the high-side timing correction circuit 30H and the low-side timing correction circuit 30L have the same circuit configuration, the configuration operation will be described below using the high-side timing correction circuit 30H as a representative.

  FIG. 2 shows a detailed configuration of the logic circuit of the high side timing correction circuit 30H.

  FIG. 3 is a timing chart of the high side timing correction circuit 30H.

  In this case, for example, the PWM drive signal SUH having a pulse width from the time point ta to the time point tc supplied from the motor control ECU 18 is converted into a signal UD1out synchronized with the rising edge of the clock CLK at the time point t10 by the delay flip-flop UD1. The UD1out is output as the PWM drive signal DUH delayed through the AND UA3 and the delay flip-flop UD3 until the time t11 supplied to the gate drive circuit 20.

  Further, the PWM drive signal SVH having a pulse width from the time point ta to the time point tc supplied from the motor control ECU 18 at the same time point ta at which the turn-on (rise) timing coincides with the PWM drive signal SUH is shifted in turn-on timing. Is operated as follows. In this case, the PWM drive signal SVH is made into a signal VD1out synchronized with the rising of the clock CLK at time t10 by the delay flip-flop VD1, and the time when the signal VD1out is supplied to the gate drive circuit 20 through the AND VA3 and the delay flip-flop VD3. The PWM drive signal DVH delayed until t12 (given on-delay delay time Ton) is output.

  That is, due to the action of the high side timing correction circuit 30H, the PWM drive signal DUH is delayed by about 1 clock CLK and the PWM drive signal SVH is about 2 clock CLK (one clock is the on delay time Td). Min) The delayed PWM drive signal DVH is operated so that the turn-on timing is shifted.

  FIG. 4 shows a configuration of the high side timing correction circuit 30H that more simply represents the logic circuit of the high side timing correction circuit 30H shown in FIG. In FIG. 4, the clock CLK is not shown.

  FIG. 5 shows a time chart obtained by subdividing the period from the time point ta to the time point t16 in the timing chart of the high side timing correction circuit 30H shown in FIG.

  Hereinafter, the operation of the high-side timing correction circuit 30H (logic circuit) from time ta to time t16 will be mainly described with reference to FIGS.

  In this embodiment, the timing of the UVW phase PWM drive signals SUH, SVH, SWH is compared at the time of turn-on, and the timing is shifted by one clock CLK (one clock cycle). Actually, the turn-on same timing is judged in any two phases of the combination of UV phase, VW phase and WU phase. When the timing is UV phase, priority order U → V, and when VW phase, priority order V → W In the order of WU phases, in order of priority W → U, the phase described on the right side of → is operated to give an on-delay time Td for one clock to the phase described on the left side of →. is doing.

  In practice, the input-side delay flip-flops UD1, VD1, and WD1 and the output-side delay flip-flops UD3, VD3, and WD3 do not have to be provided, but the operation is established, but the prevention of the occurrence of whiskers and the like is ensured. It is provided for stabilizing the operation for providing an on-delay time Td for one clock.

  Therefore, first, as shown in FIG. 5, from the motor control ECU 18, PWM drive signals SUH and SVH having a pulse width from the time point ta to the time point tc, and a PWM drive signal SWH having a pulse width from the time point tb to the time point tc are obtained. It is assumed that the high side timing correction circuit 30H is supplied. In the following description, “time point” is also referred to as “timing”.

  In this case, the PWM drive signals SUH and SVH supplied to the delay flip-flops UD1 and VD1, respectively, are the rising timing t10 of the 0th clock CLK indicated as “0” at the rising edge of the clock CLK in FIG. It is delayed so as to be synchronized with the clock CLK at the timing t15 of the fifth clock CLK, and is shaped into signals UD1out and VD1out having a pulse width from time t10 to time t15.

  The PWM drive signal SWH supplied to the delay flip-flop WD1 is shaped into a signal WD1out that is delayed so as to be synchronized with the clock CLK at the rising timing t12 of the second clock CLK and the timing t15 of the fifth clock CLK. Is done.

  Next, the signal UV1out appearing on the output side of the inverter UV1 becomes an inverted signal of the signal obtained by delaying the signal UD1out by one clock CLK by the delay flip-flop UD2.

  The signal UA1out that appears on the output side of the AND UA1 is a logical product signal of the signal UD1out and the signal UV1out.

  Next, the signal VV1out appearing on the output side of the inverter VV1 becomes an inverted signal of the signal obtained by delaying the signal VD1out by one clock CLK by the delay flip-flop VD2.

  The signal VA1out that appears on the output side of the AND VA1 is a logical product signal of the signal VD1out and the signal VV1out.

  The signal UA2out appearing on the output side of the AND UA2 is a logical product signal of the signal UA1out and the signal VA1out. The signal VV2out that appears on the output side of the inverter VV2 is an inverted signal of the signal UA2out.

  The signal VA3out that appears on the output side of the AND VA3 is a logical product signal of the signal VD1out and the signal VV2out.

  As a result, the PWM drive signal DVH appearing on the output side of the flip-flop VD3 is a signal obtained by delaying the signal VA3out by one clock CLK.

  Next, the signal WV1out appearing on the output side of the inverter WV1 becomes an inverted signal of the signal obtained by delaying the signal WD1out by one clock CLK by the delay flip-flop WD2. The signal WA1out that appears on the output side of the AND WA1 is a logical product signal of the signal WD1out and the signal WV1out.

  The signal WA2out appearing on the output side of the AND WA2 is a logical product signal of the signal WA1out and the signal UA1out. In this case, the signal WA2out is held at the low level L.

  Further, the signal UV2out that appears on the output side of the inverter UV2 is an inverted signal of the signal WA2out, and in this case, a signal that maintains the high level H.

  As a result, the PWM drive signal DUH appearing on the output side of the flip-flop UD3 is a signal obtained by delaying the signal UD1out by one clock CLK.

  Further, the signal VA2out appearing on the output side of the AND VA2 is a logical product signal of the signal VA1out and the signal WA1out. In this case, the signal VA2out is held at the low level L.

  Further, the signal WV2out that appears on the output side of the inverter WV2 is an inverted signal of the signal VA2out, and in this case, the signal that holds the high level H.

  As a result, the PWM drive signal DWH appearing on the output side of the flip-flop WD3 is a signal obtained by delaying the signal WD1out by one clock CLK.

  Here, considering the U-phase high-side PWM drive signal DUH and the V-phase high-side PWM drive signal DVH output from the high-side timing correction circuit 30H, the V-phase high-side PWM drive signal DVH is the U-phase high-side. It can be seen that the on-delay time Ton with respect to the delay time of one clock CLK is given to the PWM drive signal DUH.

  Therefore, it is driven by the U-phase high-side PWM drive signal UHd and the V-phase high-side PWM drive signal VHd, which are amplification signals of the U-phase high-side PWM drive signal DUH and the V-phase high-side PWM drive signal DVH, respectively. The IGBT 21uh and the IGBT 21vh are not driven at the same time (at the same timing), in other words, they are driven with even turn-onming, and the surge current Ip at the time of turn-on shown in FIG. Can do.

  As described above, in the above-described embodiment, a plurality of series circuits of the high-side IGBT 21h (21uh, 21vh, 21wh) and the low-side IGBT 21l (21ul, 21vl, 21wl) are connected between the DC power sources 4 to form a bridge circuit. The coils 51u, 51v, 51w of each UVW phase of the motor 14 are connected to the midpoints of the high-side IGBT 21h and the low-side IGBT 21l of the inverter circuit 6, and the PWM drive signals Hd (UHd, VHd, WHd) are connected to the high-side IGBT 21h and the low-side IGBT 21l. ), Ld (ULd, VLd, WLd) is applied to turn on or off to supply an alternating current to the coils 51u, 51v, 51w to drive the motor 14, and this motor control device 50 is configured. High side timing training The circuit 30H and the low-side timing correction circuit 30L are in two phases of the UVW phase for each of the high-side IGBT 21h (21uh, 21vh, 21wh) and / or each of the low-side IGBT 21l (21ul, 21vl, 21wl). The timings of the PWM drive signals Hd (UHd, VHd, WHd) and Ld (ULd, VLd, WLd) are manipulated so that the turn-on timings of the phases and the turn-on timings of the other phases are shifted.

  Therefore, in the motor control device 50, it is possible to reliably avoid the occurrence of an excessive surge current that may be generated by simultaneously turning on the switching elements of a plurality of phases at a certain timing.

  In the embodiment described above, avoidance of simultaneous turn-on has been described. However, it is possible to easily apply a modified circuit to avoid simultaneous turn-off. Further, although the description has been given with respect to three phases, it goes without saying that the circuit can be modified and applied to a motor control device of five phases or the like.

  In the above embodiment, the high-side timing correction circuit 30H detects that the U-phase PWM drive signal SUH and the V-phase PWM drive signal SVH supplied to the high-side timing correction circuit 30H are signals that are turned on simultaneously. In addition, since the timing is shifted by adding the on-delay time Ton to the PWM drive signal VHd of one phase, in this case V-phase, the design guideline of the timing correction circuit becomes clearer and the circuit configuration is simplified. it can.

  In this case, the on-delay time Ton is set equal to or slightly longer than the generation time of the surge current Ip {delay time (attenuation time) Td that is the time for the surge current Ip to decay to about 10%}, etc. Since it is set according to the generation time, the generation of twice the surge current can be avoided reliably, and the modulation of the motor 14, for example, the generation of the third harmonic can be suppressed to the minimum.

  Here, since the period of the reference clock CLK is adjusted to the on-delay time Ton so as to correspond to the time delayed by one clock CLK, the design guideline of the high-side timing correction circuit 30H becomes much clearer and the circuit The configuration can be simplified. Of course, if the period of the clock CLK does not correspond to the delay time Td in which the surge current Ip is generated, the on-delay time Ton corresponding to the clock corresponding to the delay time Td in which the surge current Ip is generated is set. You only have to set it.

  As described above, according to the above-described embodiment, the timings of the PWM drive signals UHd, VHd, and WHd are shifted so that the IGBTs 21h (21uh, 21vh, 21wh) between the phases do not turn on at the same time. In the control device 50, it is possible to reliably avoid the occurrence of an excessive surge current (instantaneous current) that may be generated by simultaneously turning on the two-phase IGBTs at a certain timing. In this embodiment, the surge current peak can be reduced to about half.

  Note that the present invention is not limited to the above-described embodiment, and it is needless to say that various configurations can be adopted based on the contents described in this specification.

1 is a circuit block diagram showing a configuration of a motor control device according to an embodiment of the present invention. FIG. 2 is a detailed logic circuit diagram showing a configuration of a high-side timing correction circuit in the motor control apparatus of FIG. 1 example. 3 is a timing chart of the high-side timing correction circuit of FIG. 2 example. FIG. 3 is a logic circuit diagram that more simply represents a detailed logic circuit of the high-side timing correction circuit of FIG. 2 example; 4 is a time chart showing a predetermined section in a more detailed manner in the timing chart shown in FIG. 3. It is a circuit block diagram which shows the structural example of the motor control apparatus which concerns on a prior art. FIG. 7A is an explanatory diagram showing a triangular wave and a sine wave to be compared, and FIG. 7B is a waveform diagram of a PWM drive signal as a comparison result. 8A is an explanatory diagram showing a triangular wave to be compared and a three-phase sine wave, FIG. 8B is a waveform diagram of a U-phase high-side PWM drive signal as a comparison result, and FIG. 8C is a V-phase high-side PWM drive as a comparison result. FIG. 8D is a waveform diagram of a W-phase high-side PWM drive signal as a comparison result. It is explanatory drawing of the surge electric current when two-phase high side IGBT turns on simultaneously.

Explanation of symbols

DESCRIPTION OF SYMBOLS 2, 50 ... Motor control apparatus 4 ... DC power supply 5 ... Smoothing capacitor 6 ... Inverter circuit 11 ... U-phase arm 12 ... V-phase arm 13 ... W-phase arm 16 ... Current sensor 18 ... Motor control ECU 20 ... Gate drive circuit 21uh, 21vh, 21wh, 21ul, 21vl, 21wl ... IGBT
22 ... Triangular wave 24 ... Sine wave 24u ... U phase sine wave 24v ... V phase sine wave 24w ... W phase sine wave 30H ... High side timing correction circuit 30L ... Low side timing correction circuit

Claims (5)

A coil of each phase of the motor at each midpoint of the high-side switching element and the low-side switching element of an inverter circuit in which a plurality of series circuits of a high-side switching element and a low-side switching element are connected between DC power sources to form a bridge circuit In a motor control device for driving the motor by supplying an alternating current to the coil by applying a PWM drive signal to the high-side switching element and the low-side switching element to turn it on or off,
A timing correction circuit for manipulating the timing of the PWM drive signal so that the turn-on timing of a certain phase and the turn-on timing of another phase shift with respect to each of the high-side switching elements or the low-side switching elements. A motor control device comprising: A coil of each phase of the motor at each midpoint of the high-side switching element and the low-side switching element of an inverter circuit in which a plurality of series circuits of a high-side switching element and a low-side switching element are connected between DC power sources to form a bridge circuit In a motor control device for driving the motor by supplying an alternating current to the coil by applying a PWM drive signal to the high-side switching element and the low-side switching element to turn it on or off,
A timing correction circuit that manipulates the timing of the PWM drive signal so that the turn-on timing of one phase and the turn-on timing of another phase are shifted with respect to each of the high-side switching element and the low-side switching element. A motor control device comprising: The motor control device according to claim 1 or 2,
The timing correction circuit includes:
When it is detected that the PWM drive signal of one phase and the PWM drive signal of the other phase supplied to the timing correction circuit are signals to be turned on at the same time, an on-delay time is added to the PWM drive signal of one phase. The motor control device characterized by shifting. The motor control device according to claim 3, wherein
The motor control device according to claim 1, wherein the on-delay time is set according to a generation time of a surge current that flows when the high-side switching element or the low-side switching element is turned on. In the motor control device according to claim 3 or 4,
The motor is characterized in that the on-delay time is determined such that the period of the reference clock corresponds to a time delayed by one clock when the timing correction circuit is composed of a logic circuit that operates by a reference clock. Control device.

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