JP2011072075A - Power semiconductor drive - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce dead time equivalent to a difference of on/off delay time of an insulation transfer circuit without increasing the size and cost of an inverter. <P>SOLUTION: A control computing section 11 and a PWM signal generation section 12 generate a first drive pulse signal for driving a power semiconductor device 33up, and a second drive pulse signal for driving a power semiconductor device 33un. A PWM output section 13 outputs the first drive pulse signal having a positive logic from an amplifier 13a, and outputs the second drive pulse signal having a negative logic from an inverting amplifier 13b. The insulation transfer circuit 21a electrically insulates the first drive pulse signal having a positive logic for transfer to an amplifier 22a. The insulation transfer circuit 21b electrically insulates the second drive pulse signal having a negative logic for transfer to an inverting amplifier 22b. The amplifier 22a drives the power semiconductor device 33up, and the inverting amplifier 22b inverts the second drive pulse signal having a negative logic to drive the power semiconductor device 33un. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a power semiconductor drive device for driving a power semiconductor constituting an inverter or a converter.

  In an inverter in which power semiconductor elements such as IGBTs are connected in series as an upper arm and a lower arm and are driven so as to be alternately turned on, the upper and lower arms are simultaneously turned on to prevent short circuit current from flowing. A dead time which is a time when the elements are simultaneously turned off is provided.

  This dead time is determined by a control unit that outputs a switching signal so that the dead time at the power semiconductor element input unit satisfies the following formula (1) in consideration of the delay time of the power semiconductor element and its drive circuit. It is set in advance.

Tdead '= Tdead + Td-on-Td-off> 0 (1)
Tdead: Dead time generated by the control unit Tdead ': Dead time at the power semiconductor element input unit Td-on: On delay time Td-off: Off delay time (Td-on, Td-off includes a signal Including rise time Tr and fall time Tf)
In the conventional inverter, the PWM signal for driving the power semiconductor is supplied to the drive circuit via the photocoupler in order to prevent noise from the high voltage part to the low voltage part and to ensure safety. The

  In the photocoupler, a light emitting diode emits light by an input current, and this light is converted into an output current by a phototransistor. However, because of the influence of the lifetime of the base carrier of the phototransistor and the Miller integration effect that negative feedback from the collector to the base changes from the on delay time required for the phototransistor to change from off to on, it changes from on to off. The off-delay time required for is significantly longer (Non-patent Document 1).

  Accordingly, since the delay time for the phototransistor is Td-on-Td-off <0, in order to secure a positive value as Tdead 'in the equation (1), it is necessary to provide a large value as the dead time Tdead. was there.

  To solve this problem, the technique described in Patent Document 1 includes a phase adjustment circuit that delays the rise time or fall time of the drive signal in the drive circuit of the inverter. Thus, the dead time required for driving the inverter circuit is reduced by making the rise delay time and the fall delay time as the whole drive circuit equal, thereby improving the output characteristics of the inverter.

JP 2008-125342 A

"Response speed of general-purpose photocouplers", NEC Electronics, [URL] http://www.necel.com/opto/en/technology/speed/index.htm

  However, the conventional driving circuit has a configuration in which the rising delay time and the falling delay time of the entire driving circuit are matched by newly providing a phase adjustment circuit that adds a delay time to the rising or falling edge of the driving signal. Therefore, there is a problem that the number of parts constituting the drive circuit is increased, and accordingly, the size and cost of the inverter are increased.

  In order to solve the above problems, the present invention includes a PWM control unit that generates drive pulse signals for driving the power semiconductor elements of the upper arm and the power semiconductor elements of the lower arm based on the voltage command values, A drive circuit that drives the power semiconductor element of the upper arm and the power semiconductor element of the lower arm, and an insulation transmission circuit that electrically insulates the drive pulse signal and transmits the drive pulse signal from the PWM control unit to the drive circuit. The power semiconductor drive device is characterized in that the transmission polarity of the upper arm drive pulse signal and the transmission polarity of the lower arm drive pulse signal by the insulation transmission circuit are different from each other.

  According to the present invention, it is possible to reduce the dead time corresponding to the ON / OFF delay difference caused by the insulated transmission circuit without increasing the size and cost of the inverter, and to improve the voltage usage rate. There is an effect that can be done.

It is a block diagram which shows the structure of the inverter system provided with the semiconductor drive circuit for electric power which concerns on this invention. It is a block diagram which shows the control part in Example 1-5, the power semiconductor element for 1 arm, and its drive part. FIG. 3 is a timing chart showing the operation of FIG. 2. It is a block diagram which shows the control part in Example 2, and the power semiconductor element for 1 arm, and its drive part. It is a block diagram which shows the control part in Example 3, and the power semiconductor element for 3 arms, and its drive part. It is a block diagram which shows the control part in Example 4, and the power semiconductor element for 3 arms, and its drive part. FIG. 10 is a block diagram illustrating a control unit, a power semiconductor element for three arms, and a driving unit thereof in Example 5. It is a circuit diagram which shows the structural example of the insulation transmission circuit by a photocoupler.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a configuration diagram showing a configuration of a motor / inverter system using a first embodiment of a power semiconductor drive circuit according to the present invention. In FIG. 1, an inverter circuit 30 includes a DC power source 31, a capacitor 32, and power semiconductor elements 33up to 33wn, and outputs a three-phase AC voltage for driving a motor generator (hereinafter abbreviated as MG) 50. To do. The DC power supply 31 and the capacitor 32 supply a stable DC power supply, and the power semiconductor elements 33up to 33wn are constituted by, for example, IGBTs, MOS-FETs, and diodes, and perform a switching operation based on a drive signal applied to the gate. .

  Current sensor 40 detects three-phase alternating currents Iu, Iv, and Iw output from inverter circuit 30. The position sensor 60 detects the position of the rotor in the MG 50.

  The PWM control unit 10 performs a control calculation based on information detected by the current sensor 40 and the position sensor 60, and generates a PWM signal for switching the power semiconductor elements 33up to 33wn.

  The drive units 20up to 20wn receive the PWM signal from the PWM control unit 10 and output drive signals for the power semiconductor elements 33up to 33wn. Since the inverter circuit 30 is operated by a high voltage DC power source 31, an insulation transmission circuit that insulates the PWM control unit, which is a low voltage unit, from the high voltage unit is provided inside the drive units 20up to 20wn. , Prevents malfunctions due to noise from the high-voltage part to the low-voltage part and ensures the safety of the human body.

  FIG. 2 is a block diagram in which the PWM control unit 10 and the power semiconductor elements 33up and 33un for one arm of the U phase and the driving units 20up and 20un are extracted. Although not shown, the same applies to the V phase and the W phase.

  The PWM control unit 10 includes a control calculation unit 11, a PWM signal generation unit 12, and a PWM output unit 13. The control calculation unit 11 calculates and outputs a U-phase command value, a V-phase command value, and a W-phase command value for controlling the MG 50 based on the command value and information detected by the current sensor 40 and the position sensor 60. The PWM signal generation unit 12 generates a PWM signal for turning on / off the power semiconductor elements 33up to 33wn by comparing the command value of each phase output from the control calculation unit 11 with a carrier (for example, a triangular wave). , Output to the PWM output unit 13.

  The PWM output unit 13 does not invert the polarity of the PWM signal of the upper arm, and amplifies the current by amplifying and outputting the current to drive the insulation transmission circuit 21a, and amplifies the current by inverting the polarity of the PWM signal of the lower arm. And an inverting amplifier 13b for driving the insulating transmission circuit 21b.

  The drive unit 20up includes an insulation transmission circuit 21a and an amplifier 22a. The drive unit 20un includes an insulation transmission circuit 21b and an inverting amplifier 22b.

  The insulation transmission circuits 21a and 21b have the same internal configuration, and are, for example, the insulation transmission circuit 21 as shown in FIG. The insulating edge transmission circuits 21a and 21b are configured by using an insulating transmission element such as a photocoupler, and electrically insulate the PWM signal output from the PWM control unit 10 to provide an amplifier 22a and an inverting amplifier that are high voltage units. 22b.

  In FIG. 8, the photocoupler 71 includes a light emitting diode 71a and a phototransistor 71b. The cathode of the light emitting diode 71a is connected to the input terminal In, and the anode of the light emitting diode 71a is connected to the power source (for example, + 5V) of the low voltage device (PWM control unit 10) via the resistor 72. The emitter of the phototransistor 71b is connected to the ground of the high voltage device (inverter circuit 30), and the collector of the phototransistor 71b is connected to the control power supply of the high voltage device via the resistor 73.

  In the insulated transmission circuit 21 configured as described above, when the input terminal In is at a high level, no current flows through the light emitting diode 71a, and the light emitting diode 71 does not emit light. Accordingly, no light is incident on the phototransistor 71 b and no collector current flows, so that the output terminal Out is at a high level pulled up by the resistor 73. When the input terminal In is at a low level, a current flows to the light emitting diode 71a through the resistor 72, and the light emitting diode 71 emits light. Therefore, light enters the phototransistor 71b and a collector current flows, and the output terminal Out is at a low level. Therefore, the insulation transmission circuit 21 is a circuit that transmits a positive logic input to a positive logic output (or a negative logic input to a negative logic output).

  The amplifier 22a amplifies the current of the positive logic PWM signal input from the insulation transmission circuit 21, and outputs the amplified signal to the gate of the power semiconductor element 33up. The inverting amplifier 22b amplifies the current of the negative logic PWM signal input from the insulation transmission circuit 21, reverses the polarity, and outputs the result to the gate of the power semiconductor element 33un.

  In the present embodiment, the upper arm side PWM signal (point up2) output from the PWM output unit 13 to the drive unit 20up is positive logic, and the lower arm side PWM signal (point is output from the PWM output unit 13 to the drive unit 20un). This has been described with a specific example in which un2) is negative logic. It is also possible to configure this upside down, and the same effect can be obtained in both cases.

  Conventionally, the upper and lower arm drive signals output from the PWM output unit 13 to the drive units 20up and 20un output PWM signals with the same polarity. However, since the insulation transmission circuits 21a and 21b using photocouplers have a Td-off later than the Td-on, the dead times Tdead 'at the gate terminals of the power semiconductor elements 33up and 33un are Td-on and Td. Since the time corresponding to the on / off delay difference of -off is decreased, the dead time must be generated in the PWM control unit 10 in consideration of this amount in advance.

  FIG. 3 is a timing chart showing the operation of this embodiment, and shows voltage waveforms at respective points in FIG. FIG. 3A shows a signal at point up 1 (= signal at point up 2), which is an upper arm drive signal output from the PWM signal generation unit 12 and the PWM output unit 13. FIG. 3B is a signal at the point up3, and shows the on / off state of the output of the insulation transmission circuit 21a (photocoupler) driven by the signal of FIG. FIG. 3C shows the signal at point up4, which is the gate voltage of the power semiconductor element 33up that is the upper arm. FIG. 3D shows a signal at the point un1, which is a lower arm drive signal output from the PWM signal generator 12. FIG. 3E shows a signal at point un2, which is a lower arm drive signal output from the PWM output unit 13, and is a signal obtained by inverting the polarity of the signal shown in FIG. FIG. 3 (f) is a signal at point un3, and shows the on / off state of the photocoupler of the insulation transmission circuit 21b driven by the signal (e). FIG. 3G shows the signal at point un4, which is the gate voltage of the power semiconductor element 33un, which is the lower arm.

  As apparent from FIGS. 3A and 3D, the PWM signal generator 12 provides the dead time Tdead when the upper arm drive signal and the lower arm drive signal are both turned off at the time of rising and falling. ing.

  When the voltage at the point up1 in FIG. 3A falls, the photocoupler of the insulation transmission circuit 21a transitions from OFF to ON, and the power semiconductor element 33up transitions from ON to OFF with a delay of Td-off-up. To do. Next, after Tdead has elapsed since the voltage at the point up1 in FIG. 3A falls, the voltage at the point un1 in FIG. 3D rises and the voltage at the point un2 in FIG. 3E falls. Thereby, as shown in FIG.3 (f), the photocoupler of the insulation transmission circuit 21b changes from OFF to ON. Then, the power semiconductor element 33un shifts from OFF to ON with a delay of Td-on-un from the rise of the voltage at the point un1 in FIG. Therefore, when the time from when the power semiconductor element 33up of the upper arm is turned off to when the power semiconductor element 33un of the lower arm is turned on is Tdead ', Expression (2) is obtained.

Tdead '= Tdead + Td-on-un-Td-off-up (2)
Here, the delay time Td-off-up from off to on of the insulation transfer circuit 21a and the delay time Td-on-un from off to on of the insulation transfer circuit 21b are substantially within the range of variation of elements. Since Td-on-un≈Td-off-up, equation (3) is established.
Tdead '≒ Tdead (3)

  When the voltage at the point un1 in FIG. 3D falls, the voltage at the point un2 in FIG. 3E rises, and the photocoupler of the insulation transfer circuit 21b changes from on to off. However, as described in the background art, the on-to-off transition of the photocoupler takes more time than the off-to-on transition. The voltage at point un4 falls with a delay of Td-off-un from the fall of the voltage at point un1 in FIG. 3D, and the power semiconductor element 33un of the lower arm transitions from on to off.

  On the other hand, the voltage at the point up1 in FIG. 3A rises with a delay of Tdead from the fall of the voltage at the point un1 in FIG. The insulation transfer circuit 21ba photocoupler transitions from on to off by the rise of the voltage at the point up1. However, as described above, the transition from on to off of the photocoupler takes more time than the transition from off to on. The voltage at the point up4 falls with a delay of Td-on-up from the rise of the voltage at the point up1 in FIG. 3A, and the power semiconductor element 33up of the upper arm changes from off to on. Therefore, if the time from when the lower-arm power semiconductor element 33un is turned off to when the upper-arm power semiconductor element 33up is turned on is Tdead ', Expression (4) is obtained.

Tdead '= Tdead + Td-on-up-Td-off-un (4)
Here, the delay time Td-off-un from on to off of the insulation transmission circuit 21b and the delay time Td-on-up from on to off of the insulation transmission circuit 21a are substantially within the range of variation of elements. Since Td-off-un≈Td-on-up, equation (5) is established.
Tdead '≒ Tdead (5)

  As described above, in this embodiment, the PWM output unit 31 outputs the upper arm drive signal with positive logic and the lower arm drive signal with negative logic. When switching from on to off, the lower arm drive signal insulation transmission circuit 21b changes from on to off, and when the upper arm drive signal insulation transmission circuit 21a transitions from off to on, the lower arm drive The insulation transmission circuits 21a and 21b are switched in the same direction such that the signal insulation transmission circuit 21b transitions from OFF to ON.

  Therefore, as shown in the equations (3) and (5), Td-on-un≈Td-off-up and Td-off-un≈Td-on-up, so that Tdead≈Tdead ′ The dead time generated by the PWM control unit 10 is given to the gate of the power semiconductor element as it is. Accordingly, it is possible to reduce the dead time corresponding to the ON / OFF delay difference caused by the insulating transmission circuit 21 considered in setting Tdead.

  As described above, according to this embodiment, the dead time can be reduced without increasing the size and cost of the inverter, the pulse utilization rate in PWM control is improved, and the inverter has good output characteristics. There is an effect that can be provided.

  Next, a second embodiment of the power semiconductor drive circuit according to the present invention will be described. The overall system configuration of the second embodiment is the same as that shown in FIG. FIG. 4 is a block diagram in which the PWM control unit 10 and the power semiconductor elements 33up and 33un for one arm of the U phase and the driving units 20up and 20un are extracted. A command value correction unit 14 is added to FIG. The V-phase and W-phase are also provided with a similar command value correction unit 14. Since other configurations are the same as those in FIG. 2, the same components are denoted by the same reference numerals and redundant description is omitted.

  The command value correction unit 14 has a function of offsetting the voltage command value received from the control calculation unit 11 to the high voltage side by a predetermined value and outputting it to the PWM signal generation unit 12.

  In the voltage waveform at point UP1 in FIG. 3A which is an operation timing chart of the first embodiment, the high-level section of the upper arm side PWM signal generated by the PWM signal generation unit 12 is set as Th-up, and FIG. The high level section of the PWM signal at the point up4 in (c) is set as Th-up ′.

  At this time, there is a relationship Th-up '= Th-up + (Td-off-up-Td-on-up). In the example of FIG. 3, Td- is caused by the influence of the on / off delay difference of the insulating transmission circuit 21a. Since off-up <Td-on-up, the PWM signal reaching the gate of the power semiconductor element 33up is greater than the PWM pulse width generated by the PWM controller 10 | Td-off-up-Td-on-up | Becomes shorter. Similarly, the high level section of the PWM signal at the point un1 on the lower arm side shown in FIG. 3D is set as Th-un, and the high level section of the PWM signal at the point un4 in FIG. far.

  At this time, the relationship is Th-un '= Th-un + (Td-off-un-Td-on-un). In the example of FIG. 3, Td-off is affected by the on / off delay difference of the insulating transmission circuit 21b. Since -un> Td-on-un, the PWM signal reaching the gate of the power semiconductor element 33un is about | Td-off-un-Td-on-un | than the PWM pulse width generated by the PWM controller 10. become longer.

  The command value correction unit 14 offsets the voltage command value, which is the control calculation result of the control calculation unit 11, by a predetermined value to the high voltage side and outputs the offset to the PWM signal generation unit 12. As a result, the pulse widths of the drive signal output to the upper arm side power semiconductor 33up and the drive signal output to the lower arm side power semiconductor 33un are imbalanced and the inverter output voltage is lowered to the low voltage side. There is an effect that the offset is canceled and the voltage utilization rate in the inverter output is improved.

  The present embodiment has been described with a specific example in which the upper arm side drive unit 20up is positive logic and the lower arm side drive unit 20un is negative logic. When this is configured in the opposite direction of the upper and lower arms, the PWM signal input to the upper arm side drive unit 20up is negative logic, and the PWM signal input to the lower arm side drive unit 20un is positive logic, The value correction unit 14 can obtain the same effect as described above by offsetting the voltage command value received from the control calculation unit 11 to the low voltage side by a predetermined value and outputting it to the PWM signal generation unit 12.

  As described above, according to this embodiment, the dead time can be reduced without increasing the size and cost of the inverter, the pulse utilization rate in PWM control is improved, and the inverter has good output characteristics. There is an effect that can be provided.

  In addition, according to the present embodiment, the command value correction unit for offsetting the voltage command value output to the PWM signal generation unit by a predetermined value positively or negatively is provided, so that the drive signal output to the upper arm side power semiconductor and There is an effect that the imbalance of the pulse width of the drive signal output to the lower arm side power semiconductor and the accompanying offset of the inverter output voltage are canceled, and the voltage utilization rate at the inverter output is improved.

  Next, a third embodiment of the power semiconductor drive circuit according to the present invention will be described. The overall system configuration of the third embodiment is the same as that shown in FIG. FIG. 5 shows the PWM control unit 10 and the power semiconductor elements 33up, 33un, 33vp, 33vn, 33wp, 33wn and the driving units 20up, 20un, 20vp, 20vn, 20wp, 20wn of this embodiment extracted for the three arms. It is a block diagram which shows a structure.

  When a failure that stops the operation of the PWM control unit 10 occurs and the input of the PWM signal is stopped, the signal transmission of the insulation transmission circuits 21a and 21b is cut off, so that the output becomes a high level. For example, according to the first embodiment, the drive unit 20up on the U-phase upper arm side is positive logic, the drive unit 20un on the U-phase lower arm side is negative logic, the drive unit 20vp on the V-phase upper arm side is negative logic, and the V-phase lower arm side In the case where an inverter is configured by arranging a positive logic circuit in the drive unit 20 vn of the U-phase, if a failure occurs that stops the entire PWM control unit 10, the drive unit 20 up on the U-phase upper arm side and the V-phase lower arm side The drive unit 20 vn continues to output a high level signal to the gates of the corresponding power semiconductor elements 33 up and 33 vn and turns them on. As a result, a high voltage is continuously applied to the U-phase winding and the V-phase winding of MG50, leading to an overcurrent.

  In this embodiment, as shown in FIG. 5, the three-phase upper arms and the lower arms constituting the inverter are configured to turn on and off the power semiconductor element drive circuit with the same polarity logic. Thus, even when a failure occurs that interrupts the input signals to the insulating transmission circuits 21a and 21b, the power semiconductor element of the upper arm and the power semiconductor element of the lower arm are not turned on at the same time. . Accordingly, it is possible to prevent the occurrence of an overcurrent that passes between the upper and lower arms when the PWM control unit 10 fails such that the inputs of the insulating transmission circuits 21a and 21b are cut off.

  Further, the inverter output voltage offset generated by the configuration in which the polarity of the PWM signal of the upper arm and the polarity of the PWM signal of the lower arm, which are described in the second embodiment, are transmitted by the insulating transmission circuits 21a and 21b is described in the following. Since the three phases are offset in the same direction by adopting the configuration, there is an effect that the line voltage is canceled.

  In FIG. 5, the upper arms of the three phases are configured with positive logic, and the lower arms of the three phases are configured with negative logic. Conversely, the upper arms are configured with negative logic and the lower arms are configured with positive logic. By doing so, the same effect can be obtained.

  As described above, according to this embodiment, the dead time can be reduced without increasing the size and cost of the inverter, the pulse utilization rate in PWM control is improved, and the inverter has good output characteristics. There is an effect that can be provided.

  In addition, according to the present embodiment, the upper and lower arms of the three phases constituting the inverter are configured to turn on and off the drive circuit of the power semiconductor element with the same polarity logic. There is an effect that it is possible to prevent the occurrence of overcurrent penetrating between the upper and lower arms in the event of a failure of the PWM control unit 10 in which the inputs of the insulating transmission circuits 21a and 21b are cut off.

  Next, a power semiconductor drive circuit according to a fourth embodiment of the present invention will be described. The overall system configuration of the fourth embodiment is the same as that shown in FIG. FIG. 6 shows the present embodiment in which the PWM control unit 10 and the power semiconductor elements 33up, 33un, 33vp, 33vn, 33wp, 33wn and the driving units 20up, 20un, 20vp, 20vn, 20wp, 20wn for three arms are extracted. It is a block diagram which shows a structure. Three PWM monitoring circuits 23 for monitoring the U-phase, V-phase, and W-phase PWM signals are added to FIG. The PWM monitoring circuit 23 monitors the PWM signal received from the insulation transmission circuit 21a, and outputs a gate to the power semiconductor elements 33up, 33vp, and 33wp when the high level state continues for a certain time (for example, PWM carrier cycle) or more. A shutdown operation is performed to force the drive signal to a low level.

  In the configuration of FIG. 5 of the third embodiment, when a failure that stops the operation of the PWM control unit 10 occurs and the input of the PWM signal stops, the insulation transmission circuit 21a turns off the signal transmission, so the output is Become a high level. Therefore, a high level signal is continuously output to the gates of the power semiconductor elements 33up, 33vp, and 33wp, and all of them are turned on simultaneously. Since this is a three-phase short-circuited state, if this state continues while the MG 50 is rotating, an overcurrent is caused by the induced voltage.

  In this embodiment, when a failure that causes the PWM control unit 10 to stop operating occurs, the PWM monitoring circuit 23 detects this failure and forcibly outputs a gate drive signal to be output to the power semiconductor elements 33up, 33vp, and 33wp. Shut down operation to low level. As a result, the power semiconductor elements 33up, 33vp, and 33wp are all turned off, and no overcurrent flows through the MG 50.

  As described above, according to this embodiment, the dead time can be reduced without increasing the size and cost of the inverter, the pulse utilization rate in PWM control is improved, and the inverter has good output characteristics. There is an effect that can be provided.

  Further, according to the present embodiment, it is possible to prevent the occurrence of an overcurrent that passes between the upper and lower arms when the PWM control unit 10 fails such that the inputs of the insulated transmission circuits 21a and 21b are cut off. There is an effect.

  Further, according to the present embodiment, even when a failure that causes the PWM control unit 10 to stop operating occurs and the input of the PWM signal is stopped, after the high-level output state of the insulation transmission circuit 21 has elapsed for a certain period of time, Since the power semiconductor elements 33up, 33vp, 33wp of the upper arm are turned off, there is an effect that an overcurrent due to a three-phase short circuit can be prevented when the PWM control unit 10 fails.

  Next, a fifth embodiment of the power semiconductor drive circuit according to the present invention will be described. The overall system configuration of the fifth embodiment is the same as that shown in FIG. FIG. 7 shows the present embodiment in which the PWM control unit 10 and the power semiconductor elements 33up, 33un, 33vp, 33vn, 33wp, 33wn and the driving units 20up, 20un, 20vp, 20vn, 20wp, 20wn for three arms are extracted. It is a block diagram which shows a structure. In contrast to FIG. 5, PWM mutual monitoring circuits 24a, 24b, and 24c are added to the drive units 20up, 20vp, and 20wp for each phase.

  The PWM mutual monitoring circuits 24a, 24b, and 24c receive the logical value of the output of the insulation transmission circuit 21a of the phase to which each belongs and the logical value of the output of the other two-phase insulation transmission circuit 21a, and these three input logical values Monitor each other. If any one of the PWM mutual monitoring circuits 24a, 24b, and 24c detects a state in which three logical values are equal to each other for a predetermined time (for example, a PWM carrier cycle), the remaining PWM mutual monitoring circuits are detected. An abnormality detection signal is output. As a result, when a failure occurs that causes the PWM control unit 10 to stop operating, the power semiconductor elements 33up, 33vp, and 33wp of the upper arm of each phase are turned off.

  As described above, according to this embodiment, the dead time can be reduced without increasing the size and cost of the inverter, the pulse utilization rate in PWM control is improved, and the inverter has good output characteristics. There is an effect that can be provided.

  Further, according to this embodiment, it is possible to prevent the occurrence of an overcurrent that short-circuits the upper and lower arms when the PWM control unit 10 fails such that the inputs of the insulated transmission circuits 21a and 21b are cut off. There is an effect.

  Furthermore, according to the present embodiment, even if a failure that causes the PWM control unit 10 to stop operating occurs and the input of the PWM signal stops, the power semiconductor elements 33up, 33vp, 33wp of the upper arm are turned off. There is an effect that an overcurrent due to a three-phase short circuit can be prevented when the PWM control unit 10 fails.

10: PWM control unit 11: control calculation unit 12: PWM signal generation unit 13: PWM output unit 13a: amplifier 13b: inverting amplifier 14: command value correction unit 20up, 20un, 20vp, 20vn, 20wp, 20wn: drive unit 21a, 21b: Insulation transmission circuit 22a: Amplifier 22b: Inverting amplifier 23: PWM monitoring circuits 24a, 24b, 24c: PWM mutual monitoring circuit 30: Inverter circuit 31: DC power supply 32: Capacitors 33up, 33un, 33vp, 33vn, 33wp, 33wn: Power semiconductor element 40: current sensor 50: motor generator (MG)
60: Position sensor 71: Photocoupler 71a: Light emitting diode 71b: Phototransistors 72, 73: Resistance

Claims (5)

A PWM controller that generates a first drive pulse signal for driving the power semiconductor element of the upper arm and a second drive pulse signal for driving the power semiconductor element of the lower arm based on the voltage command values, respectively;
A first drive circuit for driving the power semiconductor element of the upper arm;
A second drive circuit for driving the power semiconductor element of the lower arm;
A first insulation transmission circuit that electrically insulates and transmits a first drive pulse signal to the first drive circuit;
A second insulation transmission circuit that electrically insulates and transmits a second drive pulse signal to the second drive circuit;
In a power semiconductor drive device comprising:
A power semiconductor drive device, wherein a transmission polarity by a first insulation transmission circuit and a transmission polarity by a second insulation transmission circuit are different from each other.   2. The power control device according to claim 1, wherein the PWM control unit generates the first and second drive pulse signals after offsetting the voltage command value by a predetermined value positively or negatively in advance. Semiconductor drive device.   3. The power semiconductor drive device according to claim 1, wherein the transmission polarities of the three-phase upper arms constituting the inverter and the lower arms are equalized by the insulation transmission circuit. 4.   The operation state of the drive circuit on the transmission polarity side where the power semiconductor element is turned on when the entire PWM control unit is faulty is monitored, and when the power semiconductor element is turned on for a predetermined time, the power semiconductor element is 4. The power semiconductor drive device according to claim 3, further comprising a monitoring circuit for turning off.   When the logic of the drive circuits on the transmission polarity side where the power semiconductor element is turned on when the entire PWM control unit fails is mutually monitored, and the time when the on / off states of the plurality of drive circuits are the same continues for a predetermined time, 4. The power semiconductor drive device according to claim 3, further comprising a monitoring circuit for turning off the power semiconductor element.

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