JP2011193543A - Gate voltage controller for voltage-type inverter, gate voltage control method, and intelligent power module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a gate voltage controller for a voltage-type inverter, capable of correcting an error of a mean output voltage due to a dead time without using a current detector for detecting the output value of the inverter device. <P>SOLUTION: In the gate voltage controller for a voltage-type inverter having a configuration in which switching elements Q1-Q6 each having an antiparallel diode are connected in series, the switching elements: have current detecting sections 29 which have current detecting terminals Es for outputting small detecting currents related to main currents, and detect currents flowing through the current detecting terminals Es; gate voltage control sections 6H, 6L for controlling gate voltages applied to gates of the switching elements; and gate voltage correcting sections 12 for changing the pulse widths of the gate voltages of the gate voltage control sections in a subsequent switching period, depending on whether the current detecting section detects a current or not when the gate voltage is applied to the switching element. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention has a configuration in which switching elements having diodes connected in antiparallel are connected in series, and the switching element has a gate of a voltage source inverter having a current detection terminal that outputs a detection current correlated with a main current. The present invention relates to a voltage control device, a gate voltage control method, and an intelligent power module using a voltage source inverter.

In power converter circuits such as inverter devices and servo amplifiers, a so-called intelligent circuit that includes a switching arm composed of switching elements, a gate drive circuit that drives and protects the switching arm, and a protection circuit are built in one module. A power module (IPM) is often used.
By using this intelligent power module, it is not necessary to design a gate drive circuit, so it can be easily applied to inverter devices, and has a merit such as high reliability because it has a built-in protection circuit. Yes.

As an inverter device to which such an intelligent power module is applied, one having a configuration shown in FIG. 4 is known. FIG. 4 shows a drive control circuit for one phase of the inverter circuit.
That is, the inverter circuit shown in FIG. 4 includes a control circuit 100 that outputs a control command, an intelligent power module 102 to which a command value output from the control circuit 100 is input via the photocoupler 101, and the intelligent power module. And an electric motor 103 driven by a three-phase output current output from 102.

  The control circuit 100 adds the voltage correction value calculated by the voltage correction circuit 104 described later to the voltage command value for one phase of the three-phase voltage command values by the adder 111, and outputs the output of the adder 111 to the pulse width. The pulse width modulation signal output from the pulse width modulation circuit 112 and the inverted pulse width modulation signal logically inverted by the logic inversion circuit 113 are supplied to the dead time generation circuit 114. To give a predetermined on-delay. The dead time generation circuit 114 generates a dead time by delaying the pulse width modulation signal by a predetermined on delay time when the pulse width modulation signal changes from the off state to the on state by the on delay circuits 115a and 115b. The HS and the low side signal LS are output.

A high side signal HS and a low side signal LS output from the dead time generation circuit 114 are supplied to the intelligent power module 102 via the photocoupler 101, respectively. The intelligent power module 102 includes drive ICs 121H and 121L and an inverter circuit 122 that drives the electric motor 103.
The drive IC 121 </ b> H receives a high side signal HS, the high side signal HS is supplied to the gate drive circuit 124 via the normally closed switch circuit 123, and a gate drive signal is output from the gate drive circuit 124 to the inverter circuit 122. The The drive IC 121H has a current detection circuit 125 that detects a current flowing through the switching element of the inverter circuit 122. The detection current detected by the current detection circuit 125 is supplied to the overcurrent protection circuit 126, and this overcurrent protection circuit When the detected current exceeds the overcurrent threshold at 126, the normally closed switch circuit 123 is opened.

The drive IC 121L also has the same configuration as the drive IC 121H, and the corresponding parts are denoted by the same reference numerals, and detailed description thereof is omitted.
The inverter circuit 122 has six switching elements Q1 to Q6 configured by, for example, insulated gate bipolar transistors (IGBT), and each switching element Q1 to Q6 divides an emitter as shown in an enlarged view in FIG. Thus, the main emitter terminal Em and the sense emitter terminal Es are configured, and a small sense current correlated with the main current flowing through the main emitter terminal Em from the sense emitter terminal Es is output. The flywheel diodes D1 to D6 are connected in the reverse direction between the collector terminals of the switching elements Q1 to Q6 and the main emitter terminal Em.

  Then, three switching arms SA1 to SA3 each having two switching elements Q1 to Q6 connected in series are formed, and each of the switching arms SA1 to SA3 is provided with a positive electrode side line Lp and a negative electrode side line to which DC power is supplied. A three-phase alternating current that is connected between Ln and is output from the connection point of the switching elements Q1 and Q2, Q3 and Q4, and Q5 and Q6 of each switching arm SA1 to SA3 is output to the electric motor 103. Further, DC capacitors C1 and C2 are connected between the positive electrode side lines Lp and Ln.

Further, a current detection resistor R is connected between the sense emitter terminal Es and the main emitter terminal Em of each of the switching elements Q1 to Q6, and the terminal voltage of the current detection resistor R is the current detection circuit of the drive ICs 121H and 121L described above. 125.
The motor drive current output from the inverter circuit 122 is detected by the current detector 130 and supplied to the voltage correction circuit 104 of the control circuit 100. The voltage correction circuit 104 causes an error in the average output voltage due to dead time. I am trying to correct.

The error of the average output voltage due to this dead time will be described below with reference to FIGS.
Now, for one switching arm of the inverter circuit 122, for example, SA1, as shown in FIG. 5A, the output current Iout flows from the connection point to the electric motor 103 side at the connection point of the switching elements Q1 and Q2. It is assumed that it is on the positive electrode side of the three-phase current.
In this state, as shown in FIG. 5B, the upper arm gate drive signal output from the drive IC 121H is turned on at time t1. At this time, the gate drive signal of the lower arm output from the drive IC 121L is kept off.

  When the gate drive signal of the upper arm is turned on, the switching element Q1 on the high side of the inverter circuit 122 is turned on, and the collector current Ic flowing through the collector and emitter of the inverter circuit 122 is indicated by a broken line in FIG. And reaches a predetermined value at time t2 slightly delayed from time t1. In response to this, the collector-emitter voltage Vce of the switching element Q1 decreases from a predetermined voltage to zero as shown by a solid line in FIG.

  At this time, the switching element Q2 on the low side maintains the OFF state, and the collector current Ic flowing between the collector and the emitter maintains zero as shown by the broken line in FIG. 5 (f) and the switching element Q1 is turned on. As a result, a reverse voltage is applied to the diode D2, so that the forward current If flowing through the diode D2 becomes zero as shown in FIG. 5 (g), but the collector-emitter voltage Vce is a solid line in FIG. 5 (f). It rises to a predetermined voltage as shown.

For this reason, the output voltage of the switching arm SA1 becomes Ed / 2 that is ½ of the DC voltage Ed that is the voltage across the DC capacitor C1 shown in FIG.
After that, when the gate drive signal of the upper arm is inverted to the OFF state as shown by the broken line in FIG. 5B at time t3, the switching element Q1 is turned OFF accordingly, and therefore the collector current Ic of the switching element Q1. Decreases to zero, and accordingly, the collector-emitter voltage Vce increases to a predetermined value as shown by the solid line in FIG. 5B.

At this time, since the gate drive signal of the lower arm is delayed on to generate the dead time Td, the off state is continued. However, as the switching element Q1 is turned off, the reverse voltage is released and the diode D2 becomes forward with respect to the output current Iout, so that the current If begins to flow through the diode D2 as shown in FIG. As a result, the collector-emitter voltage Vce of the switching element Q2 is reduced to zero as shown in FIG.
In this state, since the diode D2 is connected to the DC capacitor C2, the output voltage of the switching arm SA1 decreases to -Ed / 2.

Thereafter, when the dead time Td elapses at time t4 and the gate drive signal of the lower arm is inverted to the on state, the switching element Q2 is turned on, but the direction in which the output current Iout flows can be passed to the switch element Q2. Since the direction of the current is opposite, the output current Iout continues to flow through the diode D2, and the current flowing through the switching element Q2 remains zero.
Thereafter, since the gate drive signal for the lower arm is turned off at time t5, the switching element Q2 is turned off, but the current If continues to flow through the diode D2. When the predetermined dead time Td elapses, the gate drive signal of the upper arm is inverted to the on state, so that the switching element Q1 is turned on, the collector current Ic flows and becomes the output current Iout, and the output voltage is Return to Ed / 2.

On the other hand, as shown in FIG. 6 (a), in the state where the current flows from the electric motor 103 side to the switching arm SA1, the detailed explanation is omitted, but during the dead time Td, the above is reversed. Current flows through the diode D1 connected in antiparallel with the high-side switching element Q1, and during this time, the output voltage Vout is maintained at Ed / 2.
Therefore, the time during which the output voltage Vout is maintained at Ed / 2 varies depending on the direction of the current between the switching arm SA1 and the electric motor 103, and an error in the average output voltage due to the dead time occurs. .

For this reason, in order to correct the error of the average output voltage caused by the dead time, the motor drive current output from the inverter circuit 122 to the electric motor 103 is detected by the current detector 130, and this detected current is detected by the voltage correction circuit 104. The correction voltage for correcting the error of the average output voltage caused by the dead time is generated, and this is added to the voltage command value.
As described above, in order to correct the error of the average output voltage caused by the dead time, the conventional example described below is known as a configuration for detecting the motor driving current and correcting the voltage command value.

  That is, for example, in the AC motor drive circuit, after calculating the command voltage V * [T1] for the PWM inverter, the dead time compensation voltage until the information of the detected current Ifb [T2] output from the PWM inverter in the next sampling interval is obtained. The next detection current judgment means for judging the detection current detection completion in the next sampling section and the current polarity judgment means for judging the current polarity from the detection current Ifb [T2] in the next sampling section. And dead time compensation means for outputting the dead time compensation voltage Vcomp [T2] is provided, and the dead time compensation voltage Vcomp is added to the command voltage V * [T2] calculated from the command voltage computing means by the voltage addition means. A configuration is known in which the final command voltage Vf * is calculated (see Patent Document 1). .

  In addition, the inverter output current is detected, the component near the fundamental frequency is extracted by a filter, the influence of the current ripple component is eliminated, accurate compensation is performed, and the center frequency is adjusted by using the filter as a bandpass filter. Accordingly, a dead time compensation method for a voltage source inverter has also been proposed in which phase correction corresponding to the detected current value and control delay time is easily performed.

JP 2004-15856 A JP 2009-77482 A

However, in the conventional examples described in Patent Document 1 and Patent Document 2, the correction voltage for detecting the output current supplied from the inverter to the load and compensating for the error in the average output voltage due to the dead time is provided. Therefore, a current detector that detects the output current of the inverter is necessary, and a method of detecting using a current sensor that uses a Hall element as this current detector, or a shunt as a current detection resistor There is a method to connect a resistor and detect the voltage at both ends via an insulation amplifier, but the current sensor and the insulation amplifier are relatively expensive, which is an unresolved issue that causes an increase in the cost of the inverter device There is.
Therefore, the present invention has been made paying attention to the above-mentioned unsolved problems of the conventional example, and it is possible to reduce the error of the average output voltage due to the dead time without using the current detector for detecting the output current of the inverter device. An object of the present invention is to provide a gate voltage control device and a gate voltage control method for a voltage source inverter that can be corrected.

  To achieve the above object, a gate voltage control device for a voltage source inverter according to a first aspect of the invention is a gate voltage control device for a voltage source inverter having a configuration in which switching elements having diodes connected in antiparallel are connected in series. The switching element has a current detection terminal that outputs a small detection current having a correlation with a main current, and is applied to a current detection unit that detects a current flowing through the current detection terminal and a gate of the switching element. A gate voltage control unit for controlling a gate voltage to be applied, and a gate voltage of the gate voltage control unit in a next switching period according to whether or not a current is detected by the current detection unit when a gate voltage is applied to the switching element And a gate voltage correction unit for changing the pulse width of the above.

  According to this configuration, the current flowing through the current output terminal that outputs a small detection current correlated with the main current to the switching element constituting the voltage source inverter is detected by the current detection unit, and the switching voltage of the switching element is detected by the gate voltage control unit. When a gate voltage is applied to the gate, it can be determined whether or not current is flowing through a diode connected in antiparallel by determining whether or not the current is detected by the current detection unit. Based on the determination result, the dead time start timing is changed to correct the error in the average output voltage.

  The gate voltage control apparatus for a voltage source inverter according to a second aspect of the present invention is the following, when the gate voltage correction unit detects a current with the current detection unit when a gate voltage is applied to the switching element. In the switching cycle, the gate voltage pulse width is increased by a predetermined time, and when the current detection unit does not detect the current, the gate voltage pulse width is corrected in the next switching cycle by a predetermined time. It is characterized by.

  According to this configuration, if a current flows through the switching element when a gate voltage is applied to the switching element, it is determined that no current flows through the diode during the dead time, and the gate voltage off timing is delayed by a predetermined time. If the current is not flowing through the switching element when the gate drive voltage is applied and the gate drive voltage is applied, it is determined that the current is flowing through the diode during the dead time, and the gate voltage on timing is delayed by a predetermined time. Thus, the error in the average output voltage due to the dead time is corrected by shortening the pulse width.

The gate voltage control apparatus for a voltage source inverter according to a third aspect of the present invention is the voltage type semiconductor switching device in which the switching element is at least one of an insulated gate bipolar transistor, a field effect transistor, and an electrostatic induction transistor. It is characterized by being composed.
According to this configuration, the current output terminal can be provided by dividing the current output side by the voltage source semiconductor switching element.

  A gate voltage control method for a voltage source inverter according to a fourth aspect of the invention is a gate voltage control method for a voltage source inverter having a configuration in which switching elements having diodes connected in antiparallel are connected in series, The element is provided with a current detection terminal for outputting a detection current having a correlation with a main current, the current flowing through the current detection terminal is detected, and when a gate voltage is applied to the gate of the switching element, the current is detected at the current detection terminal. When the current is flowing, the pulse width of the gate voltage is increased by a predetermined time in the next switching cycle, and when the current is not flowing through the current detection terminal, the pulse width of the gate voltage is predetermined in the next switching cycle. It is characterized by correcting the error of the average output voltage due to dead time by compensating for shortening by the time.

  According to this configuration, if a current flows through the switching element when a gate voltage is applied to the switching element, it is determined that no current flows through the diode during the dead time, and the gate voltage off timing is delayed by a predetermined time. If the current is not flowing through the switching element when the gate drive voltage is applied and the gate drive voltage is applied, it is determined that the current is flowing through the diode during the dead time, and the gate voltage on timing is delayed by a predetermined time. Thus, by shortening the pulse width, the error in the average output voltage due to the dead time can be corrected.

An intelligent power module according to a fifth aspect of the invention includes an inverter circuit having a configuration in which switching elements having diodes connected in antiparallel are connected in series, and a driver having a gate control function and a protection function for driving the inverter circuit. An intelligent power module including a circuit in one module, wherein the driver circuit includes the gate voltage control device according to any one of the first to third inventions.
According to this configuration, in the intelligent power module, it is possible to provide a driver circuit including a gate voltage control device with a simple configuration.

According to the present invention, a pulse of a gate voltage that forms a dead time by providing a current detection terminal in a switching element constituting an inverter circuit and detecting a current direction of the current detection terminal of the switching element by a gate voltage control device. By changing the width, it is possible to correct the average output voltage error due to the dead time while ensuring a predetermined dead time, and there is no need to provide a current sensor or insulation amplifier that detects the output current of the inverter circuit An inexpensive voltage source inverter can be configured.
In addition, since the intelligent power module is configured by applying the gate voltage control device to the driver circuit, an inexpensive intelligent power module can be provided.

It is a block diagram of the voltage source inverter which shows one Embodiment of this invention. FIG. 2 is a block diagram illustrating a specific configuration of a sampling trigger generation circuit and a sampling circuit in FIG. 1. It is a time chart with which it uses for description of operation | movement of the voltage source inverter of FIG. It is a block diagram which shows the voltage type inverter of a prior art example. It is operation | movement explanatory drawing when an electric current flows into the upper arm in the voltage type inverter of a prior art example. It is operation | movement explanatory drawing when an electric current flows into the arm in the voltage type inverter of the prior art example.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing an example of a voltage source inverter provided with an intelligent power module having a gate voltage control device of the present invention. FIG. 1 also shows the circuit configuration for one phase of the three-phase inverter circuit, but the other two-phase circuit configurations are the same. In the figure, reference numeral 1 denotes a control circuit, which includes a pulse width modulation (PWM) circuit 2 to which a voltage command value is input. The pulse width modulation signal output from the pulse width modulation circuit 2 is a high-side signal. HS is output directly to the intelligent power module (IPM, hereinafter simply referred to as IPM) 5 via the photocoupler 4H, and IPM5 via the logic inversion (NOT) circuit 3 as the low-side signal HL via the photocoupler 4L. Is output.

The IPM 5 includes a high-side drive IC 6H as a gate voltage control unit, a low-side drive IC 6L as a gate voltage control unit, and an inverter circuit 7. A three-phase motor drive current output from the inverter circuit 7 is provided. It is output to the three-phase motor 8.
The drive IC 6H includes a dead time generation circuit 11 that forms a gate drive signal having a predetermined gate voltage with a dead time for the signal SH input from the photocoupler 4H, and a gate output from the dead time generation circuit 11 Compensation pulse forming circuit 12 as a gate voltage correction unit that forms a gate driving pulse signal that compensates for an error in the average output voltage caused by dead time with respect to the driving signal, and a compensation gate output from the compensation pulse forming circuit 12 And a gate drive circuit 14 to which the drive signal GHc is input via the normally closed switch circuit 13.

  The dead time generation circuit 11 includes an on delay circuit 21 that delays the rising timing when the input signal SH is turned on by the dead time Td, as in the conventional example described above, and is output from the on delay circuit 21. The gate drive signal GH is supplied to the compensation pulse forming circuit 12. Further, the signal SH input from the photocoupler 4H to the on-delay circuit 21 is supplied to the sampling trigger generation circuit 22 and supplied as a trigger signal ST to a later-described sampling circuit.

  The compensation pulse forming circuit 12 has an ON delay circuit 25 that delays the shift to the ON state with respect to the input gate drive signal GH by a predetermined compensation time Tc, and an OFF state with respect to the input gate drive signal GH. The off-delay circuit 26 that delays the transition by a predetermined compensation time Tc, the multiplexer 27 that selects the delay outputs of the on-delay circuit 25 and the off-delay circuit 26 and outputs them as the compensation gate drive signal GHc, and the selection operation of the multiplexer 27 And a sampling circuit 28 to be controlled.

  Here, as shown in FIG. 2, the sampling circuit 28 detects the current output from the current detection terminal Es of the high-side switching element Q1 in the switching arm SA1 constituting the inverter circuit 7, for example, a voltage follower or the like. The current detection voltage Vd corresponding to the detection current is input from the current detection circuit 29 configured by the amplifier of FIG. 5, and the trigger signal ST is input from the sampling trigger generation circuit 22 of the dead time generation circuit 11 described above.

In the sampling circuit 28, the current detection voltage Vd input from the current detection circuit 29 is input to one end of the comparator 30, the reference voltage Vr is input to the other end of the comparator 30, and the current detection voltage Vd is output from the comparator 30. A comparison signal Sc having a logical value of “1” is output when becomes equal to or higher than the reference voltage Vr, and this comparison signal Sc is supplied to the D input terminal of the D-type flip-flop circuit 31.
The trigger signal ST output from the sampling trigger generation circuit 22 is input to the clock terminal CLK of the D-type flip-flop circuit 31 via the logic inversion (NOT) circuit 32, and at the rising edge of the output pulse of the logic inversion circuit 32. The comparison signal Sc is latched.

  The positive output terminal Q of the D-type flip-flop circuit 31 is connected to the input terminal D of the D-type flip-flop circuit 33 at the next stage. The sampling trigger generation circuit 22 is connected to the clock terminal CLK of the D-type flip-flop circuit 33. The trigger signal ST output from is supplied as it is. An output signal output from the positive output terminal Q of the D-type flip-flop circuit 33 is input to the multiplexer 27 as the selection signal SS.

The multiplexer 27 compensates by selecting the output signal of the on-delay circuit 25 and shortening the pulse width when the selection signal SS input from the sampling circuit 28 is a logical value “0”, that is, when no current flows through the switching element Q1. Compensation gate drive signal that is output as the gate drive signal GHc and has the pulse width increased by selecting the output signal of the off-delay circuit 26 when the selection signal SS is a logical value “1”, that is, when a current flows through the switching element Q1. Output as GHc.
In addition, the current detection voltage Vd detected by the current detection circuit 29 is supplied to the overcurrent protection circuit 35, and when the current detection voltage Vd becomes equal to or higher than a predetermined threshold voltage indicating an overcurrent state. Then, the normally closed switch circuit 13 is controlled to be in an open state, and the application of the gate voltage to the switching element Q1 is stopped.

  Further, the inverter circuit 7 includes switching arms SA1 to SA3 in which six switching elements Q1 to Q6 each composed of, for example, an insulated gate bipolar transistor (IGBT) with current sense are connected in series from an external DC power source. It has the structure connected in parallel between the positive electrode line Lp and the negative electrode line Ln into which direct-current power was input. In addition, each of the switching elements Q1 to Q6 is divided into two emitters, and becomes a main emitter terminal Em through which a main current flows and a current detection terminal through which a small current having a correlation with a current flowing through the main emitter terminal Em flows. It consists of a sense emitter terminal Es. Further, flywheel diodes D1 to D6 are connected in antiparallel between the collector terminals and the main emitter terminal Em of the switching elements Q1 to Q6, respectively.

And the three-phase alternating current drive current output from the connection point of switching element Q1 and Q2, Q3 and Q4 of each switching arm SA1-SA3, and Q5 and Q6 is output to the three-phase motor 8 as a load.
Further, DC capacitors C1 and C2 are connected in series between the positive electrode line Lp and the negative electrode line Ln, and their connection point is connected to the connection point of the switching elements Q1 and Q2.
Further, a current detection resistor R is connected between the sense emitter terminal Es and the main emitter terminal Em of each of the switching elements Q1 to Q6, and terminal voltages at both ends of the current detection resistor R are high side drive IC 6H and low side drive IC 6L. The current detection circuit 29 is supplied.

Next, the operation of the above embodiment will be described with reference to FIG.
Assume that the output current Iout is supplied to the three-phase motor from the connection point between the switching elements Q1 and Q2 of the switching arm SA1 as in FIG.
In this state, as described above, the diode current If flows through the flywheel diode D2 connected in antiparallel with the switching element Q2 serving as the low-side arm, as shown in FIG. 5 (h). The time when Vout becomes Ed / 2 is shorter than the desired time, and an error occurs in the average output voltage.

  However, in the above embodiment, a signal that gives the same logical value as the signal SH input from the photocoupler 4H to the ON delay circuit 21 of the dead time generation circuit 11 is supplied from the sampling trigger generation circuit 22 to the sampling circuit 28 as the trigger signal ST. Is done. In this case, the sampling trigger generation circuit 22 is realized by a voltage follower circuit to which the input signal SH is input, a non-inverting amplifier circuit, or a simple connection.

  In this sampling circuit 28, the current flowing through the sense emitter terminal Es of the switching element Q1 of the inverter circuit 7 is detected by the current detection circuit 29 as the current detection voltage Vd, and this current detection voltage Vd is supplied to the comparator 30 to be the reference voltage Vr. Compared with At this time, a current path is formed as shown in FIG. 5A, and the high-side signal HS output from the control circuit 1 is turned on at the time t11 in the same manner as the signal SH shown in FIG. 3A. The state is maintained. In response to this, the compensation gate drive signal GHc input to the gate drive circuit 14 of the high side drive IC 6H maintains the ON state at time t11 as shown in FIG. The switching element Q1 is in an on state. On the other hand, at time t11, the gate drive signal GL output from the on-delay circuit 21 of the low-side drive IC 6L is maintained in the off state as shown in FIG. Assume that it is off.

In this state, since the switching element Q1 is in the ON state, the collector current Ic flows through the collector terminal and the main emitter terminal Em of the switching element Q1, and this is output to the electric motor 8 as the output current Iout.
Thus, since the collector current Ic flows through the main emitter terminal Em of the switching element Q1, a small current correlated with the main current flows through the sense emitter terminal Es, and the terminal voltage of the current detection resistor R is Positive potential. Since this terminal voltage is supplied to the current detection circuit 29, it is amplified by the current detection circuit 29 and supplied to the overcurrent protection circuit 35 and the sampling circuit 28. At this time, when the current detection voltage Vd output from the current detection circuit 29 is less than the overcurrent threshold set by the overcurrent protection circuit 35, the overcurrent protection circuit 35 closes the normally closed switch circuit 13 in a closed state, that is, an on state. To maintain.

  On the other hand, in the sampling circuit 28, since the current detection voltage Vd output from the current detection circuit 29 is equal to or higher than the reference voltage Vr, the comparison output Sc of the comparator 30 becomes the logical value “1”. However, since the trigger signal ST output from the sampling trigger generation circuit 22 maintains the logical value “1” at this time t11, the D-type flip-flop 31 does not capture the comparison output Sc, and changes the previous state. Is maintained.

After that, when the high side signal HS output from the control circuit 1 at time t12 is turned off as in the signal SH shown in FIG. 3A, the gate drive signal output from the on delay circuit 21 of the high side drive IC 6H. As shown in FIG. 3B, the gate drive signal GH is output to invert the GH to the off state.
At this time t12, the signal SH is inverted to the OFF state, so that this signal is supplied from the sampling trigger generation circuit 22 to the sampling circuit 28 as the trigger signal ST, and logically inverted by the logic inversion circuit 32 to become a logical value “1”. Since this is supplied to the clock terminal of the D-type flip-flop 31, the D-type flip-flop 31 latches the comparison output Sc having the logical value “1”, and the output signal becomes the logical value “1”.

  Thereafter, the signal SH is turned on at time t13, and the gate drive signal GH is turned on at time t14 delayed by the dead time Td in the on delay circuit 21. On the other hand, when the trigger signal ST output from the sampling trigger generating circuit 22 is inverted to the ON state at the time t13 as in the case of the signal SH, this is input to the clock input terminal CLK of the D-type flip-flop 33. In 33, the positive output of the logical value “1” of the D-type flip-flop 31 in the previous stage is latched, and the selection signal SS output from the positive output terminal Q becomes the logical value “1”.

Since this selection signal SS is supplied to the multiplexer 27, the off delay circuit 26 is selected by this multiplexer.
For this reason, even when the gate drive signal GH output from the on delay circuit 21 of the dead time generation circuit 11 is turned off at the time t15, the off time is delayed by the predetermined off compensation time Tc in the off delay circuit 26. As shown in FIG. 3C, the gate drive signal GHc is turned off at time t16 delayed by the off compensation time Tc.
For this reason, as shown in FIG. 3G, the voltage of Ed / 2 is maintained until the time t16 when the off-compensation time Tc elapses after the output voltage Vout enters the dead time Td.

  On the other hand, in the low side drive IC, the collector current Ic does not flow between the collector and the main emitter even when the low side signal LS output from the control circuit 1 has the logical value “1” and the switching element Q2 is turned on. The current detection voltage Vd output from the current detection circuit 29 is kept lower than the reference voltage Vr of the sampling circuit 28. Therefore, the comparison output Sc of the comparator 30 becomes a logical value “0”, and after this is latched in the D-type flip-flop 31, the next D-type is output when the ON delay gate drive signal is output from the ON delay circuit 21. Since it is latched by the flip-flop 33, the selection signal SS having the logical value “0” is output from the D-type flip-flop 33 at this time, whereby the on-delay circuit 25 is selected by the multiplexer 27 and the on-state is turned on. The output of the on-delay circuit 25 whose transition is delayed is output to the gate drive circuit 14 as the compensation gate drive signal GLc. For this reason, the low-side switching element Q2 is turned on at a time point t18 delayed by a compensation time Tc from the time point t17. For this reason, a predetermined dead time Td can be secured between the compensation gate drive signal GHc and the compensation gate drive signal GLc.

  For this reason, the pulse width becomes longer by the compensation time Tc than the gate drive signal GH when the compensation gate drive signal GHc of the high side drive IC 6H does not perform compensation, and conversely, the compensation gate drive signal GLc of the low side drive IC 6L is Since the pulse width is shortened by the compensation time Tc with respect to the gate drive signal GL when the compensation is not performed, the output voltage Vout of the switching arm SA1 is as shown in FIG. ), And a voltage waveform for correcting an error due to the dead time Td.

Similarly, as shown in FIG. 6A, when the output current Iout of the switching arm SA1 flows from the three-phase electric motor 8 to the switching arm SA1, the low-side switching element Q2 is turned on, contrary to the above. In this state, a collector current Ic flows between the collector terminal and the main emitter terminal Em, and this collector current Ic is detected by the current detection circuit 29 of the low side drive IC 6L. Therefore, contrary to the above, on the low-side drive IC 6L side, the off-delay circuit 26 is selected by the multiplexer 27, and the on-delay circuit 25 is selected by the multiplexer 27 on the high-side drive IC 6H side, and the output voltage Vout is An error of the average output voltage due to the dead time can be compensated.
In rare cases, the direction of the output current may change in the next switching cycle after detecting the currents at the current detection terminals of the switching elements Q1 to Q6. The frequency in this case is once every several hundred times. It is very small and does not affect the switching element control.

  Thus, according to the above-described embodiment, the switching elements Q1 to Q6 constituting the inverter circuit 7 have, for example, an emitter, and a sense emitter terminal that outputs a detection current correlated with the main current and the main emitter terminal Em that flows the main current. The sense emitter terminal Es is provided as a current detection terminal divided into Es, and the current detected at the current detection terminal is detected by the current detection circuit 29, and the gate voltage is applied to the switching elements Q1 to Q6. When it is determined that current is flowing, and it is determined that current is flowing, the pulse width is increased by performing an off delay operation that delays the transition of the gate drive signal to the OFF state for a predetermined time. When judging, the pulse width is shortened by performing an on-delay operation that delays the transition of the gate drive signal to the on state for a predetermined time. , It is possible to form a gate drive signal for compensating the error of the mean output voltage due to dead time while ensuring a predetermined dead time in the high-side and low-side switching elements.

Therefore, it is not necessary to provide a current sensor or an insulation amplifier on the output side of the inverter circuit 7 as in the conventional example, and the error of the average output voltage due to the dead time is corrected with an inexpensive and simple circuit configuration. be able to. For this reason, the intelligent power module 5 can also have an inexpensive and simple circuit configuration.
In the above embodiment, the case where an insulated gate bipolar transistor (IGBT) is applied as the switching elements Q1 to Q6 has been described. However, the present invention is not limited to this, and a current is applied to a MOS field effect transistor or an electrostatic induction transistor. Additional detection terminals can be used.

  In the above embodiment, the case where a signal that gives the same logical value as the signals SH and SL input from the photocouplers 4H and 4L to the on delay circuit 21 of the sampling trigger generation circuit 22 is used as the trigger signal ST has been described. The trigger signal for the D-type flip-flop 33 may be formed with a differential waveform in the positive direction using a differential waveform obtained by differentiating the signal SH, and the trigger signal for the D-type flip-flop 31 may be formed with a differential waveform in the negative direction. .

Further, in the above embodiment, the case where a voltage follower amplifier circuit is applied as the current detection circuit 29 has been described. However, the present invention is not limited to this, and when the voltage between the terminals of the current detection resistor R is large to some extent. The current detection circuit 29 can be configured by simple connection.
Furthermore, in the said embodiment, although the case where the electric motor was applied as a load of the inverter circuit 7 was demonstrated, not only this but another load can be applied.

  DESCRIPTION OF SYMBOLS 1 ... Control circuit, 2 ... Pulse width modulation circuit, 4H, 4L ... Photocoupler, 5 ... Intelligent power module (IPM), 6H ... High side drive IC, 6L ... Low side drive IC, 7 ... Inverter circuit, 8 ... Three phase Electric motor, 11 ... dead time generation circuit, 12 ... compensation pulse generation circuit, 13 ... switch circuit, 14 ... gate drive circuit, 21 ... on delay circuit, 22 ... sampling trigger generation circuit, 25 ... on delay circuit, 26 ... off Delay circuit 27 ... Multiplexer 28 ... Sampling circuit 29 ... Current detection circuit 35 ... Overcurrent protection circuit C1, C2 ... DC capacitor D1-D6 ... Diode Q1-Q6 ... Switching element Em ... Main emitter terminal , Es: current detection terminal or sense emitter terminal, R: current detection resistor

Claims (5)

A gate voltage control device for a voltage source inverter having a configuration in which switching elements having diodes connected in antiparallel are connected in series,
The switching element has a current detection terminal that outputs a small detection current having a correlation with a main current,
A current detection unit for detecting a current flowing through the current detection terminal;
A gate voltage controller for controlling a gate voltage applied to the gate of the switching element;
A gate voltage correction unit that changes a pulse width of the gate voltage of the gate voltage control unit in a next switching period according to whether or not a current is detected by the current detection unit when a gate voltage is applied to the switching element. A gate voltage control device for a voltage source inverter, comprising:   The gate voltage correction unit increases the pulse width of the gate voltage for a predetermined time during the next switching period when the current detection unit detects a current when the gate voltage is applied to the switching element. 2. The gate voltage control apparatus for a voltage source inverter according to claim 1, wherein when the current is not detected by the detection unit, correction is performed to shorten the pulse width of the gate voltage for a predetermined time in the next switching cycle. .   3. The voltage according to claim 1, wherein the switching element includes a voltage-type semiconductor switching element including at least one of an insulated gate bipolar transistor, a field effect transistor, and an electrostatic induction transistor. Type gate voltage controller. A gate voltage control method for a voltage source inverter having a configuration in which switching elements having diodes connected in antiparallel are connected in series,
The switching element is provided with a current detection terminal that outputs a detection current having a correlation with the main current,
When a current flowing through the current detection terminal is detected and a current flows through the current detection terminal when a gate voltage is applied to the gate of the switching element, the pulse width of the gate voltage is set to a predetermined time in the next switching cycle. When no current flows through the current detection terminal, compensation is performed to shorten the pulse width of the gate voltage by a predetermined time in the next switching cycle, and the error of the average output voltage due to the dead time is reduced. A gate voltage control method for a voltage source inverter, characterized in that correction is performed. An intelligent power module in which an inverter circuit having a configuration in which switching elements having diodes connected in anti-parallel are connected in series, and a driver circuit having a gate control function and a protection function for driving the inverter circuit are incorporated in one module. There,
The intelligent power module, wherein the driver circuit includes the gate voltage control device according to any one of claims 1 to 3.

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