CN116133389A

CN116133389A - Semiconductor structure, DRAM and manufacturing method of semiconductor structure

Info

Publication number: CN116133389A
Application number: CN202111035772.5A
Authority: CN
Inventors: 张铉瑀; 许民; 吴容哲; 李俊杰; 周娜; 李琳; 王佳; 杨红
Original assignee: Institute of Microelectronics of CAS; Zhenxin Beijing Semiconductor Co Ltd
Current assignee: Institute of Microelectronics of CAS; Zhenxin Beijing Semiconductor Co Ltd
Priority date: 2021-09-06
Filing date: 2021-09-06
Publication date: 2023-05-16

Abstract

The invention provides a semiconductor structure, a DRAM and a manufacturing method of the semiconductor structure, which relate to the technical field of semiconductors and comprise the following steps: a laminated structure formed by alternately molding oxide layers and supporting pieces is arranged on the semiconductor substrate; a contact hole is formed in the laminated structure, and a lower electrode is formed in the contact hole; the sacrificial layer is arranged on the laminated structure and is formed by a carbon-containing material; the hard mask layer is disposed on the sacrificial layer. In the above-described embodiments, the sacrificial layer is formed of a carbon-containing material, and the material can provide a certain hardness to the sacrificial layer itself, so that the sacrificial layer can be used as a sacrificial layer and a hard mask layer, and the thickness of the original hard mask layer can be reduced, and the thickness of the entire hard mask layer can be reduced.

Description

Semiconductor structure, DRAM and manufacturing method of semiconductor structure

Technical Field

The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor structure, a DRAM, and a method for manufacturing the semiconductor structure.

Background

DRAM is an element composed of a transistor and a capacitor. Among them, the capacitance of the capacitor is one of the most important factors determining the characteristics of the DRAM. Accordingly, in developing the DRAM, improvement in capacitance is being pursued. However, as the miniaturization of devices is proceeding, the size of products is continuously reduced, and thus the cross-sectional area of the capacitor is necessarily reduced, it is becoming more and more important to enlarge the height of the storage node in order to maximize the capacitance. In order to ensure that the storage nodes do not bend or fall over, the setting of the rack must be performed.

In the prior art, the hard mask layer is typically SOH of carbon sequence when forming the stent, and the thickness of the hard mask layer is an important factor in determining stent pattern dispersion. The better the dispersion of the support pattern, the more uniform the evaporation of the subsequent dielectric film, and the improved performance of the final semiconductor device, so reducing the thickness of the hard mask layer is a technical problem that needs to be solved by those skilled in the art.

Disclosure of Invention

The invention aims to provide a semiconductor structure, a DRAM and a manufacturing method of the semiconductor structure, so as to reduce the thickness of a hard mask layer and improve the performance of a semiconductor device.

The invention provides a semiconductor structure, comprising:

a semiconductor substrate;

the semiconductor substrate is provided with a laminated structure formed by alternately molding oxide layers and supporting pieces; a contact hole is formed in the laminated structure, and a lower electrode is formed in the contact hole;

a sacrificial layer disposed on the laminated structure, the sacrificial layer being formed of a carbonaceous material;

and a hard mask layer disposed on the sacrificial layer.

Further, the sacrificial layer is formed by ACL materials.

Further, the hard mask layer is formed by SOH material or carbon compound.

The application also provides a DRAM comprising the semiconductor structure; the semiconductor substrate further comprises a buried channel array transistor; one of the active regions of the buried channel array transistor is connected to a bit line and the other active region is electrically connected to a landing pad.

The application also provides a manufacturing method of the semiconductor structure, which comprises the following steps:

providing a semiconductor substrate;

forming a stacked structure comprising at least one mold oxide layer and a support alternating on the semiconductor substrate;

forming a contact hole in the laminated structure;

forming a lower electrode in the contact hole;

forming a sacrificial layer composed of a carbonaceous material on the laminated structure;

a hard mask layer is formed on the sacrificial layer.

Further, ACL materials are used for forming the sacrificial layer.

Further, SOH material or carbon compound is used to form the hard mask layer.

Further, the laminated structure is etched to form a contact hole, and a lower electrode is formed in the contact hole.

Further, the sacrificial layer is formed on the laminated structure by a vapor phase growth method.

Further, the hard mask layer is formed on the sacrificial layer in a spin coating mode.

In the above-described embodiments, the sacrificial layer is formed of a carbon-containing material, and the material can provide a certain hardness to the sacrificial layer itself, so that the sacrificial layer can be used as a sacrificial layer and a hard mask layer, and the thickness of the original hard mask layer can be reduced, and the thickness of the entire hard mask layer can be reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of steps of a manufacturing method according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of steps of a manufacturing method according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of steps of a manufacturing method according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of steps of a manufacturing method according to an embodiment of the present invention;

fig. 5 is a schematic diagram of steps of a manufacturing method according to an embodiment of the invention.

Reference numerals:

1. a semiconductor substrate; 2. a laminated structure; 3. a sacrificial layer; 4. a hard mask layer;

21. molding the oxide layer; 22. a support; 23. and a contact hole.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.

As shown in fig. 1 to 5, the semiconductor structure provided in this embodiment includes a semiconductor substrate on which a stacked structure composed of a mold oxide layer and a support alternately is provided; a contact hole is formed in the laminated structure, and a lower electrode is formed in the contact hole; the semiconductor structure further includes a sacrificial layer disposed on the stacked structure, the sacrificial layer formed of a carbon-containing material; the semiconductor structure further includes a hard mask layer disposed on the sacrificial layer. The sacrificial layer may be formed by ACL material, and the hard mask layer may be formed by SOH material or carbon compound.

Compared with the prior art, the semiconductor structure is formed by adopting a carbon-containing material as the sacrificial layer, and the material can enable the sacrificial layer to have certain hardness, so that the sacrificial layer can be used as the sacrificial layer and can also be used as the hard mask layer, the thickness of the original hard mask layer can be reduced, the whole thickness is further reduced, the scattering of the dielectric film can be improved during the subsequent dielectric film evaporation, the scattering of the capacitor can be effectively improved, and the performance of the semiconductor element can be improved.

The invention also provides a DRAM, which comprises the semiconductor structure; the semiconductor substrate further comprises a buried channel array transistor; one of the active regions of the buried channel array transistor is connected to a bit line and the other active region is electrically connected to a landing pad.

Specifically, the invention also provides a manufacturing method of the semiconductor structure, which comprises the following steps: providing a semiconductor substrate; forming a stacked structure comprising at least one mold oxide layer and a support alternating on the semiconductor substrate; forming a contact hole in the laminated structure; forming a lower electrode in the contact hole; forming a sacrificial layer composed of a carbonaceous material on the laminated structure; a hard mask layer is formed on the sacrificial layer. Wherein, the sacrificial layer can be formed by ACL material, or SOH material or carbon compound can be used to form the hard mask layer.

Since the sacrificial layer is formed of a carbon-containing material, the sacrificial layer itself has a certain hardness, and therefore, the sacrificial layer can be used as a sacrificial layer and a hard mask layer, and the thickness of the original hard mask layer can be reduced, and the thickness of the whole hard mask layer can be further reduced.

Referring to fig. 1 to 5, the stacked structure may be etched first to form a contact hole, and a lower electrode may be formed in the contact hole. Various process forms may be used in forming the contact hole, which are not limited herein. For example, when forming the contact hole, a sacrificial layer and a hard mask layer for etching the contact hole may be formed, an etching pattern may be formed on the hard mask layer, and then the sacrificial layer and the stacked structure may be etched according to the etching pattern. And forming a laminated structure formed by overlapping a molded oxide layer and a supporting layer on the semiconductor substrate, then arranging a hard mask layer on the laminated structure, forming a photoresist pattern on the hard mask layer, and patterning the hard mask layer. Then, the laminated structure is etched by using the hard mask layer pattern as a mask, thereby forming contact holes distributed in a honeycomb shape. However, the sacrificial layer and the hard mask layer are provided for forming the contact hole at this time, which is a different process stage from the re-formation of the sacrificial layer and the hard mask layer when the support pattern is formed.

Next, a lower electrode is formed in the contact hole, and for example, a lower electrode containing a material such as TiN may be formed in the contact hole by deposition. And forming staggered mask patterns on the whole semiconductor substrate with the contact holes, and continuing etching the residual laminated structure around the contact holes by taking the mask patterns as masks until openings with the depth identical to that of the contact holes are formed. And then depositing a dielectric layer and an upper electrode on the inner and outer walls of the lower electrode in the opening, wherein the upper electrode can be made of TiN, taN or doped polysilicon.

When the laminated structure has been formed with the contact hole and the lower electrode formed in the contact hole, the sacrificial layer may be formed on the laminated structure by vapor phase growth, and then the hard mask layer may be formed on the sacrificial layer by spin coating, where the sacrificial layer and the hard mask layer are used to form a supporting pattern in the laminated structure, which is a different process stage from the sacrificial layer and the hard mask layer formed when the contact hole is formed. At this time, the contact hole has been formed in the stacked structure, so after the support pattern is formed again, an etching pattern may be formed on the hard mask layer, and then the sacrificial layer and the stacked structure may be etched according to the etching pattern. The photoresist layer may be first formed on the hard mask layer, the photoresist layer may be exposed according to a predetermined pattern, and the etching pattern may be formed on the hard mask layer according to the pattern formed after the exposure.

In addition, the person skilled in the art may pattern the support layer according to other ways, which are not limited herein. Correspondingly, a contact plug matched with the lower electrode of the lower electrode is arranged below the molded structure, and the conductive pattern on the hard mask layer can be matched with the pattern of the contact plug, so that the lower electrode can be matched with the pattern of the contact plug. At this point, the patterned structures on the support may be mated with the conductive patterns of the hard mask layer.

In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.

The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.

Claims

1. A semiconductor structure, comprising:

a semiconductor substrate;

and a hard mask layer disposed on the sacrificial layer.

2. The semiconductor structure of claim 1, wherein the sacrificial layer is formed using ACL material.

3. The semiconductor structure of claim 1, wherein the hard mask layer is formed using SOH material.

4. A DRAM comprising the semiconductor structure of any of claims 1-3; the semiconductor substrate further comprises a buried channel array transistor; one of the active regions of the buried channel array transistor is connected to a bit line and the other active region is electrically connected to a landing pad.

5. A method of fabricating a semiconductor structure, comprising the steps of:

providing a semiconductor substrate;

forming a contact hole in the laminated structure;

forming a lower electrode in the contact hole;

a hard mask layer is formed on the sacrificial layer.

6. The method of claim 5, wherein the sacrificial layer is formed using ACL material.

7. The method of claim 5, wherein the hard mask layer is formed using SOH material or carbon compound.

8. The method of any one of claims 5-7, wherein the stacked structure is etched to form a contact hole, and a lower electrode is formed within the contact hole.

9. The method of claim 8, wherein the sacrificial layer is formed on the laminate structure by vapor phase growth.

10. The method of claim 9, wherein the hard mask layer is formed on the sacrificial layer by spin coating.