KR0151377B1 - Semiconductor memory device and its manufacture - Google Patents
Semiconductor memory device and its manufactureInfo
- Publication number
- KR0151377B1 KR0151377B1 KR1019940016636A KR19940016636A KR0151377B1 KR 0151377 B1 KR0151377 B1 KR 0151377B1 KR 1019940016636 A KR1019940016636 A KR 1019940016636A KR 19940016636 A KR19940016636 A KR 19940016636A KR 0151377 B1 KR0151377 B1 KR 0151377B1
- Authority
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- South Korea
- Prior art keywords
- film
- teos
- forming
- capacitor
- etch stop
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title abstract description 12
- 239000003990 capacitor Substances 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 3
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 239000012528 membrane Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 229920005591 polysilicon Polymers 0.000 description 10
- 150000004767 nitrides Chemical class 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 반도체 메모리장치의 제조방법에 관한 것으로, 대용량의 커패시터를 제조하기 위한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and to fabricating a large capacity capacitor.
본 발명은 반도체기판 소정부분에 게이트전극, 소오스 및 드레인영역을 각각 형성하여 트랜지스터를 형성하는 공정, 반도체기판 전면에 절연막과 식각저지막을 차례로 형성하는 공정, 상기 식각저지막상에 TEOS-O3막을 증착하는 공정, 상기 TEOS-O3막과 식각저지막 및 절연막을 선택적으로 식각하여 상기 트랜지스터의 소오스 또는 드레인영역을 노출시키는 매몰콘택을 형성하는 공정, 희석된 HF용액을 이용하여 상기 TEOS-O3막 표면을 세정하여 TEOS-O3막 표면에는 미세한 요철이 형성되도록 하는 공정, 상기 매몰콘택내를 포함한 TEOS-O3막상부에 제1도전층을 형성하는 공정, 상기 제1도전층과 TEOS-O3막 및 식각저지막을 커패시터 하부전극패턴 패터닝하는 공정, 상기 TEOS-O3막과 식각저지막을 차례로 제거하여 커패시터 하부전극을 형성하는 공정, 상기 하부전극 전표면에 커패시터 유전체막을 형성하는 공정, 상기 커패시터 유전체막 전면에 커패시터 대향전극을 형성하는 공정으로 이루어진다.According to the present invention, a process of forming a transistor by forming a gate electrode, a source, and a drain region on a predetermined portion of a semiconductor substrate, a process of sequentially forming an insulating film and an etch stop layer on the entire surface of the semiconductor substrate, and depositing a TEOS-O 3 film on the etch stop layer Selectively etching the TEOS-O 3 film, the etch stop film, and the insulating film to form a buried contact exposing the source or drain region of the transistor; and using the diluted HF solution, the TEOS-O 3 film to clean the surface TEOS-O 3 film surface, forming a first conductive layer on a film unit TEOS-O 3, including the step, the buried contact in which to form the fine irregularities, the first conductive layer and a TEOS-O 3 film and etch stop film capacitor lower electrode pattern patterning step, a step of removing the TEOS-O 3 film and the etch stop film in order to form a capacitor lower electrode, wherein Forming a capacitor dielectric film on the entire surface of the lower electrode; and forming a capacitor counter electrode on the entire surface of the capacitor dielectric film.
Description
제1도는 종래의 반도체 메모리장치의 커패시터 제조방법을 도시한 공정 순서도.1 is a process flowchart showing a capacitor manufacturing method of a conventional semiconductor memory device.
제2도는 본 발명의 반도체 메모리장치의 커패시터 제조방법을 도시한 공정순서도.2 is a process flowchart showing a capacitor manufacturing method of the semiconductor memory device of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 필드산화막 2 : 게이트산화막1 field oxide film 2 gate oxide film
3 : 게이트전극 5 : 소오스 및 드레인영역3: gate electrode 5: source and drain region
11 : 산화막 12 : 질화막11 oxide film 12 nitride film
13 : TEOS-O3막 14 : 제1도전층13: TEOS-O 3 film 14: first conductive layer
15 : 커패시터 유전체막 16 : 커패시터 대향전극15 capacitor dielectric film 16 capacitor counter electrode
본 발명은 반도체 메모리장치 제조방법에 관한 것으로, 특히 64M DRAM(Dynamic Random Access Memory)급 이상의 고집적소자에 적당한 반도체 메모리장치의 커패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a capacitor of a semiconductor memory device suitable for a highly integrated device of 64M DRAM or higher.
반도체 메모리장치가 고집적화되어 감에 따라 소자에서 요구하는 만큼의 커패시턴스를 얻기 위해 3차원구조의 커패시터가 사용되고 있으며, 그 구조로는 핀(Fin)형태와 원통형 모양 그리고 MOST(Modulated Staced)구조등이 있다. 그러나 이러한 3차원 구조들은 높은 적층구조를 가져서 스텝커버리지(step coverage)가 나빠져 후공정에 좋지 않은 영향을 미치게 되어 고유전물질의 커패시터 유전체막이 개발되기 전까지는 고집적소자에서는 상기 구조들만으로는 요구되는 커패시턴스를 충족시킬 수 없었다.As semiconductor memory devices become more integrated, three-dimensional capacitors are used to obtain the capacitance required by devices. The structures include fin, cylindrical, and MOST (Modulated Staced) structures. . However, these three-dimensional structures have a high stacking structure, which results in poor step coverage, which adversely affects post-processing. Thus, until the capacitor dielectric layer of the high dielectric material is developed, the capacitance required by the structures alone is high. Could not meet.
스토리지노드를 이중으로 쌓아올린 새로운 스택구조 형태의 커패시터를 사용하는 종래의 스택 커패시터 제조방법을 제1도를 참조하여 설명하면 다음과 같다.Referring to FIG. 1, a conventional stack capacitor manufacturing method using a new stack structured capacitor in which storage nodes are stacked in duplicate is described as follows.
먼저, 제1도 (a)에 도시된 바와 같이 필드산화막(1)에 의해 활성영역과 소자분리영역으로 구분되며, 게이트절연막(2), 게이트전극(3), 게이트측벽산화막(4) 및 소오스영역과 드레인영역(5)이 형성된 반도체기판(1) 전면에 HTO(High Temperature Oxide)(6)를 증착하고 이위에 폴리실리콘층(7)을 형성한다.First, as shown in FIG. 1A, the field oxide film 1 is divided into an active region and a device isolation region, and the gate insulating film 2, the gate electrode 3, the gate side wall oxide film 4, and the source are separated. A high temperature oxide (HTO) 6 is deposited on the entire surface of the semiconductor substrate 1 on which the region and the drain region 5 are formed, and a polysilicon layer 7 is formed thereon.
이어서 제1도 (b)에 도시된 바와 같이 상기 폴리실리콘층(7) 및 HTO(6)를 선택적으로 식각하여 매몰콘택을 형성한 후, 매몰콘택내를 포함한 상기 폴리실리콘층(7)상에 노드형성용 폴리실리콘층(8)을 형성한 다음 이온주입을 행한다.Subsequently, as shown in FIG. 1 (b), the polysilicon layer 7 and the HTO 6 are selectively etched to form a buried contact, and then on the polysilicon layer 7 including the buried contact. After forming the node-forming polysilicon layer 8, ion implantation is performed.
다음에 제1도 (c)에 도시된 바와 같이 상기 폴리실리콘층들(8, 7)을 소정패턴으로 패터닝하여 하부전극을 형성한 후, 제1도 (d)에 도시된 바와 같이 상기 형성된 하부전극 전표면에 고유전물질로서, ONO(Oxide-Nitride-Oxide), NO(Nirtide-Oxide), Ta2O5등을 증착하여 커패시터 유전체막(9)을 형성하고, 그 전면에 폴리실리콘을 증착하고 패터닝하여 대향적극(10)을 형성한다.Next, as shown in FIG. 1C, the polysilicon layers 8 and 7 are patterned in a predetermined pattern to form a lower electrode, and as shown in FIG. As a high dielectric material on the entire surface of the electrode, a capacitor dielectric film 9 is formed by depositing Oxide-Nitride-Oxide (NOO), Nitride-Oxide (NO), Ta 2 O 5, etc., and polysilicon is deposited on the entire surface thereof. And patterning to form the counter positive electrode 10.
상기와 같은 이중 노드를 갖는 커패시터의 경우에는 적층된 폴리실리콘층의 높이에 따라 커패시터의 면적이 증가되므로 그 증가폭이 적어 고집적화된 소자의 커패시턴스를 만족시킬 수 없다.In the case of the capacitor having the double node as described above, the area of the capacitor increases according to the height of the stacked polysilicon layer, so that the increase is small, and thus the capacitance of the highly integrated device cannot be satisfied.
본 발명은 상술한 문제를 해결하기 위한 것으로, 대용량의 커패시턴스를 갖는 커패시터의 제조방법을 제공하는 것을 그 목적으로 한다.The present invention has been made to solve the above-described problem, and an object thereof is to provide a method of manufacturing a capacitor having a large capacitance.
상기 목적을 달성하기 위한 본 발명의 반도체 메모리장치 제조방법은 반도체기판 소정부분에 게이트전극, 소오스 및 드레인영역을 각각 형성하여 트랜지스터를 형성하는 공정, 반도체기판 전면에 절연막과 식각저지막을 차례로 형성하는 공정, 상기 식각저지막상에 TEOS-O3막을 증착하는 공정, 상기 TEOS-O3막과 식각저지막 및 절연막을 선택적으로 식각하여 상기 트랜지스터의 소오스 또는 드레인영역을 노출시키는 매몰콘택을 형성하는 공정, 희석된 HF용액을 이용하여 상기 TEOS-O3막 표면을 세정하여 TEOS-O3막 표면에는 미세한 요철이 형성되도록 하는 공정, 상기 매몰콘택내를 포함한 TEOS-O3막상부에 제1도전층을 형성하는 공정, 상기 제1도전층과 TEOS-O3막 및 식각저기막을 커패시터 하부전극 패턴으로 패터닝하는 공정, 상기 TEOS-O3막과 식각저지막을 차례로 제거하여 커패시터 하부전극을 형성하는 공정, 상기 하부전극 전표면에 커패시터 유전체막을 형성하는 공정, 상기 커패시터 유전체막 전면에 커패시터 대향전극을 형성하는 공정으로 이루어진다.The semiconductor memory device manufacturing method of the present invention for achieving the above object is a step of forming a transistor by forming a gate electrode, a source and a drain region on a predetermined portion of the semiconductor substrate, a step of sequentially forming an insulating film and an etch stop layer on the entire surface of the semiconductor substrate , a step of the etch barrier film selectively etching step, the TEOS-O 3 film and the etch barrier layer and the insulating film deposited film TEOS-O 3 to form a buried contact to expose the source or drain region of the transistor, diluted the formation of the first conductive layer is disposed on parts TEOS-O 3 by using the HF solution cleaning the TEOS-O 3 film surface, including the step, the buried contact in such that a fine unevenness formed in the surface of TEOS-O 3 film that step, the first conductive layer and a TEOS-O 3 film and the etching process and there to stop, the TEOS-O 3 film and etching to pattern the capacitor lower electrode pattern Jersey In order to remove the process comprises a step of forming a capacitor counter electrode on the entire surface of the capacitor dielectric film to be formed in the process, the entire surface of the lower electrode to form a capacitor lower electrode dielectric film capacitor.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
본 발명은 생산적용 가능성이 높으면서도 공정단축의 잇점이 있는 피복성 및 평탄성이 우수한 TEOS-O3막과 세정공정을 이용하여 대용량의 커패시턴스를 갖는 커패시터를 제조한다.The present invention manufactures a capacitor having a large capacitance by using a TEOS-O 3 membrane and a cleaning process which have high coating applicability and excellent coating properties and flatness with the possibility of shorten the production.
제2도를 참조하여 본 발명의 반도체 메모리장치 제조방법을 설명하면 다음과 같다.Referring to FIG. 2, a method of manufacturing a semiconductor memory device of the present invention will be described below.
먼저, 제2도 (a)에 도시된 바와 같이 필드산화막(1)에 의해 활성영역과 소자분리영역으로 구분되며, 게이트절연막(2), 게이트전극(3) 및 소오스영역과 드레인영역(5)이 형성된 반도체기판(1) 전면에 절연막으로서, 예컨대 산화막(11)을 형성하고 이위에 식각저지막으로서, 예컨대 질화막(12)을 형성한다.First, as shown in FIG. 2A, the active layer and the isolation region are divided by the field oxide film 1, and the gate insulating film 2, the gate electrode 3, the source region and the drain region 5 are separated. An oxide film 11 is formed on the entire surface of the formed semiconductor substrate 1 as an insulating film, for example, and an nitride film 12 is formed thereon as an etch stop film.
이어서 제2도 (b)에 도시된 바와 같이 상기 질화막(12)상에 TEOS-O3막을 증착한 후, 제2도 (c)에 도시된 바와 같이 상기 TEOS-O3막(13)과 질화막(12) 및 산화막(11)을 선택적으로 식각하여 소오스영역(5)과 후에 형성될 커패시터 하부전극이 접속될 매몰콘택을 형성한다.Subsequently, a TEOS-O 3 film is deposited on the nitride film 12 as shown in FIG. 2B, and then the TEOS-O 3 film 13 and the nitride film as shown in FIG. 2C. 12 and the oxide film 11 are selectively etched to form a buried contact to which the source region 5 and the capacitor lower electrode to be formed later are connected.
다음에 제2도 (d)에 도시된 바와 같이 HF : 순수(DI water)가 1 : 99로 희석된 HF용액을 이용하여 세정공정을 행한다. 이때 세정공정에 의해 TEOS-O3막(13) 표면에는 미세한 요철이 형성되게 된다.Next, as shown in FIG. 2 (d), a washing process is performed using a HF solution diluted with HF: DI water 1:99. At this time, fine irregularities are formed on the surface of the TEOS-O 3 film 13 by the cleaning process.
이어서 제2도 (e)에 도시된 바와 같이 상기 메몰콘택내를 포함한 TEOS-O3막(13)상부에 제1도전층으로서, 예컨대 폴리실리콘(14)을 증착하고, 이어서 제2도 (f)에 도시된 바와 같이 상기 폴리실리콘층(10)과 TEOS-O3막(13) 및 질화막(12)을 커패시터 하부전극패턴으로 패터닝한다.Subsequently, as shown in FIG. 2 (e), a polysilicon 14 is deposited as a first conductive layer on top of the TEOS-O 3 film 13 including the inside of the buried contact, followed by FIG. The polysilicon layer 10, the TEOS-O 3 film 13, and the nitride film 12 are patterned with a capacitor lower electrode pattern, as shown in FIG.
다음에 제2도 (g)에 도시된 바와 같이 HF : 순수가 1 : 99로 희석된 HF용액을 이용한 습식식각에 의해 상기 TEOS-O3막을 제거한 후, 이어서 질화막을 제거함으로써 소정부분에 요출부가 형성된 커패시터 하부전극(14)을 형성한다. 상기 TEOS-O3막의 제거를 위한 습식식각공정시 식각시간을 조절함으로써 식각량을 조절한다.Next, as shown in FIG. 2 (g), the TEOS-O 3 membrane was removed by wet etching using an HF solution diluted with HF: pure water 1:99, followed by removal of the nitride film, thereby providing a recessed portion at a predetermined portion. The formed capacitor lower electrode 14 is formed. The amount of etching is controlled by adjusting the etching time during the wet etching process for removing the TEOS-O 3 film.
이어서 제2도 (h)에 도시된 바와 같이 상기 하부전극(14) 전표면에 커패시터 유전체막(15)을 형성하고 기판 전면에 제2도전층으로서, 예컨대 폴리실리콘을 증착하고 이를 소정패턴으로 패터닝하여 커패시터 대향전극(16)을 형성함으로써 커패시터 제조공정을 완료한다.Subsequently, as shown in FIG. 2 (h), a capacitor dielectric layer 15 is formed on the entire surface of the lower electrode 14, and polysilicon is deposited as a second conductive layer on the entire surface of the substrate, for example, and patterned into a predetermined pattern. By forming the capacitor counter electrode 16 to complete the capacitor manufacturing process.
이상과 같이 본 발명에 의하면, 커패시터 하부전극이 요철부를 가짐으로써 커패시터면적이 증대되어 커패시턴스가 증가되는 효과를 얻을 수 있으며, 브레이크다운 전압 및 누설전류 등의 전기적 특성이 향상된 반도체 메모리소자의 실현을 도모할 수 있다.As described above, according to the present invention, since the capacitor lower electrode has an uneven portion, the capacitor area is increased, thereby increasing the capacitance, and the semiconductor memory device having improved electrical characteristics such as breakdown voltage and leakage current can be realized. can do.
Claims (1)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940016636A KR0151377B1 (en) | 1994-07-11 | 1994-07-11 | Semiconductor memory device and its manufacture |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940016636A KR0151377B1 (en) | 1994-07-11 | 1994-07-11 | Semiconductor memory device and its manufacture |
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| KR960006023A KR960006023A (en) | 1996-02-23 |
| KR0151377B1 true KR0151377B1 (en) | 1998-10-01 |
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| KR1019940016636A KR0151377B1 (en) | 1994-07-11 | 1994-07-11 | Semiconductor memory device and its manufacture |
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