CN113517256B - Isolation pattern for forming bit line contact of DRAM and preparation method - Google Patents
Isolation pattern for forming bit line contact of DRAM and preparation method Download PDFInfo
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- CN113517256B CN113517256B CN202010275574.5A CN202010275574A CN113517256B CN 113517256 B CN113517256 B CN 113517256B CN 202010275574 A CN202010275574 A CN 202010275574A CN 113517256 B CN113517256 B CN 113517256B
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- 238000002955 isolation Methods 0.000 title claims abstract description 94
- 238000002360 preparation method Methods 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 239000004065 semiconductor Substances 0.000 claims abstract description 33
- 125000006850 spacer group Chemical group 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 140
- 238000005530 etching Methods 0.000 claims description 33
- 150000004767 nitrides Chemical class 0.000 claims description 17
- 239000011241 protective layer Substances 0.000 claims description 7
- 238000000206 photolithography Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 238000003475 lamination Methods 0.000 claims 1
- 238000000059 patterning Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention relates to an isolation pattern for forming a bit line contact of a DRAM and a method of manufacturing the same, comprising: a semiconductor substrate; a plurality of spacers located over the semiconductor substrate; each isolation part is not connected; the pattern of each isolation part is 8-shaped formed by two overlapped circles. The 8-shaped isolation part can increase the critical dimension of the contact in the bit line direction, so that the resistance of the contact part can be improved and the performance can be improved under the condition of not changing the process margin.
Description
Technical Field
The present application relates to semiconductor memory devices, and more particularly, to an isolation pattern for forming bit line contacts of a DRAM and a method of manufacturing the same.
Background
In the case of continuous shrinking of the dynamic random access memory (Dynamic Random Access Memory, DRAM), in order to secure a sufficient process margin, it is necessary to secure a distance between the isolation portion (non-contact region) and the active region, and a distance between the contact region and the active region, which are Trade-off relationships, which cannot be compromised separately. However, increasing the distance between the isolation and the active region increases the resistance of the isolation, affecting performance.
Disclosure of Invention
In view of the above-mentioned problems, the present application provides an isolation pattern for forming a bit line contact of a DRAM, comprising: a semiconductor substrate; a plurality of spacers located over the semiconductor substrate; each isolation part is not connected; the pattern of each isolation part is 8-shaped formed by two overlapped circles.
In view of the above problems, the present application further provides a method for preparing an isolation pattern for a bit line contact of a DRAM, including: providing a semiconductor substrate; forming a first isolation layer on the semiconductor substrate; and etching the first isolation layer and the semiconductor substrate, so that the first isolation layer forms a plurality of isolation parts, and the pattern of each isolation part is 8-shaped formed by two overlapped circles.
The application has the advantages that: the 8-shaped isolation part can increase the critical dimension of the contact in the bit line direction, so that the resistance of the contact part can be improved and the performance can be improved under the condition of not changing the process margin.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 shows a schematic diagram of a pattern of spacers;
fig. 2 shows a schematic structural diagram of a cross section of an isolation pattern;
FIGS. 3A-3C are schematic diagrams illustrating embodiments of forming a first dot type mask pattern on a semiconductor substrate;
fig. 4 illustrates a schematic view of sequentially forming a first dot type mask pattern, a second dot type mask pattern, a third dot type mask pattern, and a fourth dot type mask pattern on a semiconductor substrate;
FIGS. 5A-5B are schematic diagrams showing cyclic formation of a dot mask pattern on a semiconductor substrate;
FIG. 6 shows a schematic diagram of forming a patterned hole of a spacer in a second spin-on hard mask layer;
FIGS. 7A-7D show schematic diagrams of spacers resulting in an 8-shaped pattern;
FIG. 8 shows a flowchart of a method of fabricating an isolation pattern for forming a bit line contact of a DRAM;
fig. 9 shows a positional relationship diagram of the isolation portion and the active region.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The patterns of the various regions, layers and their relative sizes, positional relationships shown in the figures are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different patterns, sizes, relative positions as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.
FIG. 1 illustrates an embodiment of an isolation portion in a semiconductor structure; fig. 2 shows a cross-sectional view of the spacer in the semiconductor structure along line BB' in fig. 1; referring to fig. 1 and 2, the pattern (isolation pattern) of each isolation portion 110 is 8-shaped composed of two partially overlapped circles, and a long center line BB' of the isolation portion 110 is perpendicular to the bit line BL. Line AA' is the width of an orthographic projection of one circle in spacer 110. The orthographic projections of one isolation portion 110 cover different ends of two adjacent active regions AR, respectively, and a space for forming a bit line contact portion is left between the adjacent isolation portions 110, and at the same time, the orthographic projections of the middle portion of the isolation portion 110 also cover a section of the bit line BL between the covered two adjacent active regions AR. As shown in fig. 1, one active region AR is divided into 2 ends and a middle section, which are 3 total sections, by being covered with two adjacent word lines WL. The length of line BB' covers the different ends of the adjacent two active areas AR, as well as a section of the bit line BL.
As shown in fig. 2, each of the plurality of spacers 110, which are not connected to each other, is a thin layer on the semiconductor substrate 100. The semiconductor substrate 100 includes: a substrate 101, an oxide layer 102 on the substrate 101, and a plurality of active regions AR connected to the oxide layer 102 and perpendicular to the oxide layer 102. Each active region AR is isolated by an isolation region 103. Within the substrate 101 is an isolation region 103 and on the oxide layer 102 is an isolation portion 110. The isolation portion 110 covers two adjacent active regions isolated by the isolation region 103. Each isolation portion 110 is parallel to the bottom surface of the substrate 101, and the heights between each isolation portion 110 and the bottom surface of the substrate 101 are equal, and the planar layer where each isolation portion 110 is located is a contact layer.
In one embodiment, the substance forming the 110 pattern of spacers includes: and (3) nitride.
Fig. 8 illustrates a method of fabricating a semiconductor structure, as shown in fig. 8, an example method begins with providing a semiconductor substrate 100, as shown in operation 801; continuing with operation 802, a first isolation layer 11 is formed on the semiconductor substrate 100. Continuing with operation 803, the first isolation layer 11 and the semiconductor substrate 100 are etched, so that the first isolation layer forms a plurality of isolation portions, each of which has a pattern of 8-shape formed by two partially overlapping circles.
As shown in fig. 3A, a first isolation layer 11, a first spin-on hard mask layer 12, a first protection layer 13, a second spin-on hard mask layer 14, a second protection layer 15, a mask pattern transfer layer 16, a hard mask layer 17, and a nitride layer 18 are sequentially formed on a semiconductor substrate 100.
For operation 803, first, the etching pattern transfer stack 200 and the mask pattern transfer layer 16 are formed on the first isolation layer 11. Next, the pattern of the spacers is printed in the mask pattern transfer layer 16 by photolithography, that is, by forming the hard mask layer 17 and the nitride layer 18 on the mask pattern transfer layer 16 first, then forming a circular (dot) mask pattern on the nitride layer 18, etching the hard mask layer 17 and the nitride layer 18 with the circular mask pattern, thereby obtaining a circular trench pattern 151 on the mask pattern transfer layer 16, and repeating the forming of the circular mask pattern and the etching step, thereby obtaining an 8-shaped trench pattern on the mask pattern transfer layer 16.
Wherein etching the pattern transfer stack 200 comprises forming from below: a first spin-on hard mask layer 12, a first protective layer 13, a second spin-on hard mask layer 14, and a second protective layer 15.
Fig. 3A to 3C illustrate that the pattern of the spacer 110 is printed in the mask pattern transfer layer 16, wherein the pattern of the spacer 110 is formed by sequentially forming a first Dot Type (Dot Type) mask pattern 151, a second Dot Type mask pattern 152, a third Dot Type mask pattern 153, and a fourth Dot Type mask pattern 154 in the mask pattern transfer layer 16. First, a photoresist 19 is coated on the nitride layer 18, and then photo-patterning and mask etching are performed to form a first dot type mask pattern 151, and then a mask layer 178 is deposited, and the above steps are repeated until a fourth dot type mask pattern 154 is formed. As shown in fig. 3B, a photoresist 19 is coated on the nitride layer 18, leaving first dot pattern holes 181 for photo-patterning and mask etching. As shown in fig. 3C, oxide layer patterning is completed in the mask pattern transfer layer 16, forming a first dot type mask pattern 151, depositing a mask layer 178 in the mask pattern transfer layer 16, and performing this step in a loop until a fourth dot type mask pattern 154 is formed.
Fig. 4 illustrates that a first dot type mask pattern 151, a second dot type mask pattern 152, a third dot type mask pattern 153, and a fourth dot type mask pattern 154 are sequentially formed on the semiconductor substrate 100. Each time the photoresist 19 is coated, a corresponding second or third or fourth dot type mask pattern hole 182 or 183 or 184 is left. After forming the first, second, and third dot type mask patterns 151, 152, and 153, it is also necessary to deposit a mask layer 178 on the mask pattern transfer layer 16.
In one embodiment, the deposited mask layer 178 may be the hard mask layer 17 and the nitride layer 18.
Fig. 5A and 5B illustrate cyclically forming a dot mask pattern on the semiconductor substrate 100. After the mask layer is deposited on the mask pattern transfer layer 16 as shown in fig. 5A, a photoresist 19 is coated on the nitride layer 18, leaving corresponding second dot type mask pattern holes 182 as shown in fig. 4, and photo-patterning and mask etching are performed, and oxide layer patterning is completed on the first oxide layer 16 as shown in fig. 5B, forming a second dot type mask pattern 152. A mask layer 178 is again deposited over the mask pattern transfer layer 16. A photoresist 19 is coated on the nitride layer 18, a corresponding third dot type mask pattern hole 183 is left, photo-patterning and mask etching are performed, and oxide layer patterning is completed on the first oxide layer 16, so that a third dot type mask pattern 153 is formed. A final mask layer 178 is deposited over the mask pattern transfer layer 16, photoresist 19 is coated over the nitride layer 18, corresponding fourth-dot mask pattern holes 184 are left, photo-patterning and mask etching are performed, and oxide layer patterning is completed over the first oxide layer 16, as shown in fig. 4, to form fourth-dot mask patterns 154.
In operation 803, after the fourth dot type mask pattern 154 is formed, the pattern of the spacer is printed in the mask pattern transfer layer 16, the pattern in the mask pattern transfer layer 16 is transferred to form a main etch pattern mask using the etch pattern transfer stack 200, and the first spacer 11 and the substrate 100 are etched using the main etch pattern mask. By etching the second protective layer 15 and the second spin-on hard mask layer 14 with the pattern (pattern) of the mask pattern transfer layer 16 as a mask, a second spin-on hard mask layer pattern (pattern hole) 141 of the isolation portion is formed in the second spin-on hard mask layer 14, that is, as shown in fig. 6, the pattern hole 141 of the isolation portion is formed in the second spin-on hard mask layer 14. Forming a dielectric layer 142 on the second spin-on hard mask layer pattern 141; the second spin-on hard mask layer pattern 141 is removed, thereby transferring the pattern of the spacer to the dielectric layer 142 and forming a main etch pattern mask.
For operation 803, after forming the main etch pattern mask, etching the first isolation layer 11 and the substrate 100 using the main etch pattern mask, comprising: etching the first isolation layer 11 and the substrate 100 using the main etching pattern mask, and forming a hard mask 121 with an arc rounded top on the first spin-on hard mask layer 12; the hard mask 121 is removed. The second spin-on hard mask layer 14 is removed by filling the dielectric layer 142 in the pattern holes 141 of the isolation portion 110, and main etching is performed to remove the first spin-on hard mask layer 12, thereby obtaining a plurality of 8-shaped isolation portions 110 on the semiconductor substrate. Fig. 7A to 7D show a pattern in which a plurality of 8-shaped spacers 110 are formed on the first spacer 11. That is, the oxide 142 is deposited in the pattern holes 141 of the spacers, and etching is performed using an Etch Back (Etch Back) process, and the second protective layer 15 and the mask pattern transfer layer 16 on the second spin-on hard mask layer 14 are removed, resulting in the second spin-on hard mask layer 14 in which the pattern holes 141 of the spacers are filled with the dielectric layer 142, as shown in fig. 7A. As shown in fig. 7B, the mask 143 in the second spin-on hard mask layer 14 is removed, leaving the filled dielectric layer 142. As shown in fig. 7C, main etching is performed to form a hard mask 121 with an arc-shaped rounded top on the second spin-on hard mask layer 14, and to etch grooves 104 on the first spin-on hard mask layer 12, the first isolation layer 11, and the semiconductor substrate 100. As shown in fig. 7D, the hard mask 121 in the first spin-on hard mask layer 12 is removed, and a plurality of 8-shaped spacers 110 are formed on the semiconductor substrate, and spaces for forming bit line contacts are left between adjacent spacers 110. Wherein the dielectric layer 142 may be an oxide.
In one embodiment, oxide 142 is deposited in the patterned holes 141 of the spacers using atomic layer deposition (Atomic Layer Deposition, ALD).
After the isolation pattern 110 is obtained, a sidewall (Spacer) is formed on the sidewall of the isolation pattern 110. In one embodiment, the sidewall-forming material comprises nitride or silicon.
Fig. 9 shows a positional relationship diagram of the isolation portion and the active region. The planar layer where the isolation portion 110 is located is a contact layer, and the non-isolation portion regions in the contact layer are all contact regions. Where the distance D1 is a distance between the edge of the isolation portion 110 and the active region AR covered thereby, i.e., a distance between the contact region and the active region AR requiring separation. D2 is a separation distance between the edge of the isolation portion 110 and the active region AR not covered by it, i.e., a distance to be included between the contact region active regions AR.
The 8-shaped isolation part 110 in the embodiment of the application can increase the critical dimension of the contact in the direction of the bit line BL, so that the resistance of the contact part can be improved and the performance can be improved under the condition of not changing the process margin.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired pattern may be formed by various techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.
Claims (14)
1. An isolation pattern for forming a bit line contact of a DRAM, comprising:
a semiconductor substrate;
a plurality of spacers located over the semiconductor substrate;
each isolation part is not connected;
the pattern of each isolation part is 8-shaped formed by two overlapped circles;
the isolation part covers different ends of two adjacent active areas;
a space for forming a bit line contact part is reserved between the adjacent isolation parts;
the edge of the isolation part is spaced from the active region covered by the isolation part; the edge of the spacer is spaced from the active region not covered by it.
2. The isolation pattern of claim 1, wherein said semiconductor substrate further comprises an oxide layer and a plurality of active regions isolated by isolation regions.
3. The isolation pattern of claim 1, wherein the isolation portion is over an oxide layer of the semiconductor substrate.
4. The isolation pattern of claim 1, wherein a long center line of the isolation portion is perpendicular to the bit line.
5. The isolation pattern of claim 1, wherein an orthographic projection of a middle portion of the isolation portion covers a section of one bit line.
6. The isolation pattern of claim 1, wherein the substance forming the isolation portion further comprises: and (3) nitride.
7. A method for fabricating an isolation pattern for a bit line contact of a DRAM, comprising:
providing a semiconductor substrate;
forming a first isolation layer on the semiconductor substrate;
etching the first isolation layer and the semiconductor substrate, so that the first isolation layer forms a plurality of isolation parts, and the pattern of each isolation part is 8-shaped formed by two overlapped circles;
the isolation part covers different ends of two adjacent active areas;
a space for forming a bit line contact part is reserved between the adjacent isolation parts;
the edge of the isolation part is spaced from the active region covered by the isolation part; the edge of the spacer is spaced from the active region not covered by it.
8. The method of manufacturing of claim 7, wherein etching the first isolation layer and the semiconductor substrate comprises:
forming an etching pattern transfer stack and a mask pattern transfer layer on the first isolation layer;
printing the pattern of the spacer in the mask pattern transfer layer using photolithography;
transferring the pattern in the mask pattern transfer layer by using the etching pattern transfer lamination to form a main etching pattern mask;
and etching the first isolation layer and the substrate by using the main etching pattern mask.
9. The method of manufacturing according to claim 8, wherein the printing the pattern of the spacer in the mask pattern transfer layer using photolithography includes:
forming a hard mask layer and a nitride layer on the mask pattern transfer layer;
forming a circular mask pattern on the nitride layer;
etching the hard mask layer and the nitride layer with the circular mask pattern to obtain a circular trench pattern on the mask pattern transfer layer;
and repeating the steps of forming a circular mask pattern and etching to obtain an 8-shaped groove pattern on the mask pattern transfer layer.
10. The method of manufacturing of claim 9, wherein the etching pattern transfer stack comprises the following from top to bottom: the first spin-on hard mask layer, the first protective layer, the second spin-on hard mask layer and the second protective layer.
11. The method of manufacturing according to claim 10, wherein transferring the pattern in the mask pattern transfer layer to form a main etch pattern mask using the etch pattern transfer stack, comprises:
etching the second protective layer and the second spin-on hard mask layer by taking the pattern in the mask pattern transfer layer as a mask to form a second spin-on hard mask layer pattern;
forming a dielectric layer on the second spin-on hard mask layer pattern;
and removing the second spin-on hard mask layer pattern so as to transfer the pattern of the isolation part to the dielectric layer, and forming a main etching pattern mask.
12. The method of manufacturing of claim 8, wherein said etching said first isolation layer and substrate using said main etch pattern mask comprises:
etching the first isolation layer and the substrate by using the main etching pattern mask, and forming a hard mask with an arc-shaped round corner at the top on the first spin-on hard mask layer;
the hard mask is removed.
13. The method of preparing as claimed in claim 9, further comprising the steps of: and forming a side wall on the side wall of the isolation part after the isolation part is obtained.
14. The method of manufacturing of claim 13, wherein the sidewall forming substance further comprises: nitride or silicon.
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| CN202010275574.5A CN113517256B (en) | 2020-04-09 | 2020-04-09 | Isolation pattern for forming bit line contact of DRAM and preparation method |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102117772A (en) * | 2009-12-30 | 2011-07-06 | 海力士半导体有限公司 | Semiconductor device with vertical cells and fabrication method thereof |
| CN104900584A (en) * | 2014-03-05 | 2015-09-09 | 爱思开海力士有限公司 | Semiconductor device with line-type air gaps and method for fabricating the same |
| US10050041B1 (en) * | 2015-01-05 | 2018-08-14 | Samsung Electronics Co., Ltd. | Semiconductor device and method of manufacturing the same |
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| KR20120086637A (en) * | 2011-01-26 | 2012-08-03 | 에스케이하이닉스 주식회사 | Semiconductor device and method for manufacturing the same |
| KR102509322B1 (en) * | 2017-09-29 | 2023-03-14 | 에스케이하이닉스 주식회사 | Semiconductor device with air gap and method for fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102117772A (en) * | 2009-12-30 | 2011-07-06 | 海力士半导体有限公司 | Semiconductor device with vertical cells and fabrication method thereof |
| CN104900584A (en) * | 2014-03-05 | 2015-09-09 | 爱思开海力士有限公司 | Semiconductor device with line-type air gaps and method for fabricating the same |
| US10050041B1 (en) * | 2015-01-05 | 2018-08-14 | Samsung Electronics Co., Ltd. | Semiconductor device and method of manufacturing the same |
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