CN113517256A - Isolation pattern for forming bit line contact of DRAM and method of fabricating the same - Google Patents

Isolation pattern for forming bit line contact of DRAM and method of fabricating the same Download PDF

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Publication number
CN113517256A
CN113517256A CN202010275574.5A CN202010275574A CN113517256A CN 113517256 A CN113517256 A CN 113517256A CN 202010275574 A CN202010275574 A CN 202010275574A CN 113517256 A CN113517256 A CN 113517256A
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layer
pattern
isolation
mask
etching
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CN113517256B (en
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叶甜春
安佑松
杨涛
李俊峰
王文武
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention relates to an isolation pattern for forming a bit line contact of a DRAM and a preparation method thereof, comprising the following steps: a semiconductor substrate; a plurality of isolation portions over the semiconductor substrate; each isolating part is not connected with each other; the pattern of each isolation part is 8-shaped consisting of two partially overlapped circles. The 8-shaped isolation part can increase the critical dimension of the contact in the bit line direction, thereby improving the resistance of the contact part and improving the performance under the condition of not changing the process margin.

Description

Isolation pattern for forming bit line contact of DRAM and method of fabricating the same
Technical Field
The present invention relates to a semiconductor memory device, and more particularly, to an isolation pattern and a fabrication method for forming a bit line contact of a DRAM.
Background
In the case of Dynamic Random Access Memory (DRAM) being continuously scaled down, in order to ensure a sufficient process margin, it is necessary to ensure a distance between an isolation portion (non-contact region) and an active region and a distance between a contact region and the active region, which are in a Trade-off relationship, and one of them cannot be separately compromised. However, increasing the distance between the isolation and the active region increases the resistance of the isolation, affecting performance.
Disclosure of Invention
In view of the above-mentioned existing problems, the present application provides an isolation pattern for forming a bit line contact of a DRAM, comprising: a semiconductor substrate; a plurality of isolation portions over the semiconductor substrate; each isolating part is not connected with each other; the pattern of each isolation part is 8-shaped consisting of two partially overlapped circles.
In view of the above problems, the present application also provides a method for preparing an isolation pattern of a bit line contact of a DRAM, comprising: providing a semiconductor substrate; forming a first isolation layer on the semiconductor substrate; and etching the first isolation layer and the semiconductor substrate, so that the first isolation layer forms a plurality of isolation parts, and the pattern of each isolation part is in a shape of 8 consisting of two partially overlapped circles.
The application has the advantages that: the 8-shaped isolation part can increase the critical dimension of the contact in the bit line direction, thereby improving the resistance of the contact part and improving the performance under the condition of not changing the process margin.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 shows a schematic view of a pattern of spacers;
fig. 2 shows a schematic structural view of a cross section of an isolation pattern;
FIGS. 3A-3C are schematic diagrams illustrating embodiments of forming a first dot type mask pattern on a semiconductor substrate;
fig. 4 is a schematic view showing the formation of a first dot type mask pattern, a second dot type mask pattern, a third dot type mask pattern and a fourth dot type mask pattern in this order on a semiconductor substrate;
FIGS. 5A-5B are schematic diagrams illustrating the cyclical formation of dot mask patterns on a semiconductor substrate;
FIG. 6 shows a schematic view of a patterning hole forming an isolation portion in a second spin-on hard mask layer;
FIGS. 7A-D show schematic views of the spacer resulting in a 8-word pattern;
FIG. 8 shows a flow chart of a method of fabricating an isolation pattern for forming bitline contacts of a DRAM;
fig. 9 is a diagram showing a positional relationship between the isolation portion and the active region.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The patterns of the various regions, layers and the relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions/layers with different patterns, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
FIG. 1 illustrates an embodiment of an isolation in a semiconductor structure; FIG. 2 illustrates a cross-sectional view of an isolation portion in the semiconductor structure taken along line BB' in FIG. 1; referring to fig. 1 and 2, the pattern (isolation pattern) of each isolation portion 110 is a figure 8 consisting of two partially overlapped circles, and the long center line BB' of the isolation portion 110 is perpendicular to the bit line BL. Line AA' is the width of the orthographic projection of one circle in spacer 110. The orthographic projection of one isolation portion 110 covers different ends of two adjacent active regions AR respectively, a space for forming a bit line contact portion is left between the adjacent isolation portions 110, and meanwhile, the orthographic projection of the middle portion of the isolation portion 110 also covers a section of the bit line BL between the two adjacent covered active regions AR. As shown in fig. 1, one active region AR is covered by two adjacent word lines WL and divided into 2 ends and a middle section for a total of 3 sections. The length of the line BB' covers the different ends of the adjacent two active areas AR, as well as a section of the bit line BL.
As shown in fig. 2, each of the plurality of spacers 110, which are not connected to each other, is a thin layer on the semiconductor substrate 100. The semiconductor substrate 100 includes: a substrate 101, an oxide layer 102 on the substrate 101, and a plurality of active regions AR connected to the oxide layer 102 and perpendicular to the oxide layer 102. The active regions AR are isolated by isolation regions 103. Isolation region 103 is within substrate 101 and isolation 110 is on oxide layer 102. The isolation portion 110 covers two adjacent active regions isolated by the isolation region 103. Each isolation portion 110 is parallel to the bottom surface of the substrate 101, the heights between each isolation portion 110 and the bottom surface of the substrate 101 are all equal, and the planar layer where each isolation portion 110 is located is a contact layer.
In one embodiment, the substance forming the 110 pattern of spacers includes: and (3) nitride.
Fig. 8 illustrates a method of fabricating a semiconductor structure, as shown in fig. 8, the exemplary method begins with operation 801 of providing a semiconductor substrate 100; continuing with operation 802, a first isolation layer 11 is formed on the semiconductor substrate 100. Continuing with operation 803, the first isolation layer 11 and the semiconductor substrate 100 are etched such that the first isolation layer forms a plurality of isolation portions, each having a pattern in the shape of a figure 8 consisting of two partially overlapping circles.
As shown in fig. 3A, a first isolation layer 11, a first spin-on hard mask layer 12, a first protective layer 13, a second spin-on hard mask layer 14, a second protective layer 15, a mask pattern transfer layer 16, a hard mask layer 17, and a nitride layer 18 are sequentially formed on a semiconductor substrate 100.
For operation 803, first, the etching pattern transfer stack 200 and the mask pattern transfer layer 16 are formed on the first isolation layer 11. Next, the pattern of the isolation portion is printed in the mask pattern transfer layer 16 by photolithography, that is, by forming the hard mask layer 17 and the nitride layer 18 on the mask pattern transfer layer 16 first, then forming a circular (dot type) mask pattern on the nitride layer 18, etching the hard mask layer 17 and the nitride layer 18 with the circular mask pattern to obtain a circular trench pattern 151 on the mask pattern transfer layer 16, and repeating the formation of the circular mask pattern and the etching step to obtain an 8-letter type trench pattern on the mask pattern transfer layer 16.
Wherein etching the pattern transfer stack 200 comprises forming from: a first spin-on hard mask layer 12, a first protective layer 13, a second spin-on hard mask layer 14, and a second protective layer 15.
Fig. 3A to 3C illustrate printing of a pattern of the spacer portion in the mask pattern transfer layer 16, wherein the pattern of the spacer portion 110 is formed by sequentially forming a first Dot Type (Dot Type) mask pattern 151, a second Dot Type mask pattern 152, a third Dot Type mask pattern 153, and a fourth Dot Type mask pattern 154 in the mask pattern transfer layer 16. First, a photoresist 19 is coated on the nitride layer 18, and then photo-patterning and mask etching are performed to form a first dot type mask pattern 151, and then a mask layer 178 is deposited, and the above steps are repeated until a fourth dot type mask pattern 154 is formed. As shown in fig. 3B, a photoresist 19 is coated on the nitride layer 18, leaving a first dot mask pattern hole 181, and photo patterning and mask etching are performed. As shown in fig. 3C, the oxide layer patterning is completed on the mask pattern transfer layer 16 to form the first dot type mask pattern 151, the mask layer 178 is deposited on the mask pattern transfer layer 16, and this step is repeated until the fourth dot type mask pattern 154 is formed.
Fig. 4 illustrates that a first dot type mask pattern 151, a second dot type mask pattern 152, a third dot type mask pattern 153, and a fourth dot type mask pattern 154 are sequentially formed on the semiconductor substrate 100. Each time the photoresist 19 is coated, the corresponding second dot type mask pattern hole 182 or third dot type mask pattern hole 183 or fourth dot type mask pattern hole 184 is left. After the first dot type mask patterns 151, the second dot type mask patterns 152, and the third dot type mask patterns 153 are formed, a mask layer 178 is further deposited on the mask pattern transfer layer 16.
In one embodiment, the deposited mask layer 178 may be the hard mask layer 17 and the nitride layer 18.
Fig. 5A and 5B illustrate cyclically forming dot mask patterns on the semiconductor substrate 100. As shown in fig. 5A, after the mask layer is deposited on the mask pattern transfer layer 16, a photoresist 19 is coated on the nitride layer 18, as shown in fig. 4, and a corresponding second dot type mask pattern hole 182 is left, and photo patterning and mask etching are performed, as shown in fig. 5B, to complete oxide layer patterning on the first oxide layer 16, thereby forming a second dot type mask pattern 152. The mask layer 178 is again deposited on the mask pattern transfer layer 16. The photoresist 19 is coated on the nitride layer 18, and the third dot type mask pattern hole 183 is formed, and photo patterning and mask etching are performed to complete oxide layer patterning on the first oxide layer 16, thereby forming the third dot type mask pattern 153. A final mask layer 178 is deposited on the mask pattern transfer layer 16, a photoresist 19 is coated on the nitride layer 18, a fourth-point type mask pattern hole 184 is left, photo patterning and mask etching are performed, and oxide layer patterning is completed on the first oxide layer 16, as shown in fig. 4, thereby forming a fourth-point type mask pattern 154.
For operation 803, after the fourth-point type mask pattern 154 is formed and the pattern of the spacer is printed in the mask pattern transfer layer 16, the pattern in the mask pattern transfer layer 16 is transferred to form a main etch pattern mask using the etch pattern transfer laminate 200, and the first spacer 11 and the substrate 100 are etched using the main etch pattern mask. By etching the second protective layer 15 and the second spin-on hard mask layer 14 with the pattern (pattern) of the mask pattern transfer layer 16 as a mask, a second spin-on hard mask layer pattern (pattern hole) 141 of the isolation portion is formed in the second spin-on hard mask layer 14, that is, as shown in fig. 6, the pattern hole 141 of the isolation portion is formed in the second spin-on hard mask layer 14. Forming a dielectric layer 142 on the second spin-on hard mask layer pattern 141; the second spin-on hard mask layer pattern 141 is removed, thereby transferring the pattern of the isolation portion onto the dielectric layer 142 and forming a main etch pattern mask.
For operation 803, after forming the main etch pattern mask, etching the first isolation layer 11 and the substrate 100 using the main etch pattern mask, including: etching the first isolation layer 11 and the substrate 100 by using the main etching pattern mask, and forming a hard mask 121 with an arc-shaped fillet at the top on the first spin-on hard mask layer 12; the hard mask 121 is removed. The dielectric layer 142 is filled in the pattern hole 141 of the isolation part 110, the second spin-on hard mask layer 14 is removed, main etching is performed, the first spin-on hard mask layer 12 is removed, and a plurality of isolation parts 110 with 8-shaped patterns are obtained on the semiconductor substrate. Fig. 7A to 7D show patterns in which a plurality of 8-shaped spacers 110 are formed on the first spacer 11. That is, the oxide 142 is deposited in the pattern holes 141 of the isolation portions, and etching is performed using an Etch Back (Etch Back) process to remove the second protective layer 15 and the mask pattern transfer layer 16 on the second spin-on hard mask layer 14, resulting in the second spin-on hard mask layer 14 in which the pattern holes 141 of the isolation portions are filled with the dielectric layer 142, as shown in fig. 7A. As shown in fig. 7B, the mask 143 in the second spin-on hard mask layer 14 is removed, leaving the filled dielectric layer 142. As shown in fig. 7C, a main etch is performed to form a hard mask 121 with a rounded top on the second spin-on hard mask layer 14, and a recess 104 is etched in the first spin-on hard mask layer 12, the first isolation layer 11 and the semiconductor substrate 100. As shown in fig. 7D, the hard mask 121 in the first spin-on hard mask layer 12 is removed, thereby obtaining a plurality of 8-shaped isolation portions 110 in the pattern on the semiconductor substrate, and a space for forming a bit line contact portion is left between adjacent isolation portions 110. The dielectric layer 142 may be an oxide.
In one embodiment, the oxide 142 is deposited in the pattern hole 141 of the isolation portion using Atomic Layer Deposition (ALD).
After the pattern 110 of the isolation portion is obtained, a sidewall Spacer (Spacer) is formed on the sidewall of the pattern 110 of the isolation portion. In one embodiment, the material forming the sidewall spacers comprises nitride or silicon.
Fig. 9 is a diagram showing a positional relationship between the isolation portion and the active region. The planar layer where the isolation portion 110 is located is a contact layer, and the non-isolation portion regions in the contact layer are contact regions. Where the distance D1 is the distance between the edge of the isolation 110 and the active area AR covered by it, i.e. the distance between the contact area and the active area AR that needs to be separated. D2 is the separation distance between the edge of the isolation 110 and the active area AR not covered by it, i.e. the distance that needs to be included between the contact area active areas AR.
The 8-shaped isolation part 110 in the embodiment of the present application can increase the critical dimension of the contact in the bit line BL direction, thereby improving the resistance of the contact part and improving the performance without changing the process margin.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that the desired pattern of layers, regions, etc. may be formed by various techniques. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (16)

1. An isolation pattern for forming a bitline contact for a DRAM, comprising:
a semiconductor substrate;
a plurality of isolation portions over the semiconductor substrate;
each isolating part is not connected with each other;
the pattern of each isolation part is 8-shaped consisting of two partially overlapped circles.
2. The semiconductor structure of claim 1, further comprising an oxide layer and a plurality of active regions isolated by isolation regions in the semiconductor substrate.
3. The semiconductor structure of claim 1, wherein the isolation is over an oxide layer of the semiconductor substrate.
4. The semiconductor structure of claim 1, wherein the isolation portion covers different ends of two adjacent active regions.
5. The semiconductor structure of claim 4, wherein a space for forming a bit line contact is left between adjacent ones of the spacers.
6. The semiconductor structure of claim 1, wherein a long centerline of the isolation is perpendicular to a bit line.
7. The semiconductor structure of claim 1, wherein an orthographic projection of a middle portion of the isolation portion covers a segment of one bitline.
8. The semiconductor structure of claim 1, wherein the species forming the isolation portion further comprises: and (3) nitride.
9. A method for preparing an isolation pattern of a bit line contact of a DRAM, comprising:
providing a semiconductor substrate;
forming a first isolation layer on the semiconductor substrate;
and etching the first isolation layer and the semiconductor substrate, so that the first isolation layer forms a plurality of isolation parts, and the pattern of each isolation part is in a shape of 8 consisting of two partially overlapped circles.
10. The method of claim 9, wherein the etching the first isolation layer and the semiconductor substrate comprises:
forming an etching pattern transfer lamination layer and a mask pattern transfer layer on the first isolation layer;
printing a pattern of the spacer in the mask pattern transfer layer using photolithography;
transferring the pattern in the mask pattern transfer layer to form a main etching pattern mask by using the etching pattern transfer lamination;
and etching the first isolation layer and the substrate by using the main etching pattern mask.
11. The method for manufacturing according to claim 10, wherein the printing the pattern of the spacer in the mask pattern transfer layer using photolithography includes:
forming a hard mask layer and a nitride layer on the mask pattern transfer layer;
forming a circular mask pattern on the nitride layer;
etching the hard mask layer and the nitride layer by using the circular mask pattern, thereby obtaining a circular groove pattern on the mask pattern transfer layer;
and repeating the steps of forming a circular mask pattern and etching to obtain an 8-shaped groove pattern on the mask pattern transfer layer.
12. A producing method according to claim 10, wherein said etching the pattern transfer laminate includes forming from below: the mask comprises a first spin-on hard mask layer, a first protective layer, a second spin-on hard mask layer and a second protective layer.
13. The method of claim 12, wherein transferring the pattern in the mask pattern transfer layer to form a main etch pattern mask using the etch pattern transfer stack comprises:
taking the pattern in the mask pattern transfer layer as a mask, and etching the second protective layer and the second spin-on hard mask layer to form a second spin-on hard mask layer pattern;
forming a dielectric layer on the second spin-on hard mask layer pattern;
and removing the second spin-on hard mask layer pattern so as to transfer the pattern of the isolation part to the dielectric layer and form a main etching pattern mask.
14. The method of claim 10, wherein said etching said first isolation layer and said substrate using said main etch pattern mask comprises:
etching the first isolation layer and the substrate by using the main etching pattern mask, and forming a hard mask with an arc-shaped fillet at the top on the first spin-coating hard mask layer;
the hard mask is removed.
15. The method of claim 11, further comprising the steps of: and after the isolation part is obtained, forming a side wall on the side wall of the isolation part.
16. The method of claim 15, wherein the material forming the sidewall spacers further comprises: nitride or silicon.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102117772A (en) * 2009-12-30 2011-07-06 海力士半导体有限公司 Semiconductor device with vertical cells and fabrication method thereof
US20120187535A1 (en) * 2011-01-26 2012-07-26 Hynix Semiconductor Inc. Semiconductor device and method for manufacturing the same
CN104900584A (en) * 2014-03-05 2015-09-09 爱思开海力士有限公司 Semiconductor device with line-type air gaps and method for fabricating the same
US10050041B1 (en) * 2015-01-05 2018-08-14 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
US20190103302A1 (en) * 2017-09-29 2019-04-04 SK Hynix Inc. Semiconductor device with air gap and method for fabricating the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102117772A (en) * 2009-12-30 2011-07-06 海力士半导体有限公司 Semiconductor device with vertical cells and fabrication method thereof
US20120187535A1 (en) * 2011-01-26 2012-07-26 Hynix Semiconductor Inc. Semiconductor device and method for manufacturing the same
CN104900584A (en) * 2014-03-05 2015-09-09 爱思开海力士有限公司 Semiconductor device with line-type air gaps and method for fabricating the same
US10050041B1 (en) * 2015-01-05 2018-08-14 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
US20190103302A1 (en) * 2017-09-29 2019-04-04 SK Hynix Inc. Semiconductor device with air gap and method for fabricating the same

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