CN116031227A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN116031227A
CN116031227A CN202211297992.XA CN202211297992A CN116031227A CN 116031227 A CN116031227 A CN 116031227A CN 202211297992 A CN202211297992 A CN 202211297992A CN 116031227 A CN116031227 A CN 116031227A
Authority
CN
China
Prior art keywords
bonding material
semiconductor device
semiconductor chip
electrode
back electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211297992.XA
Other languages
English (en)
Inventor
酒井伸次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of CN116031227A publication Critical patent/CN116031227A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4839—Assembly of a flat lead with an insulating support, e.g. for TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32013—Structure relative to the bonding area, e.g. bond pad the layer connector being larger than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/182—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/186—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

得到一种半导体装置及其制造方法，其能够提高散热性，减小散热性的波动。半导体芯片(5)的背面电极(6)与导电性的管芯焊盘(4)通过含Ag量50‑85％的Ag接合材料(8)而接合。端子(2)与半导体芯片(5)连接。绝缘性的封装树脂(1)将管芯焊盘(4)、半导体芯片(5)、Ag接合材料(8)及端子(2)的一部分。端子(2)从封装树脂(1)凸出，在前端具有基板接合面。金属毛刺(16)从与Ag接合材料(8)接触的背面电极(6)的下表面的外周部凸出。Ag接合材料(8)的厚度比金属毛刺(16)的上下方向的高度大2μm以上。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置及其制造方法。
背景技术
通常使用焊料作为半导体芯片的背面电极与管芯焊盘之间的接合材料。特别地，在通过回流进行基板安装的情况下，使用铅含量多的高熔点焊料(例如，参照专利文献1)。但是，即使在应对于基板回流或高可靠性用途等需要高熔点焊料的用途中，也开始考虑到环境影响而限制焊料中的铅含量。考虑到环境影响而应用使用了Ag膏的烧结结合。
专利文献1：日本特开2005-150595号公报
但是，存在由于热收缩和溶剂的挥发而在Ag接合材料中容易产生孔洞的问题。通过半导体芯片的切割，从而在从半导体芯片的背面电极的外周部进行俯视观察时，大致环状的金属毛刺凸出。已判明该金属毛刺会阻碍在Ag膏中产生的溶剂的挥发部分向外部排出。存在由于孔洞的产生而产生散热性的下降和波动的问题。
发明内容
本发明就是为了解决上述这样的课题而提出的，其目的在于，得到能够提高散热性、减小散热性的波动的半导体装置及其制造方法。
本发明涉及的半导体装置的特征在于，具有：导电性的管芯焊盘；半导体芯片；背面电极，其设置于所述半导体芯片的背面；含Ag量50-85％的Ag接合材料，其将所述背面电极与所述管芯焊盘接合；端子，其与所述半导体芯片连接；以及绝缘性的封装树脂，其将所述管芯焊盘、所述半导体芯片、所述Ag接合材料及所述端子的一部分覆盖，金属毛刺从与所述Ag接合材料接触的所述背面电极的下表面的外周部凸出，所述Ag接合材料的厚度比所述金属毛刺的上下方向的高度大2μm以上。
发明的效果
在本发明中，Ag接合材料的厚度比金属毛刺的上下方向的高度大2μm以上。由此，能够确保使在对Ag膏进行烧结时由于溶剂的挥发或收缩而产生的孔洞释放出去的路径。因此，能够减少Ag接合材料中的孔洞。因此，能够提高散热性，减小散热性的波动。
附图说明
图1是表示实施方式1涉及的半导体装置的俯视图。
图2是沿图1的I-II的剖视图。
图3是将实施方式1涉及的半导体装置的半导体芯片放大的剖视图。
图4是表示实施方式1涉及的半导体装置的制造方法的剖视图。
图5是表示实施方式1涉及的半导体装置的制造方法的剖视图。
图6是表示实施方式1涉及的封装件被面安装于绝缘基板的状态的剖视图。
图7是将实施方式2涉及的半导体装置的半导体芯片的安装部分放大的剖视图。
图8是表示实施方式2涉及的半导体装置的制造工序的剖视图。
具体实施方式
参照附图，对实施方式涉及的半导体装置及其制造方法进行说明。对相同或相应的结构要素标注相同的标号，有时省略重复说明。
实施方式1
图1是表示实施方式1涉及的半导体装置的俯视图。封装树脂1在俯视观察时呈长方形。从封装树脂1的相对的长边分别凸出有端子2、3。
图2是沿图1的I-II的剖视图。端子2、3和管芯焊盘4是由铜等金属形成的导电性的引线框。管芯焊盘4与端子2连结。端子2与端子3电分离。
半导体芯片5是由Si或SiC形成的功率芯片。在半导体芯片5的背面设置有背面电极6，在表面设置有表面电极7。Ag接合材料8将半导体芯片5的背面电极6与管芯焊盘4接合。端子2经由管芯焊盘4及Ag接合材料8而与半导体芯片5连接。
半导体芯片9是对半导体芯片5的导通进行控制的控制IC。在半导体芯片9的背面设置有背面电极10，在表面设置有表面电极11。Ag接合材料12将半导体芯片9的背面电极10与端子3接合。端子3经由Ag接合材料12而与半导体芯片9连接。Ag接合材料8、12含有50-85％的Ag。
导线13将半导体芯片5的表面电极7与半导体芯片9的表面电极11电连接。导线13由Cu、Al、Au等材质形成。在管芯焊盘4的表面接合有半导体芯片5，在背面接合有绝缘层14。在绝缘层14的背面接合有散热板15。散热板15例如由铜材形成。
绝缘性的封装树脂1将管芯焊盘4、半导体芯片5、9、Ag接合材料8、12、导线13及端子2、3的一部分覆盖。散热板15的背面从封装树脂1露出，将半导体芯片5的通电时的发热散热至外部。从封装树脂1的侧面凸出的端子2、3向下方弯折。端子2、3的前端部被调整至比封装树脂1低的位置处，具有与封装树脂1的背面或散热板15平行的基板接合部。通过具有基板接合面，从而能够将封装件面安装于基板。
图3是将实施方式1涉及的半导体装置的半导体芯片放大的剖视图。背面电极6具有从半导体芯片5侧依次层叠的欧姆电极6a、粘接层6b及防氧化电极6c。欧姆电极6a与半导体芯片5欧姆接合。最表面的防氧化电极6c与Ag接合材料8接触。在从背面电极6的下表面的外周部进行俯视观察时，大致环状的金属毛刺16向下方凸出。Ag接合材料8的厚度t比金属毛刺16的上下方向的高度h大2μm以上。
接着，对本实施方式涉及的半导体装置的制造方法进行说明。图4及图5是表示实施方式1涉及的半导体装置的制造方法的剖视图。
首先，如图4所示，使用切割刀具17对半导体晶片18进行切割而分割成单个的半导体芯片5。此时，背面电极6由于高温而变形，成为金属毛刺16。
接下来，如图5所示，在导电性的管芯焊盘4之上涂敷Ag膏19。将具有背面电极6的半导体芯片5载置于Ag膏19之上。在200℃下对Ag膏19进行2小时左右的加热，将管芯焊盘4与背面电极6烧结接合。烧结后的Ag膏19成为Ag接合材料8。在管芯焊盘4之上涂敷的Ag膏19的厚度被设定为烧结后的Ag接合材料8的厚度比金属毛刺16的上下方向的高度大2μm以上。
优选烧结前的Ag膏19的粘度大于或等于20Pa·S，优选为25Pa·S左右。这样，通过使用粘度高的Ag膏19，从而能够以少的量使Ag膏19变厚。另外，能够削减Ag膏19的供给量。由此，能够防止由于Ag膏19的供给过多导致的Ag膏19的飞散、向半导体芯片5的表面的漫入或向管芯焊盘4的背面的漫入，避免半导体芯片5的倾斜等。此外，Ag膏19的厚度上限值是由封装件高度、管芯焊盘4的面积、膏粘度、半导体芯片5的倾斜精度等决定的。
此外，由于Ag膏19包含溶剂，因此烧结后的Ag含有率小于或等于85％，但不是膏的Ag接合材料的Ag含有率高于85％。在使用不是膏的Ag接合材料的情况下不存在孔洞的课题，因此不是本发明的对象。
图6是表示实施方式1涉及的封装件被面安装于绝缘基板的状态的剖视图。绝缘基板20具有绝缘材料21和在绝缘材料21的表面设置的金属配线22。从封装树脂1凸出的端子2的基板接合面通过导电性的接合材料23而与金属配线22接合。
含Ag量50-85％的Ag接合材料8的再熔融温度是960度。另一方面，接合材料23例如是铅95％焊料，其熔融温度是300度。因此，接合材料23的熔融温度低于Ag接合材料8的再熔融温度。
在管芯焊盘4与背面电极6通过Ag接合材料8而接合且被树脂封装之后，将从封装树脂1凸出的端子2、3通过接合材料23而与金属配线22接合。在该回流时封装件内的Ag接合材料8也被暴露于高温。因此，使通过回流而使端子2、3与金属配线22接合时的加热温度低于Ag接合材料8的再熔融温度。由此，能够防止Ag接合材料8的再熔融。由于Ag接合材料8不会再熔融，因此能够保证高的产品可靠性。因此，就面安装的半导体装置而言，应用Ag接合材料8的优点大。
如以上所说明的那样，在本实施方式中，Ag接合材料8的厚度比金属毛刺16的上下方向的高度大2μm以上。由此，能够确保使在对Ag膏19进行烧结时由于溶剂的挥发或收缩而产生的孔洞释放出去的路径。因此，能够减少Ag接合材料8中的孔洞。因此，能够提高散热性，减小散热性的波动。
如果Ag接合材料8的厚度比金属毛刺16的高度大2μm以上，则孔洞呈减少倾向，如果大5μm以上，则得到孔洞大幅度地减少的结果。因此，优选Ag接合材料8的厚度比金属毛刺16的高度大5μm以上。
金属毛刺16的高度与背面电极6的厚度成正比。使用层叠有Al-Si、Ti、Ni、Au的背面电极6进行实验的结果是，得到以下这样的背面电极6的厚度与金属毛刺16的高度的关系。此外，Al-Si层与Si/SiC基板之间的欧姆性良好，即，是接触电阻低的欧姆电极6a。Au层是防氧化电极6c，Ti层及Ni层是粘接层6b。Al-Si层的厚度固定为800μm，对Au层、Ti层及Ni层的总厚度进行了变更。此外，在下述数据中，记载了背面电极6的层叠构造中的除欧姆电极6a以外的防氧化电极6c和粘接层6b的合计厚度。
【表1】
防氧化电极与粘接层的总厚度 金属毛刺的长度
样本1 850μm 13.16μm
样本2 500μm 11.17μm
样本3 150μm 6.05μm
样本4 100μm 5.05μm
样本5 50μm 4.35μm
可知能够通过使背面电极6的总厚度变薄而抑制金属毛刺16的产生。欧姆电极6a也能够设为小于或等于100μm，根据防氧化电极6c的材质的选择，欧姆电极6a可以省略。确认到在使欧姆电极6a变薄的情况下，与削减了防氧化电极6c和粘接层6b的合计厚度的情况同样地，能够抑制金属毛刺16。
另外，可知通过将背面电极6的厚度设为小于或等于1650μm(样本1)，从而降低孔洞占有背面电极6的下表面整体的占有面积。因此，优选背面电极6的厚度小于或等于1650μm。更优选背面电极6的厚度小于或等于1000μm，最优选小于或等于100μm。另外，通过使金属毛刺16的高度变小，从而能够使Ag接合材料8的厚度变薄，因此，能够减小热阻和成本。
另外，背面电极6也可以是1层欧姆电极6a和1层防氧化电极6c的层叠构造。由于没有Ti、Ni等粘接层6b，因此能够抑制背面电极6的总厚度。例如，在欧姆电极6a是Al-Si、防氧化电极6c是Au的层叠构造的情况下，能够使其合计厚度小于或等于100μm。
欧姆电极6a也可以变更为可与Si/SiC欧姆接触的除Al-Si以外的金属。防氧化电极6c也可以变更为可实现氧化及硫化对策的除Au以外的金属，例如Ag。另外，与Ag接合材料8接触的防氧化电极6c也可以是Ag层。由此，能够提高背面电极6与Ag接合材料8之间的密接性及导通性。另外，欧姆电极6a也可以是Ag合金层。由此，能够确保半导体芯片5与背面电极6之间的欧姆性。
如果背面电极6的最表面的防氧化电极6c是Au层，则能够实现背面电极6的防氧化/防硫化，能够稳定地确保背面电极6与管芯焊盘4的电接合及机械接合。
背面电极6也可以是从半导体芯片5侧层叠有Ag合金-Ag-Au的构造或层叠有Ag合金-Au的构造。由此，材料数变少，制造性提高，能够削减成本。另外，能够使背面电极6的厚度变薄、使金属毛刺16的高度变小而减少孔洞。另外，Ag合金与Si实现欧姆接触，因此能够削减Al-Si、Ti、Ni层。
实施方式2
图7是将实施方式2涉及的半导体装置的半导体芯片的安装部分放大的剖视图。背面电极6的端部配置于比半导体芯片5的背面的端部更靠内侧处。在图中仅示出了矩形的功率芯片的2边的端部，但剩余的2边的端部也是同样地，背面电极6的端部配置于比半导体芯片5的背面的端部更靠内侧处。在背面电极6不存在金属毛刺16。其它结构与实施方式1相同。
图8是表示实施方式2涉及的半导体装置的制造工序的剖视图。当在半导体晶片18形成背面电极6时，以在后来成为半导体芯片5的端部的位置不形成背面电极6的方式进行图案化。在对半导体晶片18进行切割而分割成单个的半导体芯片5时，不对背面电极6进行切割。因此，在背面电极6没有形成金属毛刺16。因此，能够确保使在对Ag膏19进行烧结时由于溶剂的挥发或收缩而产生的孔洞释放出去的路径。因此，能够减少Ag接合材料8中的孔洞。因此，能够提高散热性，减小散热性的波动。另外，通过不存在金属毛刺16而使Ag接合材料8的厚度变小，因此也能够减小热阻和成本。
此外，半导体芯片5不限于由硅形成，也可以由与硅相比带隙大的宽带隙半导体形成。宽带隙半导体例如是碳化硅、氮化镓类材料或金刚石。由这样的宽带隙半导体形成的半导体芯片由于耐电压性及容许电流密度高，因此能够小型化。通过使用该小型化的半导体芯片，从而组装有该半导体芯片的半导体装置也能够小型化、高集成化。另外，由于半导体芯片的耐热性高，因此能够使散热器的散热鳍片小型化，能够使水冷部空冷化，因而能够使半导体装置进一步小型化。另外，由于半导体芯片的电力损耗低且高效，因此能够使半导体装置高效化。
标号的说明
1封装树脂，2端子，4管芯焊盘，5半导体芯片，6背面电极，6a欧姆电极，6c防氧化电极，8Ag接合材料、16金属毛刺、19Ag膏，21绝缘材料，20绝缘基板，22金属配线，23接合材料。

Claims (14)

1.一种半导体装置，其特征在于，具有：
导电性的管芯焊盘；
半导体芯片；
背面电极，其设置于所述半导体芯片的背面；
含Ag量50-85％的Ag接合材料，其将所述背面电极与所述管芯焊盘接合；
端子，其与所述半导体芯片连接；以及
绝缘性的封装树脂，其将所述管芯焊盘、所述半导体芯片、所述Ag接合材料及所述端子的一部分覆盖，
所述端子从所述封装树脂凸出，在所述端子的前端具有基板接合面，
金属毛刺从与所述Ag接合材料接触的所述背面电极的下表面的外周部凸出，
所述Ag接合材料的厚度比所述金属毛刺的上下方向的高度大2μm以上。
2.根据权利要求1所述的半导体装置，其特征在于，
所述Ag接合材料的厚度比所述金属毛刺的上下方向的高度大5μm以上。
3.根据权利要求1或2所述的半导体装置，其特征在于，
除所述金属毛刺以外的所述背面电极的厚度小于或等于1650μm。
4.根据权利要求1至3中任一项所述的半导体装置，其特征在于，
所述背面电极是与所述半导体芯片欧姆接合的欧姆电极和与所述Ag接合材料接触的防氧化电极的层叠构造。
5.根据权利要求4所述的半导体装置，其特征在于，
所述背面电极仅由1层所述欧姆电极和1层所述防氧化电极构成。
6.根据权利要求4或5所述的半导体装置，其特征在于，
所述欧姆电极由Al-Si或Ag合金形成。
7.根据权利要求4至6中任一项所述的半导体装置，其特征在于，
所述防氧化电极由Au形成。
8.根据权利要求4至6中任一项所述的半导体装置，其特征在于，
所述防氧化电极由Ag形成。
9.一种半导体装置，其特征在于，具有：
导电性的管芯焊盘；
半导体芯片；
背面电极，其设置于所述半导体芯片的背面；
含Ag量50-85％的Ag接合材料，其将所述背面电极与所述管芯焊盘接合；
端子，其与所述半导体芯片连接；以及
绝缘性的封装树脂，其将所述管芯焊盘的一部分、所述半导体芯片及所述Ag接合材料覆盖，
所述端子从所述封装树脂凸出，在所述端子的前端具有基板接合面，
所述背面电极的端部配置于比所述半导体芯片的背面的端部更靠内侧处。
10.根据权利要求1至9中任一项所述的半导体装置，其特征在于，
具有绝缘基板，该绝缘基板具有绝缘材料和在所述绝缘材料的表面设置的金属配线，
所述端子的所述基板接合面通过导电性的接合材料而与所述金属配线接合，
所述接合材料的熔融温度低于所述Ag接合材料的再熔融温度。
11.根据权利要求1至10中任一项所述的半导体装置，其特征在于，
所述半导体芯片由宽带隙半导体形成。
12.一种半导体装置的制造方法，其制造权利要求1至8中任一项所述的半导体装置，
该半导体装置的制造方法的特征在于，具有以下工序：
在所述管芯焊盘之上涂敷Ag膏；
将所述半导体芯片载置于所述Ag膏之上；以及
对所述Ag膏进行加热而将所述管芯焊盘与所述半导体芯片的所述背面电极烧结接合，
烧结后的所述Ag膏是所述Ag接合材料，
在所述管芯焊盘之上涂敷的所述Ag膏的厚度被设定为烧结后的所述Ag接合材料的厚度比所述金属毛刺的上下方向的高度大2μm以上。
13.根据权利要求12所述的半导体装置的制造方法，其特征在于，
烧结前的所述Ag膏的粘度大于或等于20Pa·S。
14.一种半导体装置的制造方法，其制造权利要求10所述的半导体装置，
该半导体装置的制造方法的特征在于，具有以下工序：
在将所述管芯焊盘与所述背面电极通过所述Ag接合材料而接合之后，将所述端子的所述基板接合面通过所述接合材料而与所述金属配线接合，
通过回流而将所述端子与所述金属配线接合时的加热温度低于所述Ag接合材料的再熔融温度。
CN202211297992.XA 2021-10-27 2022-10-21 半导体装置及其制造方法 Pending CN116031227A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021175883A JP2023065215A (ja) 2021-10-27 2021-10-27 半導体装置及びその製造方法
JP2021-175883 2021-10-27

Publications (1)

Publication Number Publication Date
CN116031227A true CN116031227A (zh) 2023-04-28

Family

ID=85795929

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211297992.XA Pending CN116031227A (zh) 2021-10-27 2022-10-21 半导体装置及其制造方法

Country Status (4)

Country Link
US (1) US20230132056A1 (zh)
JP (1) JP2023065215A (zh)
CN (1) CN116031227A (zh)
DE (1) DE102022120253A1 (zh)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4146785B2 (ja) 2003-11-19 2008-09-10 三菱電機株式会社 電力用半導体装置
JP7310698B2 (ja) 2020-05-01 2023-07-19 株式会社豊田自動織機 流体機械

Also Published As

Publication number Publication date
DE102022120253A1 (de) 2023-04-27
JP2023065215A (ja) 2023-05-12
US20230132056A1 (en) 2023-04-27

Similar Documents

Publication Publication Date Title
US8466548B2 (en) Semiconductor device including excess solder
JP4594237B2 (ja) 半導体装置
US8658472B2 (en) Semiconductor device
US20070166877A1 (en) Electronic component and method for its assembly
US5299091A (en) Packaged semiconductor device having heat dissipation/electrical connection bumps and method of manufacturing same
US8637379B2 (en) Device including a semiconductor chip and a carrier and fabrication method
KR20020095053A (ko) 열방출 능력이 개선된 전력용 모듈 패키지 및 그 제조 방법
KR102588854B1 (ko) 파워모듈 및 그 제조방법
JP2012138470A (ja) 半導体素子、半導体装置および半導体装置の製造方法
CN111433910B (zh) 半导体装置以及半导体装置的制造方法
JP6747304B2 (ja) 電力用半導体装置
US10236244B2 (en) Semiconductor device and production method therefor
CN116031227A (zh) 半导体装置及其制造方法
JP4861200B2 (ja) パワーモジュール
US9362221B2 (en) Surface mountable power components
US11967577B2 (en) Semiconductor device and method for manufacturing the same
JP7492375B2 (ja) 半導体装置
JP3446829B2 (ja) 半導体装置
KR102332716B1 (ko) 반도체 패키지
EP4156247A2 (en) Semiconductor device with a semiconductor chip bonded between a first, plate-shaped electrode with a groove and a second electrode
CN117121194A (zh) 电源模块及其制造方法
JP2023141693A (ja) 半導体装置
JP4123131B2 (ja) 半導体装置
CN115692366A (zh) 半导体装置
JP2023131815A (ja) 半導体装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination