CN115692366A - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN115692366A
CN115692366A CN202210867819.2A CN202210867819A CN115692366A CN 115692366 A CN115692366 A CN 115692366A CN 202210867819 A CN202210867819 A CN 202210867819A CN 115692366 A CN115692366 A CN 115692366A
Authority
CN
China
Prior art keywords
sintered body
metal sintered
semiconductor device
semiconductor
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210867819.2A
Other languages
English (en)
Inventor
益本宽之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of CN115692366A publication Critical patent/CN115692366A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49579Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582Metallic layers on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49558Insulating layers on lead frames, e.g. bridging members
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49562Geometry of the lead-frame for devices being provided for in H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29347Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/3301Structure
    • H01L2224/3303Layer connectors having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/335Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/335Material
    • H01L2224/33505Layer connectors having different materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8384Sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • H01L2224/8484Sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/4952Additional leads the additional leads being a bump or a wire
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49568Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49575Assemblies of semiconductor devices on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49579Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49586Insulating layers on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Dispersion Chemistry (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

目的在于提供能够提高半导体装置的可靠性的技术。半导体装置具有绝缘层,该绝缘层具有第1面和与第1面相反侧的第2面。半导体装置具有位于第1面侧的大于或等于1个半导体元件。半导体装置具有第1金属烧结体和第2金属烧结体。第1金属烧结体与绝缘层的第1面及半导体元件接触,将绝缘层与半导体元件接合。第2金属烧结体与绝缘层的第2面接触。

Description

半导体装置
技术领域
本发明涉及半导体装置。
背景技术
例如在专利文献1中,公开了半导体芯片与接合于绝缘板的配线层通过金属烧结体而接合的技术。
专利文献1:日本特开2021-27288号公报
但是,就上述这样的半导体装置而言,由于伴随半导体芯片的驱动而产生的热,在配线层与金属烧结体之间的接合部分及配线层与绝缘板之间的接合部分各自产生应力。其结果,存在在这些接合部分处产生不良情况而可靠性下降的问题。
发明内容
因此,本发明就是鉴于上述这样的问题而提出的,其目的在于提供能够提高半导体装置的可靠性的技术。
本发明涉及的半导体装置具有:绝缘层,其具有第1面和与所述第1面相反侧的第2面;大于或等于1个半导体元件,其位于所述第1面侧;第1金属烧结体,其与所述绝缘层的所述第1面及所述半导体元件接触,将所述绝缘层与所述半导体元件接合;以及第2金属烧结体,其与所述绝缘层的所述第2面接触。
发明的效果
根据本发明,能够减少接合部分,因而能够提高半导体装置的可靠性。
附图说明
图1是表示实施方式1涉及的半导体装置的结构的俯视图。
图2是表示实施方式1涉及的半导体装置的结构的剖视图。
图3是表示第1相关半导体装置的结构的剖视图。
图4是表示实施方式2涉及的半导体装置的结构的剖视图。
图5是表示实施方式3涉及的半导体装置的结构的剖视图。
图6是表示实施方式4涉及的半导体装置的结构的剖视图。
图7是表示实施方式5涉及的半导体装置的结构的剖视图。
具体实施方式
以下,一边参照附图,一边对实施方式进行说明。以下的各实施方式中说明的特征是例示,并非全部的特征都是必须的。另外,在以下示出的说明中,在多个实施方式中对相同的结构要素标注相同或类似的标号,主要对不同的结构要素进行说明。另外,在以下所记载的说明中,“上”、“下”、“左”、“右”、“表”或“背”等特定的位置及方向也并非必须与实际实施时的位置及方向一致。
<实施方式1>
图1是表示本实施方式1涉及的半导体装置的结构的俯视图,图2是沿图1的A-A线的剖视图。
本实施方式1涉及的半导体装置如图2所示具有绝缘层1、半导体元件2、第1金属烧结体3a、第2金属烧结体3b、基座板4、壳体5、粘接剂6、盖7、栅极电极8、发射极电极10、导线11和封装材料12,如图1所示,该半导体装置具有集电极(collector)电极(electrode)9。
如图2所示,绝缘层1具有第1面即上表面和与第1面相反侧的第2面即下表面。绝缘层1例如是由陶瓷构成的绝缘板。
半导体元件2位于绝缘层1的上表面侧。半导体元件2例如包含IGBT(InsulatedGate Bipolar Transistor)及MOSFET(Metal Oxide Semiconductor Field EffectTransistor)等半导体开关元件或PND(PN junction Diode)及SBD(Schottky BarrierDiode)等二极管。在本实施方式1中,半导体元件2的材料是通常的硅(Si),但如后述的那样不限于此。另外,在本实施方式1中,半导体元件2的数量是2个,但只要大于或等于1个即可。
第1金属烧结体3a与绝缘层1的上表面及半导体元件2接触,将绝缘层1与半导体元件2接合。第2金属烧结体3b与绝缘层1的下表面接触。此外,金属烧结是使金属在低于其熔点的温度下固化,即,使金属在低于其熔点的温度下烧结的技术。金属烧结体是通过以下方式形成的,即,涂敷向铜(Cu)或银(Ag)等金属的颗粒混入了溶剂的膏材料,通过金属烧结使膏材料固化。在本实施方式1中,第1金属烧结体3a承担电路图案的作用。
基座板4与第2金属烧结体3b接触,通过第2金属烧结体3b与绝缘层1接合。壳体5将半导体元件2的外周(这里是侧部)覆盖。粘接剂6将壳体5粘接于基座板4。此外,在图1及图2的例子中,在壳体5设置有孔5a,通过穿过孔5a的螺钉等将壳体5固定于基座板4。盖7将半导体元件2的上部覆盖。通过基座板4、壳体5和盖7而形成与外部空间隔离开的内部空间。
栅极电极8、集电极电极9及发射极电极10在它们的一端及另一端分别位于外部空间及内部空间的状态下与壳体5一体地设置。半导体元件2经由导线11与栅极电极8及发射极电极10的内部空间内的一端电连接。另外,如图1所示,半导体元件2经由导线11及第1金属烧结体3a与集电极电极9的内部空间内的一端电连接。图2的封装材料12例如由绝缘材料构成,被填充于半导体元件2及导线11等所在的内部空间内。
以上这样的半导体装置例如用于能够通过栅极电极8的电压对依次流过集电极电极9、导线11、第1金属烧结体3a、半导体元件2、导线11、发射极电极10的主电流进行控制的逆变器电路等。
这里,对与本实施方式1涉及的半导体装置相关的半导体装置(以下,记述为第1相关半导体装置及第2相关半导体装置)进行说明。图3是表示第1相关半导体装置的结构的剖视图。
就第1相关半导体装置而言,绝缘层1与不是金属烧结体的铜图案14a通过银钎料13a而接合,绝缘层1与不是金属烧结体的铜图案14b通过银钎料13b而接合。铜图案14a与半导体元件2通过焊料15a而接合,铜图案14b与基座板4通过焊料15b而接合。
就以上这样的第1相关半导体装置的结构而言,如果由于半导体元件2反复ON/OFF的驱动而使第1相关半导体装置内的温度升降,则在焊料15a、15b处反复产生应力。其结果,产生以焊料15a、15b为起点的裂缝等,存在产品寿命等可靠性下降的问题。另外,作为绝缘层1与铜图案14a及铜图案14b各自之间的接合材料而使用主要成分为银的银钎料13a、13b,因此,存在产生晶须而使可靠性下降的问题。
接下来,对未图示的第2相关半导体装置进行说明。第2相关半导体装置是在图1的本实施方式1涉及的半导体装置的结构的基础上,在第1金属烧结体3a与绝缘层1之间及第2金属烧结体3b与绝缘层1之间设置通常的配线层。就这样的第2相关半导体装置而言,如果在配线层与第1金属烧结体3a及第2金属烧结体3b之间的接合部分及配线层与绝缘层1之间的接合部分各自产生上述应力,则存在在接合部分处产生不良情况而可靠性下降的问题。
与此相对,在本实施方式1中,不使用第1相关半导体装置的焊料15a、15b,因而能够延长功率循环、热循环等产品寿命,能够提高可靠性。另外,由于不使用第1相关半导体装置的银钎料13a、13b,因而能够抑制晶须的产生,能够提高半导体装置的可靠性。
另外,就第2相关半导体装置而言,具有配线层与第1金属烧结体3a及第2金属烧结体3b之间的接合部分及配线层与绝缘层1之间的接合部分这2个接合部分。与此相对,在本实施方式1中,配线层与绝缘层1之间的接合部分消失,能够减少为第1金属烧结体3a及第2金属烧结体3b与绝缘层1之间的接合部分这1个接合部分。由此,能够减少由于应力而产生不良情况的接合部分,因而能够提高半导体装置的可靠性。
<实施方式2>
图4是表示本实施方式2涉及的半导体装置的结构的剖视图。
就本实施方式2涉及的半导体装置而言,不具有在实施方式1中说明过的基座板4,绝缘层1的下表面侧的第2金属烧结体3b承担基座板4的热扩散的作用。根据这样的结构,能够减少部件数量。另外,还能够期待半导体装置的低高度化(小型化)。
另外,就本实施方式2涉及的半导体装置而言,追加有与绝缘层1的上表面接触,在与壳体5之间设置有粘接剂6的第3金属烧结体3c。根据这样的结构,能够缓和从壳体5向绝缘层1的应力,因而能够抑制绝缘层1的裂缝等,能够提高半导体装置的可靠性。
<实施方式3>
图5是表示本实施方式3涉及的半导体装置的结构的剖视图。本实施方式3涉及的半导体装置具有金属板材17以取代实施方式2的将多个半导体元件2连接的导线11。金属板材17相对于多个半导体元件2而位于与绝缘层1相反侧,与多个半导体元件2接合。这样,根据金属板材17被用于配线的本实施方式3涉及的半导体装置,与导线11被用于配线的结构相比,能够提高功率循环寿命或降低半导体装置的内部电感。
此外,将多个半导体元件2与金属板材17接合的接合材料也可以是焊料等,但在本实施方式3中使用金属烧结体。即,就本实施方式3涉及的半导体装置而言,追加有将多个半导体元件2与金属板材17接合,具有与第1金属烧结体3a及第2金属烧结体3b的材料相同的材料的第4金属烧结体3d。
在将多个半导体元件2与金属板材17接合的接合材料的材料与第1金属烧结体3a等的材料不同的情况下,这些部件的熔点不同,因此,这些部件中的在制造工序中稍后被接合或烧结的部件需要使用低熔点部件。与此相对,在本实施方式3中,由于这些部件的熔点实质上相同,因此,能够同时进行这些部件的烧结。另外,由于不需要使用低熔点的部件,因此能够应对半导体元件2的高温动作。
此外,在以上的说明中,本实施方式3被应用于实施方式2,但也可以应用于实施方式1。
<实施方式4>
图6是表示本实施方式4涉及的半导体装置的结构的剖视图。在本实施方式4中,相比于实施方式3的结构,半导体元件2之下的第1金属烧结体3a的厚度大于或等于0.2mm,变得较厚。根据这样的结构,能够高效地对半导体元件2的发热进行散热,能够降低驱动时的半导体装置内部的最大温度,因此例如能够延长产品寿命。
此外,第1金属烧结体3a的厚度可以大于第2金属烧结体3b的厚度,但是比第2金属烧结体3b、第3金属烧结体3c及第4金属烧结体3d的哪一者的厚度大都可以。根据这样的结构,能够使半导体元件2的发热在半导体元件2至绝缘层1之间沿水平方向扩散,因此能够高效地散热。其结果,即使是导热率低的部件被用于绝缘层1的结构,也能够抑制散热性下降,因而能够提高可靠性。另外,通常,内部空间的高度较大,因此,即使增大第1金属烧结体3a的厚度,也能够维持半导体装置的尺寸。
另外,只要第1金属烧结体3a及第2金属烧结体3b的厚度不同即可,只要第1金属烧结体3a、第2金属烧结体3b、第3金属烧结体3c及第4金属烧结体3d中的任意大于或等于2者的厚度不同即可。第1金属烧结体3a~第4金属烧结体3d存在应力缓和、散热性提高等效果,但通过将第1金属烧结体3a~第4金属烧结体3d的厚度设为适于各自的效果的厚度,从而能够使它们的效果适当化。
此外,在以上的说明中,本实施方式4被应用于实施方式3,但也可以应用于实施方式1、2的任意者。
<实施方式5>
图7是表示本实施方式5涉及的半导体装置的结构的剖视图。就本实施方式5而言,相比于实施方式4的结构,半导体元件2之下的第1金属烧结体3a具有沿半导体元件2的外周的凹部18。并且,第1金属烧结体3a的外周部向上侧凸出。根据这样的结构,能够通过凹部18而抑制第1金属烧结体3a在烧结时蔓延至半导体元件2上部,因而能够抑制半导体装置的动作异常。
此外,在以上的说明中,本实施方式5被应用于实施方式4,但也可以应用于实施方式1~3中的任意者。
<变形例1>
在实施方式1~5中,第1金属烧结体3a及第2金属烧结体3b的至少任一者的主要成分也可以是铜,第1金属烧结体3a~第4金属烧结体3d的至少任一者的主要成分也可以是铜。铜的导热率较高,另外,铜的电阻较低,因而能够期待半导体装置的高密度化。另外,由于抑制了银的使用,因而能够抑制晶须的产生。
<变形例2>
在实施方式1~5中,半导体元件2的材料也可以包含宽带隙半导体。宽带隙半导体例如包含碳化硅(SiC)、氮化镓(GaN)、金刚石等。在半导体元件2的材料包含适用于高温动作和高频使用时的低损耗化的碳化硅的结构中,上述的高散热化、低电感化特别有效,能够实现半导体装置的高品质化及高特性化。
<变形例3>
在实施方式1~5中,半导体元件2也可以包含RC-IGBT(反向导通IGBT)。在半导体元件2包含RC-IGBT的结构中,半导体元件2的发热变大,但由于上述的高散热性及高温时的高可靠性,能够减小由半导体元件2的发热造成的缺点。另一方面,能够得到由使用RC-IGBT带来的半导体装置的高密度化的优点。
此外,能够对各实施方式及各变形例自由地进行组合,或对各实施方式及各变形例适当地进行变形、省略。
标号的说明
1绝缘层,2半导体元件,3a第1金属烧结体,3b第2金属烧结体,3c第3金属烧结体,3d第4金属烧结体,4基座板,5壳体,6粘接剂,17金属板材,18凹部。

Claims (12)

1.一种半导体装置,其具有:
绝缘层,其具有第1面和与所述第1面相反侧的第2面;
大于或等于1个半导体元件,其位于所述第1面侧;
第1金属烧结体,其与所述绝缘层的所述第1面及所述半导体元件接触,将所述绝缘层与所述半导体元件接合;以及
第2金属烧结体,其与所述绝缘层的所述第2面接触。
2.根据权利要求1所述的半导体装置,其中,
还具有:基座板,其与所述第2金属烧结体接触,通过所述第2金属烧结体与所述绝缘层接合。
3.根据权利要求1所述的半导体装置,其中,
还具有:
壳体,其将所述半导体元件覆盖;以及
第3金属烧结体,其与所述绝缘层的所述第1面接触,在所述第3金属烧结体与所述壳体之间设置有粘接剂。
4.根据权利要求1至3中任一项所述的半导体装置,其中,
所述大于或等于1个半导体元件是多个半导体元件,
所述半导体装置还具有:金属板材,其相对于所述多个半导体元件而位于与所述绝缘层相反侧,与所述多个半导体元件接合。
5.根据权利要求4所述的半导体装置,其中,
还具有:第4金属烧结体,其将所述多个半导体元件与所述金属板材接合,所述第4金属烧结体具有与所述第1金属烧结体及所述第2金属烧结体的材料相同的材料。
6.根据权利要求1至5中任一项所述的半导体装置,其中,
所述第1金属烧结体的厚度大于或等于0.2mm。
7.根据权利要求1至6中任一项所述的半导体装置,其中,
所述第1金属烧结体的厚度大于所述第2金属烧结体的厚度。
8.根据权利要求1至7中任一项所述的半导体装置,其中,
所述第1金属烧结体及所述第2金属烧结体的厚度不同。
9.根据权利要求1至8中任一项所述的半导体装置,其中,
所述第1金属烧结体具有沿所述半导体元件的外周的凹部。
10.根据权利要求1至9中任一项所述的半导体装置,其中,
所述第1金属烧结体及所述第2金属烧结体的至少任一者的主要成分是铜。
11.根据权利要求1至10中任一项所述的半导体装置,其中,
所述半导体元件的材料包含宽带隙半导体。
12.根据权利要求1至11中任一项所述的半导体装置,其中,
所述半导体元件包含RC-IGBT。
CN202210867819.2A 2021-07-26 2022-07-21 半导体装置 Pending CN115692366A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021121516A JP2023017320A (ja) 2021-07-26 2021-07-26 半導体装置
JP2021-121516 2021-07-26

Publications (1)

Publication Number Publication Date
CN115692366A true CN115692366A (zh) 2023-02-03

Family

ID=84784697

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210867819.2A Pending CN115692366A (zh) 2021-07-26 2022-07-21 半导体装置

Country Status (4)

Country Link
US (1) US20230028808A1 (zh)
JP (1) JP2023017320A (zh)
CN (1) CN115692366A (zh)
DE (1) DE102022118114A1 (zh)

Also Published As

Publication number Publication date
US20230028808A1 (en) 2023-01-26
DE102022118114A1 (de) 2023-01-26
JP2023017320A (ja) 2023-02-07

Similar Documents

Publication Publication Date Title
JP6300386B2 (ja) 半導体装置
US10971431B2 (en) Semiconductor device, cooling module, power converting device, and electric vehicle
JP6755386B2 (ja) 電力用半導体モジュールおよび電力用半導体モジュールの製造方法
CN110192284B (zh) 半导体装置和电力变换装置
CN108735692B (zh) 半导体装置
JP2007234690A (ja) パワー半導体モジュール
KR102418458B1 (ko) 전력반도체 모듈
US20150237718A1 (en) Power semiconductor device
JPWO2017183580A1 (ja) 半導体装置、パワーモジュール及びその製造方法
CN111433910B (zh) 半导体装置以及半导体装置的制造方法
JP6747304B2 (ja) 電力用半導体装置
US11127714B2 (en) Printed board and semiconductor device
CN115692366A (zh) 半导体装置
CN109564918B (zh) 半导体装置
US20190006267A1 (en) Solid top terminal for discrete power devices
US11450623B2 (en) Semiconductor device
CN111834307B (zh) 半导体模块
JP7494613B2 (ja) 半導体装置
JP7492375B2 (ja) 半導体装置
KR102588851B1 (ko) 파워모듈 및 그 제조방법
Sato et al. Development of SiC power module for high-speed switching operation
JP2021141237A (ja) 半導体装置
JP2015167171A (ja) 半導体装置
CN116031227A (zh) 半导体装置及其制造方法
JP2024505028A (ja) 熱伝導性接着層を備えた基板を有するパッケージ化された電子デバイス

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination