CN115893299A - 利用芯片下方基板中的腔体控制翘曲的集成电路封装 - Google Patents

利用芯片下方基板中的腔体控制翘曲的集成电路封装 Download PDF

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CN115893299A
CN115893299A CN202210954436.9A CN202210954436A CN115893299A CN 115893299 A CN115893299 A CN 115893299A CN 202210954436 A CN202210954436 A CN 202210954436A CN 115893299 A CN115893299 A CN 115893299A
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integrated circuit
cavity
support substrate
conductive layer
circuit package
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R·杜卡
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STMicroelectronics Malta Ltd
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STMicroelectronics Malta Ltd
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Abstract

本发明涉及利用集成电路芯片下方层压基板中形成的腔体控制翘曲的集成电路封装。支撑基板包括绝缘芯层、绝缘芯层之上的导电层和导电层之上的阻焊层。集成电路芯片的背面在裸片附接位置处安装在支撑基板的上表面。支撑基板的上表面包括位于裸片附接位置内的腔体，其中腔体延伸到集成电路芯片的背面之下。腔体由其中已将阻焊层和导电层的至少一部分移除的区域限定。键合线将集成电路芯片正面上的连接垫连接到支撑基板上表面的连接垫。

Description

利用芯片下方基板中的腔体控制翘曲的集成电路封装
相关申请的交叉引用
本申请从美国临时申请为于2021 8月11日提交的专利号63/231859号要求优先权，本公开内容通过引用并入。
技术领域
本文的实施例涉及集成电路封装，特别是控制安装有集成电路裸片的集成电路封装的层压基板的翘曲。
背景技术
图1示出集成电路封装10的一部分的横截面。封装10包括层压基板12。层压基板12由多个层的层压形成，这些层包括：绝缘(例如，FR4-阻燃剂4)芯层14；在芯层14的每个相对表面上的导电(铜)层18a、18b；在每个铜层18a、18b上的预浸料层16a、16b；在每个预浸料层16a、16b上的导电(铜)层18c、18d；以及在每个铜层18c、18d上的阻焊层20a、20b。层压基板12还可以包括电镀过孔(未明确示出)，其将铜层18a、18c的一部分电连接到铜层18b、18d的一部分。层压基板12可以采用印刷电路板PCB的形式。
集成电路裸片30安装至层压基板12的上表面。集成电路裸片30包括背面32和正面34。在正面34上提供多个集成电路电连接垫36。使用粘合材料38(例如裸片附接胶水或胶带)，在层压基板12上表面处，将集成电路裸片30的背面32附接至阻焊层20a。
在阻焊层20a中选择性地制成开口40，以露出提供层压基板12的连接垫42的铜层18c的相应部分。键合线43在电连接垫36到相应的连接垫42之间电连接。
在阻焊层20b中选择性地制成开口44，以露出提供层压基板12的连接垫46的铜层18d的相应部分。将焊球48安装至连接垫46。
罩体(或盖子)50附接至层压基板12以包封集成电路裸片30。可选地，包封体可以在层压基板12上被二次注模以包封集成电路芯片30。
集成电路裸片30的硅材料与层压基板12之间的热膨胀系数CTE存在已知的不匹配。例如，硅的CTE约为2.8ppm/℃，塑料基板的CTE约为15ppm/℃。CTE中的这种不匹配可能导致设备翘曲的风险，这会产生许多问题，诸如难以附接罩体50；损坏集成电路裸片30的硅材料或粘合材料38；以及修改集成电路裸片30的电子电路的操作(例如，操作参数漂移)。
本领域需要解决设备翘曲的问题。
发明内容
在一个实施例中，集成电路封装包括：由绝缘芯层、绝缘芯层之上的导电层和导电层之上的阻焊层形成的支撑基板，其中支撑基板包括裸片附接位置和第一连接垫；集成电路芯片，具有带第二连接垫的正面和背面，其中背面在裸片附接位置处安装至支撑基板的上表面；其中支撑基板的上表面包括位于裸片附接位置内的腔体，所述腔体延伸到集成电路芯片的背面之下，所述腔体包括一个其中不存在阻焊层和导电层的至少一部分的区域；以及第一和第二连接垫之间的键合线。
在一个实施例中，用于集成电路封装的支撑基板包括：绝缘芯层；在绝缘芯层之上的导电层；在导电层之上的阻焊层；以及在用于所述支撑基板的裸片附接位置处，在支撑基板上的表面中的腔体，该腔体包括其中不存在阻焊层和导电层的至少一部分的区域。
附图说明
为了更好地理解实施例，现在仅通过示例参考附图，其中：
图1是集成电路封装一部分的横截面；
图2是一部分集成电路封装的横截面；
图3A-图3B是替代实施例的横截面；
图4A-图4D是示出用于提供腔体的各种布置的简化的横截面图；以及
图5A-图5B是示出腔体与裸片附接位置和安装的集成电路芯片之间关系的俯视图。
具体实施方式
要注意的是，图纸不一定按比例呈现，为了便于理解所示结构，已经对尺寸、形状、厚度等进行了一些夸大。
图2示出了集成电路封装60的一部分的横截面。封装60包括层压(支撑)基板62。层压基板62由多个层的层压形成，这些层包括：绝缘(例如，FR4–阻燃剂4)芯层64；导电(铜)层68a；在芯层64的每个相对表面上的68b；在每个铜层68a、68b上的预浸料层66a、66b；在每个预浸料层66a、66b上的导电(铜)层68c、68d；以及在每个铜层68c、68d上的阻焊层70a、70b。层压基板62还可以包括电镀过孔(未明确示出)，其将铜层68a、68b的一部分电连接到铜层68c、68d的一部分。层压基板62可以采用印刷电路板PCB的形式。
此处的图示为四层铜型基板，但这仅为示例，此处的实施例同样适用于其他类型的基板，这些基板包括两层铜型基板，其省略了铜层68a、68b和预浸料层66a、66b，其中铜层68c、68d位于芯层64的每个相对表面上。
进一步处理层压基板62的上表面，以选择性地移除(例如，使用蚀刻)阻焊层70a和铜层68c的一些部分，以在用于集成电路裸片的裸片附接位置76处形成腔体74。腔体74例如可以形成在裸片附接位置76的外围区域中。在所示示例中，腔体74达到四层铜基板的预浸料层66a；而在两层铜基板的情况下，腔体将达到芯64。
集成电路芯片80在裸片附接位置76处被安装至层压基板62的上表面。集成电路芯片80包括背面82和正面84。在正面84上提供多个集成电路电连接垫86。使用粘合材料88(例如裸片附接胶水或胶带)将集成电路裸片80的背面32附接至层压基板62上表面处的阻焊层70a。要注意的是，由于腔体74的存在，集成电路裸片80的外围部分将悬臂悬挂在腔体之上。因此，在空腔74的位置处存在集成电路裸片80的背面82的一些部分，这些部分与层压基板62分离，相应地减少了CTE失配和翘曲或变形的风险。
在实施例中，集成电路裸片80是微型机电系统(MEMS)设备。MEMS设备可以是腔型设备(诸如具有压力传感器、陀螺仪或加速计)。
在阻焊层70a中选择性地制成开口90，以露出提供层压基板62的连接垫92的铜层68c的相应部分。键合线93将电连接垫86电连接到相应的连接垫92。
在阻焊层70b中选择性地制成开口94，以露出提供层压基板62的连接垫96的铜层68d的相应部分。将焊球98安装至连接垫96。连接垫96可以被布置为形成球栅阵列式布局。
罩体(或盖子)100附接至层压基板62以包封集成电路裸片80。可选地，包封体可以在层压基板62上被二次注模以包封集成电路裸片80。
图3A-图3B示出替代实施例。图2和图3中的相似参考标号涉及相似或类似的组件。注意，在集成电路裸片80的背面82的一些部分的下方提供与电连接垫86的位置竖直对齐(如图2所示)的腔体74，可能会在安装键合线的过程中出现断裂问题。图3A示出腔体74在这些位置被省略。图3B示出，在腔体74被提供的位置处，没有相应的竖直对齐的电气连接垫86。
图2和图3A-图3B的实施例示出在腔体74中的铜层68c被完全移除。然而，可以理解的是，这只是作为示例，在一些实现中，在腔74中的铜层68c的厚度只是仅仅减少(参见图4D)。在这方面，铜层68c在腔体74的位置处的厚度减小仍然有利于将集成电路裸片80的背面82的部分与层压基板62分离。
在将集成电路裸片80附接至层压基板62期间，必须小心，以使在存在腔体74的位置处并不施加裸片附接力。裸片附接力应被限制仅在裸片附接位置76的一些部分处应用，在这些部分中，铜层68c和阻焊层70a保持在适当位置。
图4A-图4D是示出用于提供腔体74的各种布置的简化横截面图。图4A-图4C示出，腔体74的区域与集成电路裸片80的背面82的、其中铜层68c和阻焊层70a保持在适当位置的区域之比可以在1:3到1:1到3:1之间变化。图4D示出腔体74在有相应的键合线连接的位置处不存在，而在没有键合线附接的其他位置处存在。图4D进一步示出一种实施，其中形成腔体并不引起移除铜层68a的整个厚度，而是部分地使该铜层68c减薄。铜层68c的减薄(即开槽或移除)的量取决于用于形成腔体的蚀刻参数。在图4A-图4D中，在形成腔体74后留在裸片附接位置内的阻焊层70a和铜层68ca的剩余部分形成支撑集成电路裸片80背面82的安装基座78。安装基座78可以全部或部分地被腔体74包围。当将集成电路裸片80安装至裸片附接位置76时，安装力最好朝向并通常垂直于基座78的上表面。
现在参考图5A-图5B，其示出封装的俯视图(减去罩体100)。俯视图示出了腔体74与裸片附接位置76的关系。集成电路裸片80在裸片附接位置76处被安装至层压基板62的阻焊层70a上。腔体74通过移除阻焊层70a和铜层68c来形成，以露出预浸料层66a(在四铜层型基板的情况下)或芯64(在双铜层型基板的情况下)。腔体74延伸到集成电路芯片80的外围区域下方，并进一步延伸到集成电路芯片80的外边缘之外。图5A示出在集成电路芯片80的整个外围区域之下提供腔体74的实施方式(横截面对应于图2和图3B，以及图4A-图4C)。另一方面，图5B示出一实现方式，其中腔体74被提供在集成电路芯片80的、其中没有电连接垫86的相应竖直对齐位置的外围区域之下(横截面对应于图3A和图3B以及图4D)。
上述描述通过本发明的示例性实施例的完整和信息性描述的示例性和非限制性示例的方式提供。然而，当结合附图和所附权利要求书阅读时，鉴于前述描述，各种修改和改编对于相关领域的技术人员来说可能变得显而易见。然而，本发明教导的所有此类和类似的修改将仍然在所附权利要求中定义的本发明的范围内。

Claims (24)

1.一种集成电路封装，包括：
支撑基板，由绝缘芯层、绝缘芯层之上的导电层和所述导电层之上的阻焊层形成，其中所述支撑基板包括裸片附接位置和第一连接垫；
集成电路芯片，具有带第二连接垫的正面、以及背面，其中所述背面在所述裸片附接位置处安装在所述支撑基板的上表面上；
其中所述支撑基板的上表面包括位于所述裸片附接位置内的腔体，所述腔体延伸到所述集成电路芯片的所述背面之下，所述腔体包括一区域，所述区域中不存在所述阻焊层和所述导电层的至少部分；以及
所述第一连接垫与所述第二连接垫之间的键合线。
2.根据权利要求1所述的集成电路封装，其中在所述集成电路芯片的外围部分的下方存在所述腔体，所述第二连接垫位于所述外围部分。
3.根据权利要求1所述的集成电路封装，其中在所述集成电路芯片的外围部分的下方不存在所述腔体，所述第二连接垫位于所述外围部分。
4.根据权利要求1所述的集成电路封装，其中所述导电层的不存在的所述部分是所述腔体内所述导电层厚度的一部分。
5.根据权利要求1所述的集成电路封装，其中所述导电层的不存在的所述部分是所述腔体内所述导电层的整个厚度。
6.根据权利要求1所述的集成电路封装，其中所述绝缘芯层由FR4材料制成。
7.根据权利要求1所述的集成电路封装，其中所述导电层由铜制成。
8.根据权利要求1所述的集成电路封装，还包括粘合层，所述粘合层用于将所述集成电路芯片的所述背面附接至所述支撑基板的所述上表面。
9.根据权利要求1所述的集成电路封装，其中所述腔体延伸到所述裸片附接位置之外。
10.根据权利要求1所述的集成电路封装，其中所述腔体延伸到所述集成电路芯片的外边缘之外。
11.根据权利要求1所述的集成电路封装，还包括安装至支撑基板的罩体，并且所述罩体被配置为包封所述集成电路芯片。
12.根据权利要求1所述的集成电路封装，其中在所述裸片附接位置内存在的所述阻焊层的剩余部分和所述导电层的剩余部分形成基座，其中所述集成电路芯片的所述背面安装至所述基座。
13.根据权利要求12所述的集成电路封装，其中所述腔体完全包围所述基座。
14.根据权利要求12所述的集成电路封装，其中所述腔体部分地包围所述基座。
15.一种用于集成电路封装的支撑基板，包括：
绝缘芯层；
在所述绝缘芯层之上的导电层；
在所述导电层之上的阻焊层；以及
在用于所述支撑基板的裸片附接位置处，所述支撑基板的所述上表面中的腔体，所述腔体包括一区域，在所述区域中不存在阻焊层和导电层的至少部分。
16.根据权利要求15所述的支撑基板，其中竖直地在安装至所述裸片附接位置的集成电路芯片的正面上的连接垫将被定位的位置之下，在所述裸片附接位置处在所述支撑基板的所述上表面中不存在所述腔体。
17.根据权利要求15所述的支撑基板，其中所述导电层的不存在的所述部分是所述腔体内所述导电层厚度的一部分。
18.根据权利要求15所述的支撑基板，其中所述导电层的不存在的所述部分是所述腔体内所述导电层的整个厚度。
19.根据权利要求15所述的支撑基板，其中所述绝缘芯层由FR4材料制成。
20.根据权利要求15所述的支撑基板，其中所述导电层由铜制成。
21.根据权利要求15所述的支撑基板，其中所述腔体延伸到所述裸片附接位置之外。
22.根据权利要求15所述的支撑基板，其中在所述裸片附接位置内存在的所述阻焊层的剩余部分和所述导电层的剩余部分形成基座，其中所述集成电路芯片的所述背面安装至基座。
23.根据权利要求22所述的支撑基板，其中所述腔体完全包围所述基座。
24.根据权利要求22所述的支撑基板，其中所述腔体部分地包围所述基座。
CN202210954436.9A 2021-08-11 2022-08-10 利用芯片下方基板中的腔体控制翘曲的集成电路封装 Pending CN115893299A (zh)

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