CN115881670A - 具有集成电阻的碳化硅功率器件以及相应的制造工艺 - Google Patents

具有集成电阻的碳化硅功率器件以及相应的制造工艺 Download PDF

Info

Publication number
CN115881670A
CN115881670A CN202211183677.4A CN202211183677A CN115881670A CN 115881670 A CN115881670 A CN 115881670A CN 202211183677 A CN202211183677 A CN 202211183677A CN 115881670 A CN115881670 A CN 115881670A
Authority
CN
China
Prior art keywords
region
silicon carbide
gate
doped
edge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211183677.4A
Other languages
English (en)
Inventor
M·G·萨吉奥
A·瓜尔内拉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Publication of CN115881670A publication Critical patent/CN115881670A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8213—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using SiC technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Non-Adjustable Resistors (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

公开了具有集成电阻的碳化硅功率器件以及相应的制造工艺。一种碳化硅功率器件具有：管芯，具有碳化硅的功能层和边缘区以及由边缘区包围的有源区；栅极结构，形成在有源区中的功能层的顶表面上；以及栅极接触焊盘，用于偏置栅极结构。该器件还具有集成电阻器，该集成电阻器具有第一导电类型的掺杂区，该掺杂区布置在边缘区中的功能层的前表面处；其中该集成电阻器在功能层中定义了绝缘电阻，该绝缘电阻介于栅极结构与栅极接触焊盘之间。

Description

具有集成电阻的碳化硅功率器件以及相应的制造工艺
技术领域
本公开涉及具有集成电阻的碳化硅功率器件以及相应的制造工艺。
背景技术
电子半导体器件是已知的，特别是例如用于功率电子应用的MOSFET(金属氧化物半导体场效应晶体管)晶体管，这些晶体管是从碳化硅衬底开始制造的。
由于碳化硅的有利的化学-物理特性，这些器件是有利的。例如，碳化硅一般具有比通常在电子器件中使用的硅的带隙更宽的带隙。因此，即使具有相对小的厚度，碳化硅也具有比硅的击穿电压更高的击穿电压，并且因此可有利地用于高电压、高功率以及高温应用中。
特别地，由于结晶质量及其大规模可用性，具有六边形多型(4H-SiC)的碳化硅可以用于功率电子应用。
发明内容
本解决方案提供了用于制造具有改善的特性的具有集成电阻的碳化硅功率器件的技术。
因此，根据本解决方案，提供了碳化硅器件以及相应的制造工艺。
附图说明
为了更好地理解本公开，现在仅通过非限制性示例的方式并参照附图来描述本公开的优选实施例，在附图中：
图1A是已知类型的碳化硅器件的一部分的示意性平面图；
图1B是图1A的器件的一部分沿截面线I-I的截面视图；
图2A是根据本解决方案的实施例的碳化硅器件的示意性平面图；
图2B是图2A的器件的一部分沿截面线II-II的截面图；
图3和图4示出根据本解决方案的相应实施例的碳化硅器件的一部分的相应截面图；以及
图5A-图5G是图2A-图2B的碳化硅器件在相应制造工艺的后续步骤中的截面图。
具体实施例
当将器件(特别是MOSFET晶体管)用于高功率应用时，许多器件并联耦合，以降低导通状态电阻(所谓的RON)。
然而，此方法可能会导致并联器件之间的不平衡，从而导致效率损失。
为了避免不平衡，可以将具有适当值的电阻与MOSFET器件的栅极接触串联插入，以在偏置该MOSFET器件的栅极结构时添加受控电阻。
例如，分立电阻(即，在制造过程中，未在MOSFET器件的管芯内采用集成技术制造)可以分开地安装在该MOSFET器件耦合到的印刷电路上。
例如，串联电阻可集成在MOSFET器件的管芯内，该管芯可通过在栅极接触焊盘附近的多晶硅的对应栅极层的光刻定义来产生。
在栅极接触之前通过分立电阻引入串联电阻具有以下缺点，即更高的制造成本和效率损失的问题。
设想添加光刻定义的多晶硅电阻的解决方案在所生产的晶圆之间并且随着工作温度的变化受到高扩散的影响。
如在此将详细描述的，本解决方案的一个方面设想将碳化硅器件的制造工艺的特点用于上述串联电阻的集成制造。
在一些实施例中，考虑到注入在碳化硅衬底中的掺杂区的激活在与衬底本身上生产的任何材料都不兼容的高温(约1800℃)下进行，则在定义有源区和形成栅极结构以及相应的接触结构和金属化部之前生产该注入的掺杂区。
由于这种特点，因此可以将掺杂区基本上定位在碳化硅衬底内所需的任何位置。
根据本解决方案的一个方面，利用此特点将被设计成在碳化硅衬底内提供绝缘电阻的适当掺杂区布置在器件的边缘区。
在一些实施例中，该电阻被用作插入在器件的栅极接触之前的集成串联电阻。
参考图1A和1B，首先(分别在示意性和简化的平面图中并且在相应的截面图中)示出了碳化硅器件，在一些实施例中为没有上述集成串联电阻的标准类型的功率MOSFET器件；以未在此示出的方式，该串联电阻例如被设置为在该MOSFET器件耦合至的印刷电路板上的分立部件。
由1表示的功率MOSFET器件在包括碳化硅的半导体材料的管芯2中制成。在平面图中，管芯2在水平面xy中具有总体上的矩形或方形形状，其边缘和角对应于所谓的划线(其中之一在图1A中由LT表示)，在该划线处半导体材料的起始晶片已经被切割。
管芯2包括碳化硅(SiC)的功能层4(衬底或形成在相同衬底层上的外延层)，该功能层具有第一导电类型(例如，N型)并且具有顶表面4a。
与划线LT相邻的外围或边缘区2a定义在功能层4中，被设计为容纳功率MOSFET器件1的边缘终止结构；中心或有源区2b也定义在该功能层4中，其中，功率MOSFET器件1被物理地生产，包括例如多个基本单元(units)或单元(cells)3，在一些实施例中是MOSFET晶体管(为简单起见，图1B中仅示出了这些基本单元3中的一个)。
在垂直传导配置的情况下，功能层4构成用于形成功率MOSFET器件1的多个基本单元3共用的漏极区。
上述边缘终止结构包括环形边缘终止区5(在下文中简称为环形区5)，在一些实施例中是在功能层4的表面部分中形成的掺杂有低浓度的P型的第二导电类型的区域。环形区5形成在边缘区2a中并且完全围绕有源区2b(精确地形成围绕有源区的环)。
具有P型的第二导电类型的体阱6设置在有源区2b内并且在功能层4的表面部分处，一个体阱用于功率MOSFET器件1的一个基本单元3。
在每个体阱6内，制成源极区8，该源极区具有N型的第一导电类型，布置在相应的栅极结构3′下方；并且还制成掺杂富集区7，该掺杂富集区是P+型的(具有高掺杂剂浓度)，被设计为提供朝着功率MOSFET器件1的公共主体和源极金属化部的电接触。
在一些实施例中，在有源区2b与边缘区2a之间的重叠区中，最外面的体阱(由6′表示)通过P+型的掺杂连接区9(也是高掺杂的)连接至环形区5。
此外，在功能层4的前表面4a上，功率MOSFET器件1包括：第一薄介电层12(例如，由氧化硅制成)，从该第一薄介电层开始，功率MOSFET器件1的基本单元3的栅极氧化物区形成在有源区2b中；以及厚氧化物区13，在边缘区2a处，在环形区5上。
存在于上述第一介电层12和厚氧化物区13上的(多晶硅或其他导电材料的)栅极层14定义在栅极氧化物区上，以提供功率MOSFET器件1的基本单元3的栅极结构(由3’表示)的电极区域。该栅极层14以连续的方式在边缘区2a中的厚氧化物区13上延伸。
第二介电层15(例如，场氧化物)覆盖上述栅极层14。该第二介电层15在边缘区2a处具有开口15′，并且被金属材料的栅极接触焊盘18覆盖，栅极接触焊盘通过这些开口15′接触栅极层14；栅极接触焊盘18可从功率MOSFET器件1的外部接触并且通过焊接电耦合至栅极电线17，用于偏置和传送来自和朝向功率MOSFET器件1的栅极结构3′的信号。
此外，该第二介电层15和上述第一介电层12在有源区2b中通过源极金属化部16彼此重叠和交叉，该源极金属化部延伸以使体阱6和功率MOSFET器件1的各个基本单元3的源极区8接触和短路。
在一些实施例中，接触区19(例如硅化物的)提供上述源极金属化部16与上述源极区8与体阱6之间的电接触。
在一些实施例中，如图1A中所示，功率MOSFET器件还包括栅极金属化部20，该栅极金属金属化部在边缘区2a处连接至栅极接触焊盘18并且在有源区2b中具有线性延伸部(在该示例中，沿水平面xy的第一轴线x)，其中，该栅极金属化部与第二介电层15相交地接触基本单元3的栅极结构3’(以未详细示出的方式，该基本单元3通常具有与栅极金属化部20的该线性延伸部正交的延伸部，在该示例中，沿水平面xy的第二轴线y)。
参考图2A和图2B，现在(再次以与上述图1A和图1B类似的示意性和简化的平面图和截面图)示出碳化硅器件，在一些实施例中，功率MOSFET器件(这里用100表示)在栅极接触之前设置有集成串联电阻。
功率MOSFET器件100通常以对应于上述功率MOSFET器件1的方式制成(因此对应元件由相同的参考标号表示)，但不同的是，功率MOSFET器件100在边缘区2a处和在边缘区2a内包括介于栅极接触焊盘18与栅极结构3’(与该栅极接触焊盘18串联布置)之间的集成电阻器30。
详细地，该集成电阻器30由掺杂区32定义，在N+型(具有高掺杂剂浓度)的示例中，掺杂区例如通过在功能层4的前表面4a处注入掺杂剂原子产生。
如图2A所示，在一个可能的实施例中，在平面图中(在上述水平面xy中)，该掺杂区32可以具有环状构造，具有围绕上述栅极接触焊盘18的水平延伸部。
在图2B所示的实施例中，该掺杂区32在绝缘阱34内制成，在该示例中，P型掺杂(与上述体阱6类似)依次布置在环形区5内。在所示的实施例中，绝缘阱34的厚度(沿着与上述水平面xy正交的轴线z)小于环形区5的对应厚度。
根据本解决方案的一个方面，在这种情况下，上述栅极接触焊盘18不与栅极层14直接接触，并且该栅极接触焊盘18不与栅极金属化部20直接连接。
在一些实施例中，栅极接触焊盘18在通过厚氧化物区13产生的开口13’内通过例如硅化物的相应第一接触区36a接触集成电阻器30和对应掺杂区32的第一端。
该集成电阻器30和对应掺杂区32的第二端通过例如布置在该开口13’中的硅化物的相应第二接触区36b电连接至上述栅极金属化部20。
在这种情况下，该栅极金属化部20通过穿过第二介电层15的单个开口15’接触栅极层14(在所示的实施例中)。
在这种情况下，栅极电线17也接触栅极接触焊盘18，然而，在栅极接触焊盘之下，不存在栅极层14，而是仅存在第二介电层15和厚氧化物区13。换言之，栅极接触焊盘18的整个水平延伸部直接布置在由厚氧化物区13和第二介电层15形成的介电区上。
事实上，在该实施例中，上述栅极层14停止在集成电阻器30的上述第二端之前的边缘区2a的初始区处。
此外，在这种情况下，栅极接触焊盘18和栅极金属化部20在衬底4的顶表面4a上通过上述第二介电层15的分离部分38电绝缘和分离。
在该实施例中，集成电阻器30的电阻值例如可以包括在0.1Ω至200Ω的范围内。
如图3中所示，功率MOSFET器件100的变体实施例设想，集成电阻器30的上述掺杂区32形成在具有P+型的高掺杂的上述掺杂连接区9内而非形成在相应阱中，该掺杂连接区将最外面的体阱6’连接至环形区5。
在这种情况下，该掺杂连接区9在环形区5内延伸(在该示例中，沿第一轴线x)，直到其到达专用于形成集成电阻器30的区域。
在该实施例中，集成电阻器30的电阻值可以高于200Ω。
如图4所示，功率MOSFET器件100的另一变体实施例设想将集成电阻器30的掺杂区32直接形成在环形区5中，而不存在专用阱。
在该实施例中，集成电阻器30的电阻值例如可以包括在0.001Ω和0.1Ω的范围内。
首先参考图5A，现在描述功率MOSFET器件100的可能的制造工艺，特别参考图2A和2B所示的实施例(然而，如将显而易见的，可以类似地考虑图3和图4的实施例)。
该制造工艺偏离标准工艺流程，例如，图1A和图1B中示出的用于制造功率MOSFET器件1的工艺流程，在边缘区2a中形成上述集成电阻器30，不需要对工艺流程进行实质性改变。
详细地，如图5A所示，首先通过前掩模40形成P型的体注入物，使用光刻技术适当地图案化，用于在功能层4内在有源区2b中形成体阱6，包括被设计为连接至环形区5(稍后将形成)的最外面的体阱6′。
根据本解决方案的一个方面，在该注入步骤中并且通过该前掩模40，还在边缘区2a内形成具有P型掺杂的绝缘阱34(与上述体阱6类似)也。
然后，在图5B，通过前掩模40，利用不同的适当图案化，形成N+型的源极注入物，用于在相应的体阱6内在有源区2b中设置源极区8。
根据本解决方案的一个方面，在该注入步骤中并且通过该前掩模40，还在边缘区2a中(在这种情况下在绝缘阱34内)形成集成电阻器30的掺杂区32。
接下来，在图5C，通过前掩模40，利用不同的适当图案化，形成P+型注入物(具有比体阱6的掺杂更高的掺杂)以在有源区2b中的相应体阱6中提供富集掺杂区7，并且还形成该有源区2b与边缘区2a之间的掺杂连接区9。
然后，在图5D，通过前掩模40，利用不同的适当图案化，形成具有较低掺杂(小于体阱6的掺杂)的P型注入物以提供环形区5，根据本解决方案，该环形区在边缘区2a中包围上述绝缘阱34，在绝缘阱中形成集成电阻器30的掺杂区32。
因此，制造过程随着前掩模40的去除和先前注入的掺杂剂的激活而进行，在一些实施例中，在高温(大约1800℃)下加热。
接下来，如图5E所示，通过形成并且适当的光刻图案化第一介电层12、栅极层14和第二介电层15，在有源区2b中形成功率MOSFET器件1的基本单元3的栅极结构3′。硅化物的接触区19也形成在每个体阱6内。
根据本解决方案的一个方面，在同一工艺步骤期间，在边缘区2a处，对厚氧化物区13以及随后的栅极层14和第二电介质层15进行光刻限定以形成开口13′；在该开口13′内，形成也由硅化物制成的第一接触区36a和第二接触区36b，其分别与掺杂区32的第一端和第二端接触。该第一接触区36a和第二接触区36b被上述第二介电层15的分离部分38分离和电绝缘。
接下来，在图5F，通过光刻工艺，在上述第二接触区36b之前，在边缘区2a的开始处，限定穿过第二介电层15的单个开口15′，以接近下面的栅极层14。
然后，在图5G，该制造方法继续进行金属层(例如，铝硅铜合金(AlSiCu))的沉积，并且进行用于形成上述栅极接触焊盘18、源极金属化部16、以及栅极金属化部20的光刻定义。
这导致形成功率MOSFET器件100，如图5G以及上述图2A和图2B所示。
本方案的优点从前面的描述中显而易见。
在任何情况下，再次强调，该解决方案允许提高功率器件的效率、性能和可靠性，在一些实施例中，功率器件是从碳化硅衬底开始制造的MOSFET晶体管。
具体地，本解决方案允许获得与栅极接触串联的集成电阻器，该集成电阻器具有由注入的N型碳化硅的特性控制的非常精确且可控的电阻值。在一些实施例中，温度特性由非常稳定的物理特性控制。
这个电阻值还具有从管芯到管芯并且相对于制造批次的非常低的差异。
有利地，可以根据掺杂区32的几何形状来精确地调整电阻值；例如，这个掺杂区32可以不具有完全的环状构造，如图2A中所示，而是可以仅限于该环的一些部分。此外，如先前所指示的，这个电阻值可以通过在具有低或高掺杂剂浓度的区域中改变该掺杂区32的限制和绝缘布置来调整(以便分别具有低电阻值或高电阻值，如先前参考图3和图4的变体所强调的)。
有利地，本解决方案在制造过程中不需要额外的步骤，因为仅需要对标准类型的制造过程的步骤进行有限的修改。
此外，在没有下面的多晶硅的区域中将电栅极线17耦合至栅极接触焊盘18的可能性(从而限制栅极层14的缺陷)是有利的。
因此，根据本解决方案制造的所得的MOSFET晶体管器件可以有利地用于各种应用领域，诸如在具有功率因数校正(PFC)的电源和UPS中、在光伏系统、能量分配系统、工业发动机和电动车辆中。
最后，清楚的是，在不背离如在所附权利要求中定义的本公开的范围的情况下，可以对在本文中描述和示出的内容做出修改和变型。
在一些实施例中，要强调的是，本解决方案可以有利地用于不同的碳化硅MOSFET晶体管器件中，例如，VDMOS信号或功率器件、IGBT(包括MOSFET晶体管)、IP(智能功率)MOSFET器件，例如，对于汽车应用，通常用于N沟道和P沟道MOSFET晶体管两者中。
一种碳化硅功率器件(100)，可以被概括为包括碳化硅功能层(4)，包括边缘区(2a)和由边缘区(2a)包围的有源区(2b)；栅极结构(3′)，形成在有源区(2b)中的功能层(4)的顶表面(4a)上；以及栅极接触焊盘(18)，用于偏置栅极结构(3′)，其特征在于，还包括集成电阻器(30)，集成电阻器(30)包括布置在边缘区(2a)中的功能层(4)的前表面(4a)处的第一导电类型(N+)的掺杂区(32)，其中，所述集成电阻器(30)被配置为在功能层(4)中定义绝缘电阻，该绝缘电阻介于栅极接触焊盘(18)与栅极结构(3′)之间。
所述栅极接触焊盘(18)可以设置在所述边缘区(2a)处并通过相应的第一接触区(36a)电接触掺杂区(32)的第一端；此外可以包括栅极金属化部(20)，其可以被配置为接触有源区(2b)中的栅极结构(3’)并且通过相应的第二接触区(36b)电接触掺杂区(32)的第二端。
该器件可以在边缘区(2a)中包括边缘终止区(5)，该边缘终止区由具有第二导电类型(P)和第一掺杂水平的掺杂区构成、被布置在功能层(4)的顶表面(4a)附近。
所述掺杂区(32)可以被限制在绝缘阱(34)内，绝缘阱具有第二导电类型(P)和高于第一掺杂水平的第二掺杂水平；绝缘阱(34)被布置在边缘终止区(5)内。
掺杂区(32)可以被限制在边缘终止区(5)内。
该器件可以进一步包括：在有源区(2b)中，在功能层(4)内形成的具有第二导电类型的体阱(6)；其中，环形区(5)可以通过掺杂连接区(9)连接至相对于有源区(2b)更靠外并且靠近边缘区(2a)的体阱(6’)；掺杂连接区(9)具有所述第二导电类型和高于第一掺杂水平的第三掺杂水平；其中，所述掺杂区(32)可以被限制在掺杂连接区(9)内。
该器件可以包括外介电区(13、15)，该外介电区在边缘区(2a)处布置在功能层(4)的前表面(4a)上；其中，开口(13′)可与外介电区(13、15)交叉，并且所述第一接触区和第二接触区(36a、36b)可彼此电分离地布置在所述开口(13′)处。
所述栅极焊盘(18)的整个水平延伸部可以直接布置在外介电区(13，15)上。
该器件可以包括导电栅极层(14)，该导电栅极层连接到有源区(2b)中的栅极结构(3’)并且延伸到边缘区(2a)，在开口(13’)之前终止。
掺杂区(32)可以在平行于所述功能层(4)的所述前表面(4a)的水平面(xy)中具有围绕栅极焊盘(18)的环形延伸部。
该器件可以包括布置在所述有源区(2b)中的多个MOSFET晶体管基本单元(3)，每个基本单元可以包括所述栅极结构(3′)中的相应栅极结构，形成在功能层(4)内的具有第二导电类型的相应体阱(6)，以及形成在体阱(6)内，在相应栅极结构(3′)下方的具有所述第一导电类型的至少一个相应源极区(8)。
一种用于制造碳化硅功率器件(100)的工艺可以被概括为包括：形成碳化硅的功能层(4)，包括边缘区(2a)和由边缘区(2a)包围的有源区(2b)；在有源区(2b)中的功能层(4)的顶表面(4a)上形成栅极结构(3′)；形成用于偏置栅极结构(3′)的栅极接触焊盘(18)，其特征在于，进一步包括形成集成电阻器(30)，该集成电阻器包括布置在边缘区(2a)中的所述功能层(4)的前表面(4a)处的第一导电类型(N+)的掺杂区(32)，该集成电阻器(30)在功能层(4)中定义绝缘电阻，该绝缘电阻介于在所述栅极接触焊盘(18)与所述栅极结构(3′)之间。
形成集成电阻器(30)可以包括：执行第一导电类型(N+)的掺杂剂的注入以形成掺杂区(32)；以及在形成栅极结构(3’)之前对掺杂剂进行热激活。
该工艺可以包括在有源区(2b)中的功能层(4)内形成具有第二导电类型(P)和第一掺杂水平的体阱(6)，以及在所述体阱(6)内在相应的栅极结构(3′)下方形成具有第一导电类型的源极区(8)；其中，可以在同一掺杂剂注入步骤中形成掺杂区(32)和源极区(8)。
形成掺杂区(32)可以包括将掺杂区形成为使得其被限制在具有所述第二导电类型(P)的掺杂的绝缘阱(34)内；其中，绝缘阱(34)和体阱(6)可以在同一相应掺杂剂注入步骤中形成。
该工艺还可以包括：在边缘区(2a)中形成边缘终止区(5)，该边缘终止区由布置在功能层(4)的顶表面(4a)附近的，具有所述第二导电类型(P)和低于第一掺杂水平的第二掺杂水平的掺杂区构成。
形成掺杂区(32)可以包括将掺杂区形成为使得其被限制在边缘终止区(5)内。
该工艺还可以包括形成掺杂连接区(9)，该掺杂连接区具有第二导电性和高于第一掺杂水平的第三掺杂水平，用于将环形区(5)连接到相对于所述有源区(2b)更靠外并且靠近边缘区(2a)的体阱(6’)；其中，形成所述掺杂区(32)可以包括将所述掺杂区形成为使得其被限制在所述掺杂连接区(9)内。
该工艺可以包括在边缘区(2a)处形成栅极接触焊盘(18)；其中，形成栅极焊盘(18)可以包括通过相应的第一接触区(36a)电接触掺杂区(32)的第一端；此外可以包括形成栅极金属化部(20)，该栅极金属化部被配置为在有源区(2b)处接触栅极结构(3’)并且通过相应的第二接触区(36b)接触掺杂区(32)的第二端。
该工艺可以包括：在边缘区(2a)处在功能层(4)的前表面(4a)上形成外介电区(13，15)；以及形成穿过外介电区(13，15)的开口(13’)，第一接触区和第二接触区(36a，36b)彼此电分离地布置在所述开口(13’)处。
上述各个实施例可被组合以提供其他实施例。如果需要，可以修改实施例的方面以采用各种实施例的概念来提供另外的实施例。
鉴于以上详细描述，可以对实施例进行这些和其他改变。通常，在以下权利要求中，所使用的术语不应被解释为将权利要求限制于说明书和权利要求中所公开的具体实施例，而是应被解释为包括所有可能的实施例以及这些权利要求所赋予的等同物的全部范围。因此，权利要求书不受本公开的限制。

Claims (20)

1.一种碳化硅功率器件，包括：
碳化硅层，包括边缘区和由所述边缘区包围的有源区；
栅极结构，形成在所述有源区中的所述碳化硅层的第一表面上；
电阻器，包括布置在所述边缘区中的所述碳化硅层的所述第一表面处的第一导电类型的第一掺杂区；
栅极接触焊盘，被配置为偏置所述栅极结构，
其中所述电阻器位于所述栅极接触焊盘与所述栅极结构之间。
2.根据权利要求1所述的器件，其中所述栅极接触焊盘被布置在所述边缘区处并且通过第一接触区电接触所述第一掺杂区的第一端；并且
所述器件进一步包括与所述有源区中的所述栅极结构电接触的栅极金属化部，所述栅极金属化部通过第二接触区与所述第一掺杂区的第二端接触。
3.根据权利要求2所述的器件，包括在所述边缘区中的边缘终止区，所述边缘终止区包括在所述碳化硅层的所述第一表面附近的具有第二导电类型和第一掺杂水平的第二掺杂区。
4.根据权利要求3所述的器件，其中所述第一掺杂区被限定在绝缘阱内，所述绝缘阱具有所述第二导电类型和高于所述第一掺杂水平的第二掺杂水平，所述绝缘阱在所述边缘终止区内。
5.根据权利要求3所述的器件，其中所述第一掺杂区位于所述边缘终止区内。
6.根据权利要求3所述的器件，进一步包括：在所述有源区中，形成在所述碳化硅层内的具有所述第二导电类型的体阱；以及
第三掺杂区，位于所述边缘终止区和所述体阱中的相对于所述有源区更靠外并且靠近所述边缘区的体阱中的每个之间，并且邻接所述边缘终止区和所述体阱中的相对于所述有源区更靠外并且靠近所述边缘区的体阱中的每个，所述第三掺杂区具有所述第二导电类型和高于所述第一掺杂水平的第三掺杂水平，
其中所述第一掺杂区被限定在所述第三掺杂区内。
7.根据权利要求2所述的器件，包括：
外介电区，布置在所述碳化硅层的所述第一表面上，在所述边缘区处；以及
开口，垂直穿过所述外介电区，
其中所述第一接触区和所述第二接触区被布置在所述开口中，并且所述第一接触区和所述第二接触区被彼此电分离。
8.根据权利要求7所述的器件，其中所述栅极焊盘直接位于所述外介电区上，与所述外介电区的整个水平延伸部重叠。
9.根据权利要求7所述的器件，包括导电栅极层，所述导电栅极层连接至所述有源区中的所述栅极结构并且延伸至所述边缘区，并且在所述开口之前终止。
10.根据权利要求2所述的器件，其中所述第一掺杂区具有在平行于所述碳化硅层的所述第一表面的水平面中围绕所述栅极焊盘的环形延伸部。
11.根据权利要求1所述的器件，包括在所述有源区中的MOSFET晶体管基本单元，所述MOSFET晶体管基本单元包括所述栅极结构、在所述碳化硅层内形成的具有第二导电类型的体阱、以及在所述栅极结构下方、在所述体阱内形成的具有所述第一导电类型的源极区。
12.一种制造碳化硅功率器件的方法，包括：
形成碳化硅层，所述碳化硅层包括边缘区和由所述边缘区包围的有源区；
在所述有源区中的所述碳化硅层的第一表面上形成栅极结构；
形成栅极接触焊盘，所述栅极接触焊盘被配置为偏置所述栅极结构；以及
在所述边缘区中的所述碳化硅层的所述第一表面处并且在所述栅极接触焊盘与所述栅极结构之间形成包括第一导电类型的掺杂区的电阻器。
13.根据权利要求12所述的方法，其中形成所述电阻器包括：
执行所述第一导电类型的掺杂剂的注入，以形成所述掺杂区；以及
在形成所述栅极结构之前，对所述掺杂剂进行热激活。
14.根据权利要求12所述的方法，包括：
在所述有源区中的所述碳化硅层内形成具有第二导电类型和第一掺杂水平的体阱；以及
在所述体阱内并且在相应的栅极结构下方形成具有所述第一导电类型的源极区，
其中所述掺杂区和所述源极区在同一掺杂剂注入步骤中被形成。
15.根据权利要求14所述的方法，其中形成所述掺杂区包括：在具有所述第二导电类型的掺杂剂的绝缘阱内形成所述掺杂区，其中所述绝缘阱和所述体阱在同一掺杂剂注入工艺中被形成。
16.根据权利要求14所述的方法，进一步包括在所述边缘区中形成边缘终止区，所述边缘终止区包括所述第二导电类型的、低于所述第一掺杂水平的第二掺杂水平的、并且靠近所述碳化硅层的所述第一表面的掺杂剂。
17.根据权利要求16所述的方法，其中形成所述掺杂区包括在所述边缘终止区内形成所述掺杂区。
18.根据权利要求16所述的方法，进一步包括形成掺杂连接区，所述掺杂连接区具有所述第二导电性和高于所述第一掺杂水平的第三掺杂水平，所述掺杂连接区域邻接所述边缘终止区以及所述体阱中的被定位成相对于所述有源区更靠外并且靠近所述边缘区的体阱，
其中形成所述掺杂区包括在所述掺杂连接区内形成所述掺杂区。
19.一种碳化硅功率器件，包括：
碳化硅层，包括有源区和在所述有源区外围的边缘区；
晶体管，在所述有源区中，所述晶体管包括在所述有源区中的所述碳化硅层的第一表面上的栅极结构；
电阻器，在所述边缘区中，所述电阻器包括与所述碳化硅层的所述第一表面相邻的第一导电类型的掺杂区；以及
栅极接触焊盘，所述电阻器耦合在所述栅极接触焊盘与所述栅极结构之间。
20.根据权利要求19所述的器件，包括：
第一接触结构，耦合在所述掺杂区与所述栅极结构之间；
第二接触结构，耦合在所述掺杂区与所述栅极接触焊盘之间；以及
介电层，将所述第一接触结构与所述第二接触结构彼此分离，
其中所述第一接触结构、所述第二接触结构和所述介电层中的每个在所述掺杂区之上延伸。
CN202211183677.4A 2021-09-28 2022-09-27 具有集成电阻的碳化硅功率器件以及相应的制造工艺 Pending CN115881670A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
IT102021000024752A IT202100024752A1 (it) 2021-09-28 2021-09-28 Dispositivo di potenza in carburo di silicio con resistenza integrata e relativo procedimento di fabbricazione
IT102021000024752 2021-09-28
US17/945,530 2022-09-15
US17/945,530 US20230097579A1 (en) 2021-09-28 2022-09-15 Silicon carbide power device with integrated resistance and corresponding manufacturing process

Publications (1)

Publication Number Publication Date
CN115881670A true CN115881670A (zh) 2023-03-31

Family

ID=78771077

Family Applications (2)

Application Number Title Priority Date Filing Date
CN202222562704.0U Active CN219513096U (zh) 2021-09-28 2022-09-27 碳化硅功率器件
CN202211183677.4A Pending CN115881670A (zh) 2021-09-28 2022-09-27 具有集成电阻的碳化硅功率器件以及相应的制造工艺

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN202222562704.0U Active CN219513096U (zh) 2021-09-28 2022-09-27 碳化硅功率器件

Country Status (5)

Country Link
US (1) US20230097579A1 (zh)
EP (1) EP4156241A1 (zh)
JP (1) JP2023049005A (zh)
CN (2) CN219513096U (zh)
IT (1) IT202100024752A1 (zh)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5385855A (en) * 1994-02-24 1995-01-31 General Electric Company Fabrication of silicon carbide integrated circuits
US8530904B2 (en) * 2010-03-19 2013-09-10 Infineon Technologies Austria Ag Semiconductor device including a normally-on transistor and a normally-off transistor
WO2014133138A1 (ja) * 2013-03-01 2014-09-04 富士電機株式会社 半導体装置
CN111466032B (zh) * 2017-12-19 2023-08-18 三菱电机株式会社 碳化硅半导体装置以及电力变换装置
DE102018108561B3 (de) * 2018-04-11 2019-08-14 Infineon Technologies Austria Ag Transistorbauelement mit gate-widerstand

Also Published As

Publication number Publication date
IT202100024752A1 (it) 2023-03-28
CN219513096U (zh) 2023-08-11
US20230097579A1 (en) 2023-03-30
JP2023049005A (ja) 2023-04-07
EP4156241A1 (en) 2023-03-29

Similar Documents

Publication Publication Date Title
TW478155B (en) Lateral thin-film silicon-on-insulator (SOI) JFET device
US11270993B2 (en) MOSFET device of silicon carbide having an integrated diode and manufacturing process thereof
US11721738B2 (en) Laterally diffused metal oxide semiconductor with gate poly contact within source window
KR101232662B1 (ko) 반도체 디바이스를 형성하는 방법 및 그의 구조
JPH09246552A (ja) 重畳されたフィールドプレート構造を有する電力半導体装置およびその製造方法
US20190229212A1 (en) LDMOS Transistor And Method For Manufacturing The Same
CN108701713A (zh) 在垂直功率半导体装置中的源极－栅极区域架构
US11276784B2 (en) Semiconductor device
JP2008294028A (ja) 半導体装置
EP1081768A2 (en) Insulated gate field-effect transistor and method of making the same
US9887187B2 (en) Semiconductor device for preventing field inversion
JP6771433B2 (ja) 半導体装置
CN219513096U (zh) 碳化硅功率器件
CN113990945B (zh) 一种绝缘栅双极型晶体管结构及其制造方法
JP4682501B2 (ja) 絶縁ゲート型半導体素子およびこれを備えた半導体集積回路装置
WO2021260853A1 (ja) 炭化珪素半導体装置
CN116601773A (zh) 用于半导体装置的边缘终止结构
US7683454B2 (en) MOS power component with a reduced surface area
JPH10189983A (ja) 半導体装置及びその製造方法
CN217239468U (zh) Mosfet装置和电子装置
JP2018011089A (ja) 半導体装置
TWI835594B (zh) 半導體裝置
EP4036957A1 (en) Silicon carbide vertical conduction mosfet device for power applications and manufacturing process thereof
JP2004152806A (ja) 絶縁ゲート型半導体素子及び絶縁ゲート型半導体素子の製造方法
JPH11307768A (ja) 炭化珪素半導体装置及びその製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination