CN115485830A - 包括衬底、集成器件、和具有底切的封装层的封装 - Google Patents

包括衬底、集成器件、和具有底切的封装层的封装 Download PDF

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Publication number
CN115485830A
CN115485830A CN202180032298.2A CN202180032298A CN115485830A CN 115485830 A CN115485830 A CN 115485830A CN 202180032298 A CN202180032298 A CN 202180032298A CN 115485830 A CN115485830 A CN 115485830A
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Prior art keywords
substrate
integrated device
encapsulation layer
package
undercut
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CN202180032298.2A
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Inventor
A·J·泰谢拉·德奎伊罗斯
A·弗朗茨
A·K·克雷弗特
C·赖特林格
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Qualcomm Inc
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Qualcomm Inc
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Publication of CN115485830A publication Critical patent/CN115485830A/zh
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Abstract

一种封装，包括：衬底、集成器件、第一封装层和空隙。该衬底包括第一表面。集成器件被耦合到衬底的第一表面。第一封装层位于衬底的第一表面和集成器件之上。第一封装层包括相对于集成器件的侧表面的底切。空隙位于集成器件和衬底的第一表面之间。空隙被封装层的底切横向地包围。

Description

包括衬底、集成器件、和具有底切的封装层的封装
相关申请的交叉引用
本申请要求2020年10月8日在美国专利和商标局提交的第17/066,049号非临时申请和2020年5月29日在美国专利和商标局提交的第63/032,177号临时申请的优先权和利益，这些申请的内容在此通过引用明确并入本文，就像其全部内容和所有适用目的在下文中完全列出。
技术领域
各种特征涉及包括衬底和集成器件的封装，但是更具体地涉及包括衬底、集成器件和封装层的封装。
背景技术
图1图示了包括衬底102和集成器件104的封装100。集成器件104通过多个焊接互连件140而被耦合到衬底102的第一表面。衬底102包括至少一个电介质层120、多个互连件121、第一阻焊层124和第二阻焊层126。多个焊接互连件130被耦合到衬底102的第二表面。封装100还包括封装集成器件104的封装层160。形成封装层160的过程可以使封装层160的至少一部分在集成器件104的下方流动，并形成在集成器件104和衬底102之间。对于某些类型的集成器件，在集成器件104和衬底102之间具有封装层160可能限制和/或损害了集成器件104和/或封装100的性能。
持续需要改善封装和位于封装中的集成器件的性能。
发明内容
各种特征涉及包括衬底和集成器件的封装，但是更具体地涉及包括衬底、集成器件和封装层的封装。
一个示例提供了一种封装，包括：衬底、集成器件、第一封装层和空隙。该衬底包括第一表面。集成器件被耦合到衬底的第一表面。第一封装层位于衬底的第一表面和集成器件之上。第一封装层包括相对于集成器件的侧表面的底切。空隙位于集成器件和衬底的第一表面之间。空隙被封装层的底切横向地包围。
另一个示例提供了一种装置，包括：衬底、集成器件、用于第一封装的部件和空隙。该衬底包括第一表面。集成器件被耦合到衬底的第一表面。用于第一封装的部件位于衬底的第一表面和集成器件之上。用于第一封装的部件包括相对于集成器件的侧表面的底切。空隙位于集成器件和衬底的第一表面之间。空隙被用于第一封装的部件的底切横向地包围。
另一个示例提供了一种用于制造封装的方法。该方法提供了包括第一表面的衬底。该方法将集成器件耦合到衬底的第一表面。该方法在衬底和集成器件的第一表面之上形成第一封装层。第一封装层包括相对于集成器件的侧表面的底切。形成第一封装层形成位于集成器件和衬底第一表面之间的空隙，其中空隙被第一封装层的底切横向地包围。
附图说明
各种特征、性质和优点从结合附图在下面阐述的详细描述中变得显而易见，其中类似的参考字符在整个附图中相应地进行标识。
图1图示了包括衬底和集成器件的封装的剖视图。
图2图示了包括衬底、集成器件和具有受控底切的封装层的封装的剖视图。
图3图示了包括衬底、集成器件和具有受控底切的封装层的封装的剖视图。
图4图示了包括衬底、集成器件和具有受控底切的封装层的封装的特写视图。
图5图示了包括衬底、集成器件和具有受控底切的封装层的另一封装的剖视图。
图6图示了包括衬底、集成器件和具有受控底切的封装层的另一封装的剖视图。
图7图示了包括衬底、集成器件和具有受控底切的封装层的另一封装的剖视图。
图8图示了包括衬底、集成器件和具有受控底切的封装层的另一封装的剖视图。
图9图示了包括衬底、集成器件和具有受控底切的封装层的另一封装的剖视图。
图10图示了包括衬底、集成器件和具有受控底切的封装层的另一封装的剖视图。
图11图示了包括衬底、堆叠器件和具有受控底切的封装层的另一封装的剖视图。
图12图示了包括衬底、堆叠器件和具有受控底切的封装层的另一封装的剖视图。
图13A-图13D图示了用于制造包括框架的裸片的示例性序列。
图14图示了用于制造包括衬底、集成器件和具有受控底切的封装层的封装的方法的示例性流程图。
图15A-图15C图示了用于制造衬底的示例性序列。
图16A-图16B图示了用于制造包括堆叠集成器件的器件的示例性序列。
图17A-图17B图示了用于制造包括堆叠集成器件的器件的示例性序列。
图18图示了可以集成本文所述的裸片、集成器件、集成无源器件(IPD)、无源组件、封装和/或器件封装的各种电子设备。
具体实施方式
在以下描述中，给出了具体细节以提供对本公开的各个方面的透彻理解。然而，本领域的普通技术人员将理解，各方面可以在没有这些具体细节的情况下进行实践。例如，电路可以用框图来示出，以避免不必要的细节模糊各方面。在其他实例中，众所周知的电路、结构和技术可以未被详细示出，以避免模糊本公开的各方面。
本公开描述了一种封装，其包括衬底、集成器件、第一封装层和空隙。该衬底包括第一表面。集成器件被耦合到衬底的第一表面。第一封装层位于衬底的第一表面和集成器件之上。第一封装层包括相对于集成器件的侧表面的底切。第一封装层在集成器件的顶表面和侧表面之上可以具有均匀的厚度。空隙位于集成器件和衬底的第一表面之间。空隙被第一封装层的底切横向地包围。第二封装层可以被形成并位于第一封装层之上。该封装可以在集成器件和第一封装层之间没有箔(例如，胶箔、胶水箔)和/或密封膜，这有助于降低封装的制造成本。使用第一封装层和第二封装层可以帮助提供具有可控底切的封装层的封装，这可以更准确和更精确地控制集成器件和衬底之间的空隙。集成器件可以被配置作为过滤器。此外，可以选择被用于衬底和(多个)封装层的材料，以使得衬底和封装的其余部分之间的热膨胀系数(CTE)失配被最小化，从而提供更坚固和可靠的封装。
包括衬底、集成器件和具有可控底切的封装层的示例性封装
图2图示了封装200的剖视图，该封装200包括衬底202、集成器件204、集成器件206、封装层207、封装层209和电磁干扰(EMI)屏蔽件250。在一些实现中，封装200可以是集成电路(IC)封装，诸如系统封装(SiP)或芯片级封装(CSP)。在一些实现中，封装200可以被配置作为包括射频(RF)过滤器的射频前端(RFFE)封装。
衬底202包括至少一个电介质层220、多个互连件221(例如，迹线、焊盘、通孔)、阻焊层224和阻焊层226。阻焊层224可以形成并位于至少一个电介质层220的第一表面之上。阻焊层226可以形成并位于至少一个电介质层220的第二表面之上。衬底202可以是无芯衬底、层状衬底或包括芯层的衬底。至少一个电介质层220可以包括不同的材料，诸如预浸料层、聚酰亚胺(例如，可光蚀的电介质层)、有机层和/或陶瓷。多个焊接互连件230通过衬底202的第二表面(例如，底面)而被耦合到多个互连件221。
集成器件204通过多个焊接互连件240而被耦合到衬底202的第一表面(例如，顶表面)。空隙242位于集成器件204和衬底202的第一表面之间。集成器件206通过多个焊接互连件260而被耦合到衬底202的第一表面(例如，顶表面)。空隙262位于集成器件206和衬底202的第一表面之间。空隙(例如，242、262)可以是没有固体材料的至少一个区域。空隙可以包括腔体。空隙可以被气体(例如，空气)占据。
集成器件(例如，204、206)可以包括裸片(例如，半导体裸片)。集成器件可以包括射频(RF)器件、无源器件、过滤器、电容器、电感器、天线、发射器、接收器、表面声波(SAW)过滤器、体声波(BAW)过滤器、发光二极管(LED)集成器件、基于碳化硅(SiC)的集成器件、基于GaAs的集成器件、基于GaN的集成器件、处理器、存储器和/或其组合。集成器件(例如，204、206)可以包括至少一个电子电路(例如，第一电子电路、第二电子电路等...)。
例如，当集成器件(例如，204、206)被配置作为半导体集成电路裸片时，集成器件可以包括衬底和器件层，该器件层包括被配置为执行操作(例如，逻辑操作)的晶体管。在另一个示例中，当集成器件(例如，204、206)被配置作为裸片过滤器(例如，SAW过滤器、BAW过滤器)时，集成器件可以包括压电衬底和形成并位于压电衬底之上的至少一个金属层，该至少一个金属层被配置作为至少一个换能器(例如，数字间换能器(IDT))。下面至少在图11、图12、图16A-图16B和图17A-图17B中进一步图示和描述了裸片过滤器的示例。当集成器件被配置作为过滤器时，集成器件和衬底之间的空隙可有助于提高被配置作为过滤器的集成器件的性能。
图2图示了封装层207被耦合到、形成并位于衬底202的第一表面、集成器件204和集成器件206之上，以使得(i)空隙242位于集成器件204和衬底202之间，以及(ii)空隙262位于集成器件206和衬底202之间。图2图示了封装层207与集成器件的侧壁或侧表面有一个中性底切。封装层的底切描述(和/或量化)封装层(或封装层的一部分)相对于组件(例如，集成器件)下方的空隙以及相对于另一个参考点(例如，与集成器件的侧壁或侧表面对齐的垂直线)的位置。封装层的底切可以描述和/或量化封装层位于集成器件下方的空隙中多远，或者封装层离集成器件下方的空隙多远。中性底切可能意味着封装层207可以与位于空隙之上的集成器件(例如，204、206)的侧壁或侧表面垂直对齐。然而，正如下文将至少在图3和图4中进一步描述的那样，封装层207可以与集成器件具有一个正底切或负底切。封装层的底切值可以在大约-20微米(μm)和50微米(μm)之间的范围。负的底切值可能意味着封装层被定位成远离集成器件并远离从集成器件的侧表面或侧壁垂直延伸的假想线(或基准)。正的底切值可能意味着封装层位于集成器件下方，朝向集成器件下方的空隙，并远离从位于空隙之上的集成器件的侧表面或侧壁垂直延伸的假想线。然而，正底切和负底切可以被不同地定义。底切值可以表示最大底切值(例如，离假想线(或基准)多远是封装层的最远部分)。对于具有多个侧面的集成器件，集成器件的每个侧面可能都有对应的底切。也就是说，针对集成器件的每一侧面，封装层都可以有一个底切值。集成器件的每一侧面的底切值可以是不同的，也可以是相同的。在一些实现中，对于集成器件的至少一个侧面可以具有可变底切值。
如图2中所示，在相应集成器件下方的每个空隙被相应集成器件所定义的封装层207的相应底切横向地包围。例如，空隙242被集成器件204的侧表面所定义的封装层207的至少一个底切横向地包围。类似地，空隙262被集成器件206的侧表面所定义的封装层207的至少一个底切横向地包围。
本公开描述了一种封装，其在位于集成器件和衬底之间的至少一个空隙附近具有针对封装层的准确和精确控制的底切，这可能导致来自集成器件和/或封装的更好的性能，因为集成器件和衬底之间的区域不被封装层所阻挡。
封装层207可以是第一封装层(例如，用于第一封装的部件)。封装层207可以包括模具、树脂和/或环氧树脂。封装层207可以包括各向同性的材料和/或各向异性的材料。正如下文将进一步描述的那样，可以使用片状成型过程(例如，真空层压、压缩成型)来形成封装层207。
封装层207在衬底202、集成器件204和集成器件206之上形成，以使得封装层207具有大致均匀的厚度，因为封装层207大致跟随衬底202、集成器件204和/或集成器件206的轮廓。第一封装层207可以在集成器件204的顶表面和/或侧表面之上具有均匀的厚度，和/或在集成器件206的顶表面和/或侧表面之上具有均匀的厚度。在一些实现中，第一封装层207在(多个)集成器件204和/或207的侧表面之上的厚度可以比在(多个)集成器件204和/或207的顶表面之上的厚度薄。需要注意的是，均匀的厚度并不一定意味着封装层在任何地方都有完全相同的厚度。在本公开中使用的均匀的厚度意指组件(例如，封装层)的厚度在一定的公差内大致相同。例如，均匀的厚度可以意指在材料的平均厚度的某一百分比内，厚度是相同的。例如，如果封装层207具有平均厚度(Tavg)，那么如果在封装层207的任何部分处的厚度在封装层207的平均厚度(Tavg)的10％或更少(例如，5％或更少)，则可以认为封装层207具有均匀的厚度。在另一个示例中，当组件(例如，封装层)的最厚部分和组件(例如，封装层)的最薄部分之间的差异为16微米(μm)或更少时，组件(例如，封装层)可以具有均匀的厚度。在一些实现中，封装层207可以具有大约80微米(μm)±8微米(μm)的厚度。然而，不同的实现可以使用具有不同的均匀的厚度的封装层207。封装层207的均匀的厚度可以适用于封装层207的接触组件(例如，集成器件、衬底)的表面的各部分。在一些实现中，封装层207的均匀性可能不适用于封装层207的与空隙相邻的各部分。片状成型过程可以允许在位于空隙之上的集成器件附近的封装层207的底切得到准确和精确的控制，这进而又允许集成器件和衬底之间的空隙(例如，242、262)得到准确和精确的控制。
可以在不需要跟随衬底202、集成器件204和集成器件206的轮廓的箔和/或密封膜的情况下提供和形成封装层207。这可以通过使用具有低粘度值的封装层207的片状模具来实现，以使得封装层207基本上不会在(多个)集成器件下方流动。例如，对于60℃-140℃的温度范围，封装层207的粘度值可以在0.01-100mPa·s(毫帕秒)之间。因此，图2和本公开的其他图图示了一种在封装层207和衬底202、集成器件204和集成器件206之间没有密封膜的封装。无箔封装或无密封膜封装的一个优点是，由于这至少少了一个步骤以及至少少了一种材料，所以封装的制造成本更低。
封装层209被耦合到、形成并位于封装层207之上。封装层209可以是第二封装层(例如，用于第二封装的部件)。封装层209可以包括模具、树脂和/或环氧树脂。封装层209可以包括各向同性的材料和/或各向异性的材料。封装层209可以包括与封装层207不同的材料。封装层209可以具有至少一个与封装层207不同的性质。例如，封装层209可以具有与封装层207不同的热膨胀系数(CTE)。在一些实现中，封装层209可以具有比封装层207的CTE高/大的CTE(例如，33百万分率(ppm))。在一些实现中，封装层209可以具有比封装层207的CTE小/低的CTE。可以使用压缩成型过程、转移成型过程或液体成型过程来形成封装层209。封装层209可以是光蚀刻的。在封装层209和封装层207之间可以具有边界界面。此外，除了成型过程外，封装层209还可以与封装层207层压在一起，形成一个单片。这个包括封装层207和封装层209的单片可以经由真空层压或压缩成型而被施加到衬底202、集成器件204和集成器件206上。
EMI屏蔽件250可以被耦合到、形成并位于封装层209和衬底202的侧部分之上。EMI屏蔽件250可以包括导电层。EMI屏蔽件250可以被配置为耦合到地。例如，EMI屏蔽件250可以被配置为与接地互连件(例如，来自衬底202的接地互连件)电耦合。EMI屏蔽件250可以是用于电磁干扰(EMI)屏蔽的部件。
为了增加和改善封装200(或本公开中描述的任何封装)的可靠性，可以选择封装200的各种组件的设计，以使得衬底202和封装200的其余部分之间的最大CTE失配为15百万分率/开尔文(ppm/K)或更少。例如，衬底202的有效CTE(例如，衬底CTE)与(多个)集成器件(例如，204、206)、耦合(多个)集成器件的焊接互连件(例如，240、260)、封装层207、封装层209和/或EMI屏蔽件250的有效和集体CTE之间的最大差异可以是大约15ppm/K或更少。因此，衬底202可以具有在封装200的其余部分的有效CTE的大约15ppm/K内的衬底CTE。衬底202的衬底CTE可以表示至少一个电介质层220、多个互连件221、阻焊层224和/或阻焊层226的有效和集体CTE。在一些实现中，衬底202的衬底CTE可以在大约5-20百万分率/开尔文(ppm/K)的范围内。
图3图示了包括封装层的封装300，该封装层包括正底切和负底切。封装300与图2的封装200相似，并且包括与封装200相似或相同的组件。图3图示了封装层207包括正底切304和负底切306。图4图示了封装300的特写视图。如图4中所示，封装层207可以被形成为使得封装层207相对于集成器件204和空隙242具有正底切304，相对于集成器件206和空隙262具有负底切。然而，需要注意的是，封装层207可以与集成器件具有正底切、中性底切和/或负底切。例如，封装层207可以与集成器件的一侧具有正底切，而与集成器件的另一侧具有负底切。在一些实现中，封装层207可以与集成器件具有可变底切。在一些实现中，封装层207的一侧可以具有正底切、中性底切和/或负底切。如上面所提及的，位于空隙之上的集成器件附近的封装层207的底切值可以在-20-50微米(μm)的范围内(例如，负20微米和正50微米之间的范围)。因此，封装层207可以与至少一个集成器件(例如，204、206)具有负底切、中性底切、正底切或其组合。底切值可以表示最大底切值(例如，离假想线多远是封装层的最远部分)。封装层207的至少一部分可以具有均匀的厚度，如图2中所述。
图5图示了包括具有各种底切的封装层的封装500。该封装500类似于图3的封装300，并且包括与封装300类似或相同的组件。封装500还包括集成器件506、封装层509、以及多个焊接互连件560。集成器件506通过多个焊接互连件560而被耦合到衬底202的第二表面(例如，底表面)。封装层509位于衬底202的第二表面之上并与之耦合。封装层509封装集成器件506和多个焊接互连件230的各部分。封装层509可以类似于封装层207和/或封装层209。封装层509可以是第三封装层(例如，用于第三封装的部件)。封装层509可以包括模具、树脂和/或环氧树脂。可以使用压缩成型过程、转移成型过程或液体成型过程来形成封装层509。封装层509可以是光蚀刻的。
集成器件506、封装层509、多个焊接互连件560和多个焊接互连件230的有效集体CTE可以被选择，以使得与衬底202的最大CTE失配为15ppm/K或更少。封装层207的至少一部分可以具有均匀的厚度，如图2中所述。
图6图示了包括封装层的封装600，该封装层包括各种底切。封装600类似于图5的封装500，并且包括与封装500类似或相同的组件。封装600还包括集成器件606、空隙662和包括腔体的衬底202。空隙662位于集成器件206和衬底202之间。空隙662可以包括位于衬底202中的腔体。集成器件606位于衬底202的腔体中。集成器件606通过多个焊接互连件660而被耦合到衬底202。集成器件606的背面面向集成器件206的正面。与本公开中的其他封装类似，对于位于空隙之上的各种集成器件，封装层207可以具有在-20-50微米(μm)范围内的底切值。对于空隙之上的集成器件(例如，204、206)，封装层207的(多个)底切值可以是可变的。封装层207的至少一部分可以具有均匀的厚度，如图2中所述。
图7图示了包括封装层的封装700，该封装层包括各种底层。封装700类似于图6的封装600，并且包括与封装600类似或相同的组件。封装700包括集成器件706、集成器件606、空隙662和包括腔体的衬底202。集成器件706位于空隙662中。集成器件706被耦合到集成器件206(例如，以正面对正面的配置)。集成器件606的背面面向集成器件706的背面。与本公开中的其他封装类似，对于位于空隙之上的各种集成器件，封装层207可以具有在-20-50微米(μm)范围内的底切值。针对集成器件的封装层207的(多个)底切值可以是可变的。封装层207的至少一部分可以具有均匀的厚度，如图2中所述。
图8图示了包括封装层的封装800，该封装层包括各种底切。封装800类似于图6的封装600，并且包括与封装600类似或相同的组件。封装800包括无源器件806、空隙662和包括腔体的衬底202。空隙662位于集成器件206和衬底202之间。空隙662可以包括位于衬底202中的腔体。无源器件806位于衬底202的腔体中。无源器件806通过多个焊接互连件660而被耦合到衬底202。无源器件806可以是电容器(例如，表面安装的电容器)。与本公开的其他封装类似，对于位于空隙之上的各种集成器件，封装层207可以具有在-20-50微米(μm)范围内的底切值。针对集成器件的封装层207的(多个)底切值可以是可变的。封装层207的至少一部分可以具有均匀的厚度，如图2中所述。
图9图示了包括封装层的封装900，该封装层包括各种底切。封装900类似于图6的封装600，并且包括与封装600类似或相同的组件。封装900包括集成器件906、集成器件606、空隙662和包括腔体的衬底202。集成器件906位于空隙662中。集成器件906通过多个焊接互连件960而被耦合到集成器件606(例如，以正面对背面的配置)。集成器件906的背面面向集成器件206的正面。与本公开中的其他封装类似，对于位于空隙之上的各种集成器件，封装层207可以具有在-20-50微米(μm)范围内的底切值。针对集成器件的封装层207的(多个)底切值可以是可变的。封装层207的至少一部分可以具有均匀的厚度，如图2中所述。
图10图示了包括封装层的封装1000，该封装层包括各种底切。封装1000类似于图6的封装600，并且包括与封装600类似或相同的组件。封装1000包括集成器件1006、空隙662和包括腔体的衬底202。集成器件1006位于空隙662中。集成器件1006通过多个焊接互连件1060而被耦合到集成器件206(例如，以正面对正面的配置)。集成器件1006的背面通过粘合剂1005而被耦合到衬底202。与本公开中的其他封装类似，对于位于空隙之上的各种集成器件，封装层207可以具有在-20-50微米(μm)范围内的底切值。针对集成器件的封装层207的底切值可以是可变的。封装层207的至少一部分可以具有均匀的厚度，如图2中所述。
图11图示了包括封装层的封装1100，该封装层包括各种底切。封装1100类似于图6的封装600，并且包括与封装600类似或相同的组件。封装1100包括堆叠器件1104、空隙1162和包括腔体的衬底202。堆叠器件1104可以包括堆叠的过滤器。堆叠器件1104包括被配置作为第一过滤器(例如，第一信号过滤部件)的第一集成器件1114、被配置作为第二过滤器(例如，第二信号过滤部件)的第二集成器件1116、聚合物框架1118和多个互连件1119。第一集成器件1114可以是顶部过滤器，第二集成器件1116可以是底部过滤器。第一集成器件1114被耦合到聚合物框架1118的第一表面。第二集成器件1116被耦合到聚合物框架1118的第二表面。空隙1120可以位于第一集成器件1114、第二集成器件1116和聚合物框架1118之间。多个互连件1119可以位于第一集成器件1114、聚合物框架1118和第二集成器件1116的表面之上。堆叠器件1104通过多个焊接互连件1140而被耦合到衬底202。堆叠器件1104的至少一部分位于衬底202的腔体中。空隙1162包括衬底202的腔体。
在衬底202、集成器件204和堆叠器件1104之上形成封装层207，以使得封装层207具有大致均匀的厚度，因为封装层207大致跟随衬底202、集成器件204和堆叠器件1104的轮廓。第一封装层207可以在堆叠器件1104的顶表面和侧表面之上具有均匀的厚度，和/或在集成器件1114的顶表面和侧表面之上具有均匀的厚度。封装层207可以具有大约80微米(μm)±8微米(μm)的厚度。堆叠器件1104的封装层207的底切可以相对于第一集成器件1114的侧表面或侧壁来定义。与本公开的其他封装类似，对于位于空隙之上的各种器件，封装层207可以具有在-20-50微米(μm)范围内的底切值。针对集成器件和/或堆叠器件的封装层207的(多个)底切值可以是可变的。封装层207的至少一部分可以具有均匀的厚度，如图2中所述。
图12图示了包括封装层的封装1200，该封装层包括各种底切。封装1200类似于图11的封装1100，并且包括与封装1100类似或相同的组件。封装1200包括堆叠器件1204、空隙1162和包括腔体的衬底202。堆叠器件1204可以包括叠加的过滤器。堆叠器件1204包括被配置作为第一过滤器(例如，用于第一信号过滤的部件)的第一集成器件1114、被配置作为第二过滤器(例如，用于第二信号过滤的部件)的第二集成器件1116、互连框架1218和多个互连件1219。第一集成器件1114可以是顶部过滤器，第二集成器件1116可以是底部过滤器。第一集成器件1114被耦合到互连框架1218。第二集成器件1116被耦合到互连框架1218。空隙1120可以位于第一集成器件1114、第二集成器件1116和互连框架1218之间。多个互连件1219可以位于第二集成器件1116中以及之上。多个互连件1219可以包括通孔、导线和/或焊盘。堆叠器件1204通过多个焊接互连件1140而被耦合到衬底202。堆叠器件1124的至少一部分位于衬底202的腔体中。空隙1162包括衬底202的腔体。
在衬底202、集成器件204和堆叠器件1204之上形成封装层207，以使得封装层207具有大致均匀的厚度，因为封装层207大致跟随衬底202、集成器件204和堆叠器件1204的轮廓。第一封装层207可以在堆叠器件1204的顶表面和侧表面之上具有均匀的厚度，和/或在集成器件1114的顶表面和侧表面之上具有均匀的厚度。封装层207可以具有大约80微米(μm)±8微米(μm)的厚度。堆叠器件1204的封装层207的底切可以相对于第一集成器件1114的侧表面或侧壁来定义。与本公开的其他封装类似，对于位于空隙之上的各种器件，封装层207可以具有在-20-50微米(μm)范围内的底切值。针对集成器件和/或堆叠器件的封装层207的(多个)底切值可以是可变的。封装层207的至少一部分可以具有均匀的厚度，如图2中所述。
应注意，一个封装中的各种特征可以在本公开中描述的任何封装中被实现。所示出的用于封装层的底切是示例性的。封装的不同实现可以包括具有不同和/或变化的底切的封装层，包括正底切、负底切、中性底切或其组合。底切值的范围是示例性的。不同的实现可以具有不同数值的底切。围绕集成器件的封装层可以针对集成器件的不同侧面具有相同或不同的底切值。本公开中图示和描述的任何集成器件和/或器件可以被至少一个封装层所包围，以使得集成器件和/或器件的所有侧面可以被至少一个封装层所包围。集成器件和/或器件的所有侧面可以被封装层包围，以使得对于集成器件和/或器件的每个特定侧面，封装层可以具有在-20-50微米(μm)范围内的特定底切值。
本公开中所示的封装的各种配置可以提供不同的技术优势，包括较低的制造成本、改进的可靠性(例如，通过更好的CTE失配)以及改进的性能(例如，通过减少组件之间的布线路径、更好定义的空隙)。
在描述了各种封装之后，现在将在下文中描述用于制造封装的序列。
用于制造包括具有受控底切的封装层的封装的示例性序列
图13A-图13D图示了用于提供或制造包括具有受控底切的封装层的封装的示例性序列。在一些实现中，图13A-图13D的序列可以被用来提供或制造图6的封装600或者本公开中描述的任何器件(例如，200、300、500、700、800、900、1000、1100、1200)。
应当注意，图13A-图13D的序列可以结合一个或多个阶段，以便简化和/或明确用于提供或制造封装的序列。在一些实现中，过程的顺序可以被改变或修改。在一些实现中，在不背离本公开的精神的情况下，可以替换或替代一个或多个过程。
如图13A中所示，阶段1图示了在提供或制造衬底202之后的状态。衬底202包括至少一个电介质层220、多个互连件222(例如，导线、焊盘、通孔)、腔体1310、阻焊层224和阻焊层226。图15A-图15B中示出和描述了制造衬底的示例。衬底的制造可以包括层压过程和电镀过程。制造衬底的过程的示例包括半加成过程(SAP)和改良的半加成过程(mSAP)。然而，不同的实现可以以不同的方式制造衬底。不同的实现可以提供不同类型的衬底(例如，无芯衬底、层状衬底)。
阶段2图示了在集成器件606通过多个焊接互连件660而被耦合到衬底202之后的状态。集成器件606可以通过拾取和放置过程而被放置在衬底202的腔体1310中。可以使用回流焊过程通过多个焊接互连件660将集成器件606耦合到多个互连件221。
如图13B中所示，阶段3图示了在通过多个焊接互连件240将集成器件204耦合到衬底202的第一表面以及通过多个焊接互连件260将集成器件206耦合到衬底202的第一表面之后的状态。集成器件204和206可以通过拾取和放置过程而被放置在衬底202的第一表面之上。可以使用回流焊接过程(i)通过多个焊接互连件240将集成器件204耦合到多个互连件221，以及(ii)通过多个焊接互连件260将集成器件206耦合到多个互连件221。
阶段4图示了在衬底202、集成器件204和集成器件206之上形成封装层207之后的状态。封装层207可以是第一封装层(例如，用于第一封装的部件)。封装层207可以包括模具、树脂和/或环氧树脂。封装层207可以包括各向同性的材料和/或各向异性的材料。可以使用片状成型过程(例如，真空层压、压缩成型)来形成封装层207。对于每个集成器件，封装层207可以具有在-20-50微米(μm)范围内的底切值。针对集成器件和/或堆叠器件的封装层207的底切值可以是可变的。
在衬底202、集成器件204和集成器件206之上形成封装层207，以使得封装层207具有大致均匀的厚度，因为封装层207大致跟随衬底202、集成器件204和集成器件206的轮廓。例如，封装层207可以具有大约80微米(μm)±8微米(μm)的厚度。片状成型过程可以允许对封装层207的底切的准确和精确控制，这继而又允许对集成器件和衬底之间的空隙(如242、262、662)的准确和精确控制。可以在不需要跟随衬底202、集成器件204和集成器件206的轮廓的铝箔和/或密封膜的情况下形成封装层207。这可以通过使用具有低粘度值的封装层207的片状模具来完成，以使得封装层207基本上不会在集成器件下方流动。因此，可以制造一种在封装层207与衬底202、集成器件204和集成器件206之间没有箔和/或密封膜的封装。无箔封装或无密封膜封装的一个优点是，由于这至少少了一个步骤以及至少少了一种材料，所以封装的制造成本更低。
如图13C中所示，阶段5图示了在封装层207之上形成封装层209之后的状态。可以使用压缩成型过程、转移成型过程或液体成型过程来形成封装层209。封装层209可以是光蚀刻的。在封装层209和封装层207之间可以具有边界界面。封装层209可以包括模具、树脂和/或环氧树脂。此外，除了成型过程外，封装层209可以与封装层207层压在一起，形成一个单片。这个包括封装层207和封装层209的单片可以经由真空层压或压缩成型而被施加到衬底202、集成器件204和集成器件206上。
阶段6图示了在通过多个焊接互连件560将集成器件506耦合到衬底202的第二表面之后的状态。集成器件506可以通过拾取和放置过程而被放置在衬底202的第二表面上。可以使用回流焊过程来通过多个焊接互连件560将集成器件506耦合到多个互连件221。阶段6还图示了耦合到衬底202的多个焊接互连件230。可以使用回流焊过程将多个焊接互连件230耦合到衬底202。
阶段7，如图13D中所示，图示了在衬底202的第二表面之上形成封装层509之后的状态。可以使用压缩成型过程、转移成型过程或液体成型过程来形成封装层509。封装层509可以是光蚀刻的。封装层509可以包括模具、树脂和/或环氧树脂。封装层509可以封装集成器件506和多个焊接互连件230的部分。在一些实现中，封装层509可以位于集成器件506的背面之上。
阶段8图示了在EMI屏蔽件250形成并位于封装层209的表面和衬底202的侧表面之上之后的状态。可以使用溅射过程、喷雾涂层和/或电镀过程来形成EMI屏蔽件250。EMI屏蔽件250可以包括导电层。EMI屏蔽件250可以被配置为耦合到地。阶段8可能图示了图6的封装600。
用于制造包括具有受控底切的封装层的封装的方法的示例性流程图
在一些实现中，制造具有受控底切的封装层的封装包括若干过程。图14图示了用于提供或制造具有受控底切的封装层的封装的方法1400的示例性流程图。在一些实现中，图14的方法1400可以被用来提供或制造本公开中描述的图6的封装600。然而，该方法1400可以被用来提供或制造本公开中描述的任何器件(例如，200、300、500、700、800、900、1000、1100、1200)。
应当注意，图14的序列可以结合一个或多个过程，以便简化和/或明确提供或制造封装的方法。在一些实现中，过程的顺序可以被改变或修改。
该方法(在1405处)提供衬底(例如，202)。衬底可以被提供或制造。衬底可以包括至少一个电介质层220、多个互连件222(例如，导线、焊盘、通孔)、腔体1310、阻焊层224和阻焊层226。图15A-图15B中示出和描述了制造衬底的示例。衬底的制造可以包括层压过程和电镀过程。制造衬底的过程的示例包括半加成过程(SAP)和改良的半加成过程(mSAP)。然而，不同的实现可以以不同的方式制造衬底。不同的实现可以提供不同类型的衬底(例如，无芯衬底、层压衬底)。图13A的阶段1图示并描述了衬底的示例。
该方法(在1410)将至少一个器件(例如，204、206、606)耦合到衬底(例如，202)上。该器件可以被放置在衬底的腔体中。该器件可以被耦合到衬底的第一表面。拾取和放置过程可以被用来将(多个)器件放置和耦合到衬底上。图13A-图13B的阶段2和3图示和描述了和描述了耦合到衬底的器件的示例。
该方法(在1415处)在衬底202的第一表面和器件(例如，204、206)之上形成封装层(例如，207)。封装层207可以是第一封装层(例如，用于第一封装的部件)。封装层207可以包括模具、树脂和/或环氧树脂。封装层207可以包括各向同性的材料和/或各向异性的材料。可以使用片状成型过程(例如，真空层压、压缩成型)来形成封装层207。对于每个集成器件，封装层207可以具有在-20-50微米(μm)范围内的底切值。针对集成器件和/或堆叠器件的封装层207的底切值可以是可变的。
在衬底202、集成器件204和集成器件206之上形成(例如，安置)封装层207，以使得封装层207具有大致均匀的厚度，因为封装层207大致跟随衬底(例如，202)和器件(例如，204、206)的轮廓。例如，封装层207可以具有大约80微米(μm)±8微米(μm)的厚度。片状成型过程可以允许对封装层207的底切的准确和精确控制，这继而又允许对器件和衬底之间的空隙(如242、262、662)的准确和精确控制。可以在不需要跟随衬底202、集成器件204和集成器件206的轮廓的铝箔和/或密封膜的情况下形成封装层207。这可以通过使用具有低粘度值的封装层207的片状模具来完成，以使得封装层207基本上不会在(多个)集成器件下方流动。图13C的阶段4图示和描述了在衬底和至少一个器件之上形成的封装层的示例。
该方法(在1420处)在第一封装层(例如，207)之上形成第二封装层(例如，209)。可以使用压缩成型过程、转移成型过程或液体成型过程来形成封装层209。封装层209可以是光蚀刻的。在封装层209和封装层207之间可以具有边界界面。封装层209可以包括模具、树脂和/或环氧树脂。图13C的阶段5图示和描述了在第一封装层之上形成的第二封装层的示例。
该方法(在1425)将至少一个器件(例如，506)和多个焊接互连件(例如，560)耦合到衬底(例如，202)的第二表面(例如，底表面)。拾取和放置过程以及回流焊过程可以被用来将集成器件506耦合到衬底202。回流焊过程可以被用来将多个焊接互连件230耦合到衬底202。图13C的阶段6图示和描述了耦合到衬底的器件和焊接互连件的示例。
该方法(在1430处)在衬底202的第二表面之上形成封装层(例如，509)。可以使用压缩成型过程、转移成型过程或液体成型过程来形成封装层509。封装层509可以是光蚀刻的。封装层509可以包括模具、树脂和/或环氧树脂。封装层509可以封装集成器件506和多个焊接互连件230的部分。图13D的阶段7图示和描述了在衬底的第二表面之上形成的封装层的示例。
该方法(在1435处)在封装层209的表面和衬底202的侧表面之上形成EMI屏蔽件(例如，250)。可以使用溅射过程、喷雾涂层和/或电镀过程来形成EMI屏蔽件250。EMI屏蔽件250可以包括导电层。EMI屏蔽件250可以被配置为耦合到地。图13D的阶段8图示和描述了形成EMI屏蔽件的示例。
用于制造衬底的示例性序列
图15A-图15C图示了用于提供或制造衬底的示例性序列。在一些实现中，图15A-图15C的序列可以被用来提供或制造图6的衬底202或者本公开中描述的任何衬底。如上所述，不同的实现可以使用不同的衬底，包括层状衬底和无芯衬底(例如，嵌入迹线衬底)。图15A-图15C中所示的衬底是可以使用的可能衬底的示例。
应当注意，图15A-图15C的序列可以结合一个或多个阶段，以便简化和/或明确用于提供或制造衬底的序列。在一些实现中，过程的顺序可以被改变或修改。在一些实现中，在不背离本公开的精神的情况下，可以替换或替代一个或多个过程。
如图15A中所示，阶段1图示了提供载体1500之后的状态。载体1500可以是衬底。
阶段2图示了在载体1500之上形成互连件1502之后的状态。互连件1502可以是来自多个互连件221的互连件。电镀过程可以被用来形成互连件1502。
阶段3图示了在互连件1502和载体1500之上形成电介质层1520之后的状态。可以使用沉积和/或层压过程来形成电介质层1520。
阶段4图示了在电介质层1520中形成一个或多个腔体1503之后的状态。可以使用激光过程(例如，激光烧蚀)或光蚀刻过程(例如，光刻过程)来形成一个或多个腔体1503。
阶段5图示了在电介质层1520之上形成互连件1504之后的状态。互连件1504可以是来自多个互连件221的互连件。电镀过程可以被用来形成互连件1504。
阶段6，如图15B中所示，图示了在电介质层1520之上形成电介质层1540之后的状态。介质层1540可以由与介质层1520相同的材料制成。沉积和/或层压过程可以被用来形成电介质层1540。可以形成电介质层1540，以使得形成腔体1310。
阶段7图示了在电介质层1540之上形成互连件1542之后的状态。互连件1542可以是来自多个互连件221的互连件。电镀过程可以被用来形成互连件1542。在一些实现中，可能已经在电介质层1540中形成一个或多个腔体，并且互连件1542可以在电介质层1540的腔体之上形成。
阶段8图示了在电介质层1540之上形成电介质层1560之后的状态。电介质层1560可以是与电介质层1520和/或1540相同的材料。沉积和/或层压过程可以被用来形成电介质层1560。可以形成介质层1560，从而形成腔体1310。
如图15C中所示，阶段9图示了在电介质层1560之上形成互连件1562和1564的状态。互连件1562可以是来自多个互连件221的互连件。电镀过程可以被用来形成互连件1562。在一些实现中，可能已经在电介质层1560中形成一个或多个腔体，并且互连件1562可以在电介质层1560的腔体之上形成。
阶段10图示了在载体1500被移除之后的状态。阶段10可以图示衬底202的一部分。电介质层220可以表示电介质层1520、1540和1560。互连件221可以表示互连件1502、1504、1542和1562以及1564。
用于制造堆叠器件的示例性序列
图16A-16B图示了用于提供或制造包括堆叠集成器件(例如，堆叠的过滤器)的器件的示例性序列。在一些实现中，图16A-图16B的序列可以被用来提供或制造图11的堆叠器件1104或者本公开中描述的任何堆叠器件。
应当注意，图16A-图16B的序列可以结合一个或多个阶段，以便简化和/或明确用于提供或制造包括堆叠集成器件的器件的序列。在一些实现中，过程的顺序可以被改变或修改。在一些实现中，在不背离本公开的精神的情况下，可以替换或替代一个或多个过程。
如图16A中所示，阶段1图示了在提供集成器件1114之后的状态。集成器件1114可以被配置作为过滤器。集成器件1114可以是裸片过滤器(例如，SAW过滤器、BAW过滤器)。集成器件1114包括衬底1610和至少一个金属层1614。衬底1610可以是压电衬底。例如，衬底1610可以包括压电材料(例如，氮化铝(AlN)、石英、铌酸锂、钽酸锂)。在另一个示例中，衬底1610可以包括压电层，该压电层形成并位于衬底1610的表面之上。例如，衬底1610可以包括具有压电层的玻璃，该压电层形成并位于玻璃的表面之上。也可以使用其他材料代替玻璃。本公开中使用的压电衬底可以意指包括压电材料的衬底和/或包括与衬底的表面耦合并位于其之上的压电层的衬底。不同的实现可以针对压电材料和/或压电层使用不同的材料。
至少一个金属层1614形成在衬底1610之上。在当衬底1610包括形成并位于衬底1610的表面之上的压电层的情况下，至少一个金属层1614可以形成并位于压电层之上。至少一个金属层1614可以包括导电材料，诸如铜(Cu)。至少一个金属层1614可以被图案化和/或配置作为集成器件1114的互连件、电极和/或换能器。在一些实现中，金属层1614可以包括第一金属层和第二金属层。第一金属层可以被配置为操作为至少一个换能器，而第二金属层可以被配置为与换能器耦合的至少一个互连件。在一些实现中，可以形成金属层1614的第一金属层，然后可以形成金属层1614的第二金属层。
阶段2图示了聚合物框架1118被耦合到集成器件1114之后的状态。可以使用沉积过程来形成聚合物框架1118并将其耦合到集成器件1114。
阶段3图示了在提供集成器件1116之后的状态。集成器件1116可以被配置作为过滤器。集成器件1116可以是裸片过滤器(例如，SAW过滤器、BAW过滤器)。集成器件1116包括衬底1620和至少一个金属层1624。衬底1620可以是压电衬底。例如，衬底1610可以包括压电材料(例如，氮化铝(AlN)、石英、铌酸锂、钽酸锂)。在另一个示例中，衬底1620可以包括压电层，该压电层形成并位于衬底1620的表面之上。例如，衬底1620可以包括具有压电层的玻璃，该压电层形成并位于玻璃的表面之上。也可以使用其他材料代替玻璃。本公开中使用的压电衬底可以意指包括压电材料的衬底和/或包括与衬底的表面耦合并位于其之上的压电层的衬底。不同的实现可以针对压电材料和/或压电层使用不同的材料。
至少一个金属层1624形成在衬底1620之上。在当衬底1620包括形成并位于衬底1620的表面之上的压电层的情况下，至少一个金属层1624可以形成并位于压电层之上。至少一个金属层1624可以包括导电材料，诸如铜(Cu)。至少一个金属层1624可以被图案化和/或配置作为集成器件1116的互连件、电极和/或换能器。在一些实现中，金属层1624可以包括第一金属层和第二金属层。第一金属层可以被配置为操作为至少一个换能器，而第二金属层可以被配置为与换能器耦合的至少一个互连件。在一些实现中，可以形成金属层1624的第一金属层，然后可以形成金属层1624的第二金属层。
阶段4图示了在衬底1620和至少一个金属层1624之上形成可选的保护层1630之后的状态。保护层1630可以被沉积在衬底1620和至少一个金属层1624之上。
如图16B中所示，阶段5图示了在集成器件1114被耦合到集成器件1116之后的状态，以使得在集成器件1114、集成器件1116和聚合物框架1118之间形成空隙1120。可以使用热压缩过程将集成器件1114耦合到集成器件1116。如果形成保护层1630，则在将集成器件1114耦合到集成器件1116之后，可以移除保护层1630。
阶段6图示了在集成器件1114、集成器件1116和聚合物框架1118的表面之上形成多个互连件1119之后的状态。多个互连件1119可以被耦合到至少一个金属层1614和至少一个金属层1624。可以使用电镀过程、溅射过程和/或喷涂过程来形成多个互连件1119。
阶段7图示了在多个焊接互连件1140耦合到多个互连件1119之后的状态。可以使用回流焊过程将多个焊接互连件1140耦合到多个互连件1119。阶段7可以图示如图11中所示的堆叠器件1104。
制造堆叠器件的示例性序列
图17A-图17B图示了用于提供或制造包括堆叠集成器件(例如，堆叠的过滤器)的器件的示例性序列。在一些实现中，图17A-图17B的序列可以被用来提供或制造图12的堆叠器件1204或者本公开中描述的任何堆叠器件。
应当注意，图17A-图17B的序列可以结合一个或多个阶段，以便简化和/或明确用于提供或制造包括堆叠集成器件的器件的序列。在一些实现中，过程的顺序可以被改变或修改。在一些实现中，在不背离本公开的精神的情况下，可以替换或替代一个或多个过程。
如图17A中所示，阶段1图示了在提供集成器件1114之后的状态。集成器件1114可以被配置作为过滤器。集成器件1114包括衬底1610和至少一个金属层1614。图17A的集成器件1114与图16A的集成器件1114类似或相同。
阶段2图示了在互连框架1218被耦合到集成器件1114之后的状态。互连框架1218可以被耦合到至少一个金属层1614。可以使用电镀过程来形成互连框架1218并将互连框架1218耦合到集成器件1114。然而，不同的实现可以以不同的方式形成和耦合互连框架1218。
阶段3图示了在提供集成器件1116之后的状态。集成器件1116可以被配置作为过滤器。集成器件1216可以是裸片过滤器(例如，SAW过滤器、BAW过滤器)。集成器件1116包括衬底1620、至少一个金属层1624和至少一个通孔1217。图17A的集成器件1116类似于图16A的集成器件1116。至少一个通孔1217可以穿过衬底1620。
阶段4图示了在衬底1620和至少一个金属层1624之上形成可选的保护层1630之后的状态。保护层1630可以被沉积在衬底1620和至少一个金属层1624之上。
如图17B中所示，阶段5图示了在集成器件1114被耦合到集成器件1116之后的状态，以使得在集成器件1114、集成器件1216和互连框架1218之间形成空隙1120。互连框架1218可以被耦合到至少一个通孔1217。如上面所提及的，互连框架1218可以被耦合到至少一个金属层1614。可以使用热压缩过程将集成器件1114耦合到集成器件1216。如果形成保护层1630，则在将集成器件1114耦合到集成器件1216之后，可以移除保护层1630。
阶段6图示了在集成器件1216的表面之上形成多个互连件1219之后的状态。多个互连件1219可以被耦合到至少一个通孔1217和至少一个金属层1624。至少一个通孔1217可以被耦合到至少一个金属层1624。可以使用电镀过程、溅射过程和/或喷涂过程来形成多个互连件1219。
阶段7图示了在多个焊接互连件1140被耦合到多个互连件1219之后的状态。可以使用回流焊过程将多个焊接互连件1140耦合到多个互连件1219。阶段7可以图示如图12中所示的堆叠设备1204。
示例性电子设备
图18图示了可以与上述器件、集成器件、集成电路(IC)封装、集成电路(IC)器件、半导体器件、集成电路、裸片、插接器、封装、封装上封装(PoP)、封装中系统(SiP)或片上系统(SoC)中的任何一个集成的各种电子设备。例如，移动电话设备1802、笔记本计算机设备1804、固定位置终端设备1806、可穿戴设备1808或汽车车辆1810可以包括如本文所述的设备1800。该设备1800例如可以是如本文所述的任何器件和/或集成电路(IC)封装。图18中图示的设备1802、1804、1806和1808以及车辆1810只是示例性的。其他电子设备也可以具有设备1800，包括但不限于包括如下的一组设备(例如，电子设备)：移动设备、手持式个人通信系统(PCS)单元、便携式数据单元诸如个人数字助理、启用全球定位系统(GPS)的设备、导航设备、机顶盒、音乐播放器、视频播放器、娱乐单元、固定位置数据单元诸如抄表设备、通信设备、智能电话、平板计算机、计算机、可穿戴设备(例如，手表、眼镜)、物联网(IoT)设备、服务器、路由器、在汽车车辆(例如，自主车辆)中实现的电子设备、或者存储或检索数据或计算机指令的任何其他设备或其任何组合。
图2-12、图13A-图13D、图14、图15A-图15C、图16A-图16B、图17A-图17B和/或图18中图示的组件、过程、特征和/或功能中的一个或多个可以被重新布置和/或组合成单个组件、过程、特征或功能，或被体现在若干组件、过程或功能中。在不背离本公开的情况下，还可以添加其他的元件、组件、过程和/或功能。还应注意，在本公开中的图2-12、图13A-图13D、图14、图15A-图15C、图16A-图16B、图17A-图17B和/或图18及其对应的描述不限于裸片和/或集成电路。在一些实现中，图2-12、图13A-13D、图14、图15A-15C、图16A-16B、1图7A-17B和/或图18及其相应描述可用于制造、创造、提供和/或生产器件和/或IC。在一些实现中，器件可以包括裸片、集成器件、集成无源器件(IPD)、裸片封装、集成电路(IC)器件、器件封装、集成电路(IC)封装、晶圆、半导体器件、封装上封装(PoP)器件、散热器件和/或插接器。
应当注意，本公开中的附图可以表示各种零件、组件、物体、器件、封装、集成器件、集成电路和/或晶体管的实际表示和/或概念表示。在一些实例中，这些附图可能不符合比例。在一些实例中，为了清晰起见，可能没有示出所有的组件和/或零件。在一些实例中，附图中的各种零件和/或组件的方位、位置、大小和/或形状可能是示例性的。在一些实现中，附图中的各种组件和/或零件可以是可选的。
词语“示例性”在本文被用来意指“用作示例、实例或说明”。本文中被描述为“示例性”的任何实现或方面不一定被解释为比本公开的其他方面更优选或有利。同样，术语“方面”并不要求本公开的所有方面都包括所讨论的特征、优点或操作模式。术语“耦合”在本文中被用来指代两个对象之间的直接或间接耦合(例如，机械耦合)。例如，如果对象A物理接触对象B，而对象B接触对象C，那么对象A和C仍然可以被认为互相耦合——即使它们没有直接彼此物理接触。术语“电耦合”可以意指两个对象直接或间接地耦合在一起，以使得电流(例如，信号、电源、地线)可以在两个对象之间传播。两个被电耦合的对象在两个对象之间可以有也可以没有电流传输。术语“第一”、“第二”、“第三”和“第四”(和/或第四以上的内容)的使用是随机的。所述的任何组件都可以是第一组件、第二组件、第三组件或第四组件。例如，一个被称为第二组件的组件，可以是第一组件、第二组件、第三组件或第四组件。术语“包围”意指该对象可以部分地包围或完全地包围另一个对象。术语“封装”意指该对象可以部分地封装或完全地封装另一个对象。术语“顶部”和“底部”是随机的。一个位于顶部的组件可以位于一个位于底部的组件之上。顶部组件可以被认为是底部组件，反之亦然。如本公开中所述，位于第二组件“之上”的第一组件可能意味着第一组件位于第二组件的之上或下方，这取决于底部或顶部是如何被随机定义的。在另一个示例中，第一组件可以位于第二组件的第一表面之上(例如，高于)，而第三组件可以位于第二组件的第二表面之上(例如，低于)，其中第二表面与第一表面相反。还需要注意的是，本申请中在一个组件位于另一个组件之上的情况下使用的术语“在……之上”(over)，可以被用来意指一个组件在另一个组件上和/或在另一个组件中(例如，在一个组件的表面上或被嵌入在一个组件中)。因此，例如，位于第二组件之上的第一组件可以意指：(1)第一组件在第二组件之上，但是不直接接触第二组件，(2)第一组件在第二组件上(例如，在第二组件的表面上)，和/或(3)第一组件在第二组件中(例如，嵌入在第二组件中)。位于第二组件“中”的第一组件可以部分位于第二组件中，或完全位于第二组件中。如在本公开中所使用的，术语“大约'值X'”，或“大致值X”意味着在“值X”的10％以内。例如，大约1或大致1的值，将意味着在0.9-1.1的范围内的值。
在一些实现中，互连件是器件或封装的元件或组件，其允许或促进两个点、元件和/或组件之间的电连接。在一些实现中，互连件可以包括迹线、通孔、焊盘、支柱、重新分布金属层和/或凸点下金属化(UBM)层。在一些实现中，互连件是一种导电材料，其可以被配置成为信号(例如，数据信号)、接地和/或电源提供电气路径。互连件可以包括一个以上的元件或组件。互连件可以由一个或多个互连件来定义。互连件可以是电路的一部分。不同的实现可以使用用于形成互连件的不同过程和/或序列。在一些实现中，可以使用化学气相沉积(CVD)过程、物理气相沉积(PVD)过程、溅射过程、喷雾涂层和/或电镀过程来形成互连件。
另外，注意到本文所包含的各种公开可以被描述为过程，其被描绘为流程图、流程图、结构图或框图。尽管流程图可以将操作描述为顺序过程，但是许多操作可以平行或并发地执行。此外，操作的顺序可以被重新布置。当一个过程的操作完成时，该过程被终止。
本文所描述的本公开的各种特征可以在不背离本公开的情况下在不同的系统中被实现。应当注意的是，本公开的前述方面仅仅是示例，并且不应被解释为对本公开的限制。对本公开的各方面的描述旨在是说明性的，而不是为了限制权利要求的范围。如此，本教导可以很容易地被应用于其他类型的装置，并且对于本领域的技术人员来说，许多替代方案、修改和变型都是显而易见的。

Claims (33)

1.一种封装，包括：
衬底，包括第一表面；
集成器件，被耦合到所述衬底的所述第一表面；
第一封装层，位于所述衬底的所述第一表面和所述集成器件之上，其中所述第一封装层包括相对于所述集成器件的侧表面的底切，以及
空隙，位于所述集成器件和所述衬底的所述第一表面之间，其中所述空隙被所述第一封装层的所述底切横向地包围。
2.根据权利要求1所述的封装，其中相对于所述集成器件的所述侧表面的所述第一封装层的所述底切在-20-50微米(μm)的范围内。
3.根据权利要求1所述的封装，其中所述封装在所述第一封装层和所述集成器件之间没有密封膜。
4.根据权利要求1所述的封装，还包括位于所述第一封装层之上的第二封装层，其中所述第一封装层在所述集成器件的顶表面之上具有均匀的厚度。
5.根据权利要求4所述的封装，其中所述第二封装层具有与所述第一封装层不同的性质。
6.根据权利要求4所述的封装，其中所述第二封装层具有第二热膨胀系数(CTE)，所述第二CTE(i)大于所述第一封装层的第一CTE，或(ii)低于所述第一封装层的所述第一CTE。
7.根据权利要求1所述的封装，其中所述衬底具有衬底CTE，所述衬底CTE在所述集成器件和所述第一封装层的有效CTE的15百万分率/开尔文(ppm/K)内。
8.根据权利要求1所述的封装，其中所述衬底具有衬底CTE，所述衬底CTE在所述封装其余部分的有效CTE的15百万分率/开尔文(ppm/K)内。
9.根据权利要求1所述的封装：
其中所述衬底包括腔体；
其中所述集成器件位于所述衬底的所述腔体之上；
其中所述空隙包括所述衬底的所述腔体，以及
其中所述封装包括位于所述衬底的所述腔体中的第二集成器件。
10.根据权利要求1所述的封装，还包括：
堆叠器件，被耦合到所述衬底；以及
第二空隙，位于所述堆叠器件和所述衬底之间；
其中所述衬底包括腔体；
其中所述第二空隙包括所述衬底的所述腔体，以及
其中所述堆叠器件位于所述衬底的所述腔体之上。
11.根据权利要求10所述的封装，其中所述堆叠器件包括第一裸片过滤器和第二裸片过滤器。
12.根据权利要求1所述的封装，其中所述集成器件包括射频(RF)器件、无源器件、过滤器、电容器、电感器、表面声波(SAW)过滤器、体声波(BAW)过滤器、处理器、存储器和/或其组合。
13.根据权利要求1所述的封装，还包括：
第二封装层，位于所述第一封装层之上；以及
电磁干扰(EMI)屏蔽件，位于所述第二封装层之上。
14.根据权利要求13所述的封装，还包括：
第二集成器件，被耦合到所述衬底的第二表面；以及
第三封装层，被耦合到所述衬底的所述第二表面，并封装所述第二集成器件。
15.一种装置，包括：
衬底，包括第一表面；
集成器件，被耦合到所述衬底的所述第一表面；
用于第一封装的部件，位于所述衬底的所述第一表面和所述集成器件之上，其中所述用于第一封装的部件包括相对于所述集成器件的侧表面的底切，以及
空隙，位于所述集成器件和所述衬底的所述第一表面之间，其中所述空隙被所述用于第一封装的部件的所述底切横向地包围。
16.根据权利要求15所述的装置，其中相对于所述集成器件的所述侧表面的所述用于第一封装的部件的所述底切在-20-50微米(μm)的范围内。
17.根据权利要求15所述的装置，其中所述装置在所述用于第一的封装部件和所述集成器件之间没有密封膜。
18.根据权利要求15所述的装置，还包括位于所述用于第一封装的部件之上的用于第二封装的部件，其中所述用于第二封装的部件具有与所述用于第一封装的部件不同的性质。
19.根据权利要求18所述的装置，其中所述用于第二封装的部件具有第二热膨胀系数(CTE)，所述第二CTE大于所述用于第一封装的部件的第一CTE。
20.根据权利要求15所述的装置，其中所述衬底具有衬底CTE，所述衬底CTE在所述集成器件和所述用于第一封装的部件的有效CTE的15百万分率/开尔文(ppm/K)内。
21.根据权利要求15所述的装置，其中所述衬底具有大约在5-20百万分率/开尔文(ppm/K)之间的衬底CTE。
22.根据权利要求15所述的装置，
其中所述衬底包括腔体；
其中所述集成器件位于所述衬底的所述腔体之上；
其中所述空隙包括所述衬底的所述腔体，以及
其中所述装置包括位于所述衬底的所述腔体中的第二集成器件。
23.根据权利要求15所述的装置，还包括：
堆叠器件，被耦合到所述衬底；以及
第二空隙，位于所述堆叠器件和所述衬底之间；
其中所述衬底包括腔体；
其中所述第二空隙包括所述衬底的所述腔体，以及
其中所述堆叠器件位于所述衬底的所述腔体之上。
24.根据权利要求23所述的装置，其中所述堆叠器件包括用于第一信号过滤的部件和用于第二信号过滤的部件。
25.根据权利要求15所述的装置，其中所述集成器件包括射频(RF)器件、无源器件、过滤器、电容器、电感器、表面声波(SAW)过滤器、体声波(BAW)过滤器、处理器、存储器和/或其组合。
26.根据权利要求15所述的装置，还包括：
用于第二封装的部件，位于所述用于第一封装的部件之上；以及
用于电磁干扰(EMI)屏蔽的部件，位于所述用于第二封装的部件之上。
27.根据权利要求26所述的装置，还包括：
第二集成器件，被耦合到所述衬底的第二表面；以及
用于第三封装的部件，被耦合到所述衬底的所述第二表面，并封装所述第二集成器件。
28.根据权利要求15所述的装置，其中所述装置包括选自以下组中的设备：音乐播放器、视频播放器、娱乐单元、导航设备、通信设备、移动设备、移动电话、智能电话、个人数字助理、固定位置终端、平板计算机、计算机、可穿戴设备、笔记本计算机、服务器、物联网(IoT)设备、以及汽车车辆中的设备。
29.一种用于制造封装的方法，包括：
提供包括第一表面的衬底；
将集成器件耦合到所述衬底的所述第一表面；以及
在所述衬底的所述第一表面和所述集成器件之上形成第一封装层；
其中所述第一封装层包括相对于所述集成器件的侧表面的底切，以及
其中形成所述第一封装层形成位于所述集成器件和所述衬底的所述第一表面之间的空隙，其中所述空隙被所述第一封装层的所述底切横向地包围。
30.根据权利要求29所述的方法，其中相对于所述集成器件的所述侧表面的所述第一封装层的所述底切在-20-50微米(μm)的范围内。
31.根据权利要求29所述的方法，其中所述封装在所述第一封装层和所述集成器件之间没有密封膜。
32.根据权利要求29所述的方法，还包括在所述第一封装层之上形成第二封装层。
33.根据权利要求32所述的方法，其中所述第二封装层具有与所述第一封装层不同的性质。
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