CN1152795A - 用离子注入湿化学蚀刻使基底上的构图结构平面化的方法 - Google Patents
用离子注入湿化学蚀刻使基底上的构图结构平面化的方法 Download PDFInfo
- Publication number
- CN1152795A CN1152795A CN96119880A CN96119880A CN1152795A CN 1152795 A CN1152795 A CN 1152795A CN 96119880 A CN96119880 A CN 96119880A CN 96119880 A CN96119880 A CN 96119880A CN 1152795 A CN1152795 A CN 1152795A
- Authority
- CN
- China
- Prior art keywords
- insulating barrier
- picture construction
- insulating layer
- uncovered
- deposition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 56
- 239000000758 substrate Substances 0.000 title abstract description 8
- 238000003631 wet chemical etching Methods 0.000 title description 10
- 238000005468 ion implantation Methods 0.000 title description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 27
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 239000011248 coating agent Substances 0.000 claims abstract 2
- 238000000576 coating method Methods 0.000 claims abstract 2
- 230000004888 barrier function Effects 0.000 claims description 47
- 238000010276 construction Methods 0.000 claims description 22
- 230000008021 deposition Effects 0.000 claims description 8
- 238000002347 injection Methods 0.000 claims description 8
- 239000007924 injection Substances 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 238000005253 cladding Methods 0.000 claims 7
- 239000000463 material Substances 0.000 claims 7
- 238000005530 etching Methods 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000002950 deficient Effects 0.000 description 3
- 239000011259 mixed solution Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
- H01L21/31056—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
Landscapes
- Engineering & Computer Science (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical & Material Sciences (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Abstract
用于平面化基底顶表面上的构图结构平面化的方法,包括下述步骤:在构图结构上沉积绝缘层,在绝缘层的表面上注入预定深度的离子化的原子,在绝缘层上涂覆一光阻层并部分去除该光阻层,使得构图结构上的一部分绝缘层在与该构图结构的宽度基本相同的横向长度值上不被覆盖,将该不被覆盖的部分暴露在蚀刻剂下直到其被去除,而基本上与余下的绝缘层平齐,以及从绝缘层上去除光阻材料。该方法还包括在去除步骤之后重复地进行深蚀刻的步骤。
Description
本发明涉及平面化处理过程,并且尤其涉及一种用于使基底上的具有构图结构的层状物平面化的改进的方法。
当今的大部分集成电路(IC)都被制成多层,包括多个导电层、互联层等。在形成多层IC时,往往会出现具有非平面形貌的层状物,众所周知,这种非平面形貌会带来一系列的不足,例如多层集成电路中的空隙,这些空隙反过来会影响集成电路的性能。
为了消除这些缺陷,常常要使构成多层IC的层状物平面化。一种传统的使层状物平面化的方法是反复地进行沉积和蚀刻例如一个光阻层,直到得到满意的平面化的形貌,如图1A至1C所示。
参见图1A,首先,一个由例如氧化硅制成的绝缘层13被这样沉积在其上有构图结构12的基底上,使得沉积层13完全覆盖该构图结构12,从而形成一个突起部13’。然后,光阻层14被沉积在包括一个突起部13’的绝缘层13的顶上,如图1B所示。由于光阻层的流动性,光阻层14的一部分14’与绝缘层13的突起部13’相比变得较不明显。然后,光阻层14和绝缘层13的突起部13’被用干蚀刻法蚀刻。其中所用的蚀刻剂被这样选择,使得它以几乎一样的速度去掉光阻层14和绝缘层13的突起部13’,使得在蚀刻后突起部13’变得较不明显,如图1C所示。上述沉积和蚀刻过程反复进行,直到得到满意的形貌。
但是,上述现有技术的平面化方法有一个缺陷,即它要得到满意的形貌需要花费太长的时间。
因此,本发明的主要目的是提供一种改进的方法,能在大大缩短的时间间隔内使一特殊的表面平面化。
根据本发明,提供了一种用于使基底顶面上的构图结构平面化的方法,所述方法包括下述步骤:
(a)将一个绝缘层沉积在构图结构上;
(b)将一个光阻层涂覆在绝缘层上并部分地去除该光阻层,使得构图结构上的一部分绝缘层在与构图结构的宽度基本上相同的横向长度上不被覆盖;
(c)将不被覆盖的绝缘层部分暴露在蚀刻剂下,直到不被覆盖的绝缘层部分被去掉,并大体上与余下的绝缘层齐平;以及
(d)从绝缘层上去掉光阻层。
本发明的上述和其他目的和特征将通过下述结合附图对优选实施例的描述而变得明显,在附图中:
图1A至1C示出用于使具有非平面形貌的层状物平面化的现有技术的方法;
图2A至2H说明根据本发明的使具有非平面形貌的层状物平面化的方法;
图3A提供了没有事先进行离子注入步骤,而直接进行湿化学蚀刻得到的边缘形状;
图3B示出事先进行了离子注入步骤,然后进行湿化学蚀刻得到的边缘形状。
图2A至2H示出用于说明根据本发明的使具有非平面形貌的层状物平面化的方法的横断面图。
参见图2A,示出了一个基底21,其上带有构图结构22,该构图结构22高度为H,宽度为W,形成在基底的顶上,其中,构图结构22可以是任何结构,诸如一根导线或一个元件等等。
本发明的平面化方法的第一步是将绝缘层23这样沉积在基底的顶上,便得它完全覆盖形成在基底21顶上的构图结构22,使得绝缘层23由于构图结构22的存在而有一个突起部23’。通过采用化学汽相淀积法,由绝缘材料例如氧化硅等制成的绝缘层23被沉积在基底21顶上。
构成本发明的平面化方法的第二步是,将离子化的原子注入到绝缘层23,如图2B所示。这一处理在绝缘层23的整个表面进行,从而形成预定深度为D的注入表面区域29。该注入表面区域29表示绝缘层23中包括由于离子注入的导致的更多的缺陷的一个区域。该注入表面区域29的深度最好在100至200的范围。
本发明的平面化方法的第三步是在经离子注入的绝缘层23的顶上涂覆一个光阻层24,并通过采用照相平板印刷法去除位于构图22顶上的光阻层24的一部分24’,从而暴露出一部分突起部23′,即不被覆盖部分,如图2C所示。在去除部分24’时,要求其宽度W’与构图结构22的宽度W相似或相等。因此,在绝缘层23的顶上构成图案的光阻层24就这样用作下面的湿化学蚀刻过程的覆盖层。
本发明的平面化方法的第四步在于湿化学蚀刻,其中,绝缘层23的不被覆盖的部分暴露在蚀刻剂下。该不被覆盖的部分一直暴露在蚀刻剂下,直到绝缘层23的突起部23’被去除,从而基本上与绝缘层23的其余部分齐平。结果,一对突包26被留在绝缘层上,如图2D所示。
在湿蚀刻的过程中,由于绝缘层23的注入表面区域29中产生的缺陷使得蚀刻剂更容易沿着注入表面区域29进行蚀刻,使得沿注入表面部分29的蚀刻速度加快。这有效地减小了余下的突包26的高度。换句话说,用湿化学蚀刻法进行平面化时,若是绝缘层23的表面进行了离子注入处理,较之绝缘层23的表面未进行离子注入处理的湿化学蚀刻效率更高。
将这两种方法作一个比较,对未经离子注入处理的绝缘层23的表面进行湿化学蚀刻得到的突包27示于图3A;而对经过离子注入处理的绝缘层表面进行湿化学蚀刻得到的突包示出图3B。图3A中的蚀刻几乎是各向同性地进行的,而图3B中,由于沿着绝缘层23的注入表面区域29的高的蚀刻速度而在突包26和光阻层24之间形成一个沟,导致突包26的高度比突包27低。
另一方面,一般将NH4F、HF和H2O的混合溶液用作蚀刻剂。众所周知,混合溶液中所述HF越稀释,在绝缘层23上得到的形貌越平。根据本发明,例如体积比NH4F∶HF为30∶1的水溶液可以用作蚀刻剂。
本发明的平面化方法的第五步是去除留在绝缘层23顶上的光阻层24。如图2E中所示,绝缘层23与它最初处于构图结构22上形成突起部23’时相比,具有更平面化的形貌,如图2A所示。
最后,在光阻层被已去除的绝缘层23的顶表面上反复地进行熟知的深蚀刻处理。可以这样来说明,光阻层28被涂覆在绝缘层23的表面上,作为待除层,如图2F所示。作为涂覆操作的结果,由于其流动性,光阻层28的顶表面比图2E中的绝缘层23的顶表面变得更平面化。然后,光阻层28与突包26一起被用例如干蚀刻的方法进行蚀刻。使用的蚀刻剂被选得对于光阻层28和绝缘层23两者具有几乎相等的蚀刻速度。由于有基本相等的蚀刻速度,当蚀刻完成时,绝缘层23的顶表面的形貌变得与光阻层28的原来的顶表面相同。换言之,绝缘层23的顶表面比进行了五个步骤之后更平面化,如图2G所示。这些涂覆和蚀刻过程反复进行,直到得到如图2H所示的满意的平面的形貌。
虽然本发明是参考优选实施例示出和描述的,但本领域的技术人员都会理解,在不脱离如所附的权利要求中限定的本发明的精神和范围的情况下,可以作出各种变化和修改。
Claims (18)
1、一种用于使在基底顶表面上的构图结构平面化的方法,其特征在于,所述方法包括下列步骤:
(a)在构图结构上沉积一绝缘层;
(b)在绝缘层上涂覆一覆盖材料,并且部分地去除该覆盖材料,使得构图结构上的一部分绝缘层不被覆盖;
(c)将绝缘层的该不被覆盖的部分暴露在蚀刻剂下,直到绝缘层的该不被覆盖的部分被去除;以及
(d)去除绝缘层顶上的余下的覆盖材料。
2、如权利要求1所述的方法,其特征在于,绝缘层是通过采用化学汽相淀积法沉积的。
3、如权利要求1所述的方法,其特征在于,覆盖材料是光阻材料。
4、如权利要求1所述的方法,其特征在于,该不被覆盖的部分在横向上的长度值与构图结构的宽度基本相同。
5、如权利要求1所述的方法,其特征在于,在沉积步骤(a)和涂覆步骤(b)之间,还包括将一定深度的离子化的原子注入到绝缘层表面的步骤。
6、如权利要求5所述的方法,其特征在于,绝缘层是通过采用化学汽相淀积法沉积的。
7、如权利要求5所述的方法,其特征在于,覆盖材料是光阻材料。
8、如权利要求5所述的方法,其特征在于,不被覆盖的部分在横向上的长度值与构图结构的宽度基本相同。
9、如权利要求5所述的方法,其特征在于,离子的注入深度范围为100A至200A。
10、如权利要求1所述的方法,其特征在于,在去除步骤(d)之后,还包括反复地进行深蚀刻处理的步骤。
11、如权利要求10所述的方法,其特征在于,绝缘层是通过采用化学汽相淀积法沉积的。
12、如权利要求10所述的方法,其特征在于,覆盖材料为光阻材料。
13、如权利要求10所述的方法,其特征在于,不被覆盖的部分在横向上的长度值与构图结构的宽度基本相同。
14、如权利要求5所述的方法,其特征在于,在去除步骤(d)之后,还包括反复地进行深蚀刻处理的步骤。
15、如权利要求14所述的方法,其特征在于,绝缘层是通过采用化学汽相淀积法沉积的。
16、如权利要求14所述的方法,其特征在于,覆盖材料为光阻材料。
17、如权利要求14所述的方法,其特征在于,不被覆盖的部分在横向上的长度值与构图结构的宽度基本相同。
18、如权利要求14所述的方法,其特征在于,离子的注入深度范围为100至200。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950033524A KR0159409B1 (ko) | 1995-09-30 | 1995-09-30 | 평탄화 방법 |
KR33524/95 | 1995-09-30 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN1152795A true CN1152795A (zh) | 1997-06-25 |
Family
ID=19428923
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN96119880A Pending CN1152795A (zh) | 1995-09-30 | 1996-09-28 | 用离子注入湿化学蚀刻使基底上的构图结构平面化的方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5958797A (zh) |
JP (1) | JPH09134922A (zh) |
KR (1) | KR0159409B1 (zh) |
CN (1) | CN1152795A (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102479680A (zh) * | 2010-11-29 | 2012-05-30 | 中国科学院微电子研究所 | 半导体器件的制造方法 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050244756A1 (en) * | 2004-04-30 | 2005-11-03 | Clarner Mark A | Etch rate control |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0722145B2 (ja) * | 1984-07-31 | 1995-03-08 | 株式会社リコー | 半導体装置の製造方法 |
US5019526A (en) * | 1988-09-26 | 1991-05-28 | Nippondenso Co., Ltd. | Method of manufacturing a semiconductor device having a plurality of elements |
US4944682A (en) * | 1988-10-07 | 1990-07-31 | International Business Machines Corporation | Method of forming borderless contacts |
US5068207A (en) * | 1990-04-30 | 1991-11-26 | At&T Bell Laboratories | Method for producing a planar surface in integrated circuit manufacturing |
US5429990A (en) * | 1994-04-08 | 1995-07-04 | United Microelectronics Corporation | Spin-on-glass planarization process with ion implantation |
JP3047343B2 (ja) * | 1994-07-30 | 2000-05-29 | 日本電気株式会社 | 半導体装置の製造方法 |
US5413953A (en) * | 1994-09-30 | 1995-05-09 | United Microelectronics Corporation | Method for planarizing an insulator on a semiconductor substrate using ion implantation |
KR0159388B1 (ko) * | 1995-09-30 | 1999-02-01 | 배순훈 | 평탄화 방법 |
JP2838992B2 (ja) * | 1995-11-10 | 1998-12-16 | 日本電気株式会社 | 半導体装置の製造方法 |
-
1995
- 1995-09-30 KR KR1019950033524A patent/KR0159409B1/ko not_active IP Right Cessation
-
1996
- 1996-09-23 US US08/716,757 patent/US5958797A/en not_active Expired - Fee Related
- 1996-09-26 JP JP8254113A patent/JPH09134922A/ja active Pending
- 1996-09-28 CN CN96119880A patent/CN1152795A/zh active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102479680A (zh) * | 2010-11-29 | 2012-05-30 | 中国科学院微电子研究所 | 半导体器件的制造方法 |
Also Published As
Publication number | Publication date |
---|---|
JPH09134922A (ja) | 1997-05-20 |
US5958797A (en) | 1999-09-28 |
KR970018222A (ko) | 1997-04-30 |
KR0159409B1 (ko) | 1999-02-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4832788A (en) | Method of fabricating a tapered via hole in polyimide | |
US5882999A (en) | Process for metallization of an insulation layer | |
KR20000048294A (ko) | 듀얼 다마신 배선의 형성방법 | |
US6479884B2 (en) | Interim oxidation of silsesquioxane dielectric for dual damascene process | |
CN1152795A (zh) | 用离子注入湿化学蚀刻使基底上的构图结构平面化的方法 | |
CN1050693C (zh) | 半导体器件薄膜的平面化方法 | |
CN1053064C (zh) | 半导体器件中针形接点的形成方法 | |
JP3962339B2 (ja) | 電子デバイスの製造方法 | |
KR100379551B1 (ko) | 듀얼 다마신 공정을 이용한 반도체 소자의 제조방법 | |
KR910006744B1 (ko) | 접속창 채움방법 | |
KR960010064B1 (ko) | 콘택홀에 선택적인 금속층 형성방법 | |
KR101016855B1 (ko) | 반도체 소자의 듀얼 다마신 패턴 형성방법 | |
KR100207530B1 (ko) | 반도체소자의 콘택홀 형성방법 | |
KR100650902B1 (ko) | 반도체 금속 배선 및 그 제조방법 | |
KR100598308B1 (ko) | 반도체 소자의 다마신 패턴 형성방법 | |
CN1099132C (zh) | 形成半导体器件的隔离层的方法 | |
DE102004063264B4 (de) | Verfahren zum Ausbilden elektrischer Verbindungen in einer Halbleiterstruktur | |
KR100688786B1 (ko) | 금속 절연체 금속 캐패시터 제조 방법 | |
KR100379530B1 (ko) | 반도체 소자의 듀얼 다마신 형성방법 | |
KR940005609B1 (ko) | 단차가 없는 도전층 패턴 제조방법 | |
KR960006341B1 (ko) | 반도체 소자의 스몰포켙 제거 방법 | |
KR100236095B1 (ko) | 반도체 소자의 금속배선 형성방법 | |
KR0148326B1 (ko) | 반도체 소자의 제조방법 | |
KR100209279B1 (ko) | 반도체 소자의 콘택홀 형성방법 | |
JPH07106419A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
WD01 | Invention patent application deemed withdrawn after publication |