CN115084221A - 一种低栅漏电容梯型栅沟槽型的功率器件的制造方法 - Google Patents
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Abstract
本发明提供了一种低栅漏电容梯型栅沟槽型的功率器件的制造方法,在具备有漂移层的碳化硅衬底上形成阻挡层,并对阻挡层蚀刻形成掩蔽层通孔,通过掩蔽层通孔进行离子注入,形成掩蔽层;清除阻挡层,在漂移层上进行离子注入,形成夹断区;在夹断区上重新形成阻挡层,并对阻挡层、夹断区、漂移层和掩蔽层蚀刻形成梯形槽,所述梯形槽上宽下窄,然后氧化栅极区,形成栅极绝缘层;进行淀积,形成栅极;通过在夹断区上重新形成阻挡层、蚀刻以及离子注入,形成源区;淀积,形成源极金属层、栅极金属层以及漏极金属层;在不影响器件性能的基础上,将功率器件的栅电容进行减少,从而提高器件的开关速度。
Description
技术领域
本发明涉及一种低栅漏电容梯型栅沟槽型的功率器件的制造方法。
背景技术
SiC器件碳化硅(SiC)材料因其优越的物理特性,广泛受到人们的关注和研究。其高温大功率电子器件具备输入阻抗高、开关速度快、工作频率高、耐高温高压等优点,在开关稳压电源、高频加热、汽车电子以及功率放大器等方面取得了广泛应用。
然而由于SiC临界击穿场强特别高而栅氧质量较差,在沟槽型SiC MOSFET中,栅氧在其底端,角度最小处电场集中,电场强度极大,故需要解决沟槽型栅底端的电场强度过大问题。随着电力电子应用对于高功率密度的追求越来越高,器件栅电容和开关速度对于电源模块的功率密度提高有着至关重要的影响。
发明内容
本发明要解决的技术问题,在于提供一种低栅漏电容梯型栅沟槽型的功率器件的制造方法,在不影响器件性能的基础上,将功率器件的栅电容进行减少,从而提高器件的开关速度。
本发明是这样实现的:一种低栅漏电容梯型栅沟槽型的功率器件的制造方法,包括如下步骤:
步骤1、在具备有漂移层的碳化硅衬底上形成阻挡层,并对阻挡层蚀刻形成掩蔽层通孔,通过掩蔽层通孔进行离子注入,形成掩蔽层;
步骤2、清除阻挡层,在漂移层上进行离子注入,形成夹断区;
步骤3、在夹断区上重新形成阻挡层,并对阻挡层、夹断区、漂移层和掩蔽层蚀刻形成梯形槽,所述梯形槽上宽下窄,然后氧化栅极区,形成栅极绝缘层;
步骤4、在栅极绝缘层上进行淀积,形成栅极;
步骤5、在夹断区上重新形成阻挡层,并对阻挡层蚀刻形成源区通孔,通过源区通孔进行离子注入,形成源区;
步骤6、在夹断区上重新形成阻挡层,并对阻挡层蚀刻形成源区金属通孔,通过源区金属通孔进行淀积,形成源极金属层;
步骤7、在夹断区上重新形成阻挡层,并对阻挡层蚀刻栅极金属淀积区,淀积形成栅极金属层;
步骤8、清除所有阻挡层,在碳化硅衬底的底面进行淀积,形成漏极金属层。
进一步地,所述掩蔽层的厚度为0.3~0.5微米。
进一步地,所述栅极以及栅极绝缘层的形状均为梯形。
进一步地,所述夹断区的掺杂浓度小于源区的掺杂浓度,高于漂移层的掺杂浓度。
进一步地,所述碳化硅衬底、漂移层以及源区为N型,所述夹断区为P型。
本发明的优点在于:
一、该功率器件的栅极为梯形,该梯形栅随着从源区、夹断区直至漂移区深度的增加,其宽度逐渐减小直至在最低处达到最小宽度;
二、在梯形栅下端增加掩蔽层,该掩蔽层可以将梯形栅下方的电场集中进行抵消,提高栅耐压能力;
三、该功率器件的夹断区与梯形栅相匹配,控制夹断区边界与梯形栅距离不随深度变化,从而实现良好的栅控能力;
四、该栅极与漏极对应的面积小,故其栅漏电容相应减小,可以提高器件的开关速度。
附图说明
下面参照附图结合实施例对本发明作进一步的说明。
图1是本发明一种低栅漏电容梯型栅沟槽型的功率器件的制造方法流程图一。
图2是本发明一种低栅漏电容梯型栅沟槽型的功率器件的制造方法流程图二。
图3是本发明一种低栅漏电容梯型栅沟槽型的功率器件的制造方法流程图三。
图4是本发明一种低栅漏电容梯型栅沟槽型的功率器件的制造方法流程图四。
图5是本发明一种低栅漏电容梯型栅沟槽型的功率器件的制造方法流程图五。
图6是本发明一种低栅漏电容梯型栅沟槽型的功率器件的制造方法流程图六。
图7是本发明一种低栅漏电容梯型栅沟槽型的功率器件的制造方法流程图七。
图8是本发明一种低栅漏电容梯型栅沟槽型的功率器件的制造方法流程图八。
图9是本发明一种低栅漏电容梯型栅沟槽型的功率器件的结构示意图。
具体实施方式
如图1至8所示,一种低栅漏电容梯型栅沟槽型的功率器件的制造方法,包括如下步骤:
步骤1、在具备有漂移层2的碳化硅衬底1上形成阻挡层9,并对阻挡层9蚀刻形成掩蔽层通孔,通过掩蔽层通孔进行离子注入,形成掩蔽层21,所述掩蔽层21的厚度为0.3~0.5微米;
步骤2、清除阻挡层9,在漂移层2上进行离子注入,形成夹断区3;
步骤3、在夹断区3上重新形成阻挡层9,并对阻挡层9、夹断区3、漂移层2和掩蔽层21蚀刻形成梯形槽4,所述梯形槽上宽下窄,然后氧化栅极区,形成栅极绝缘层41;
步骤4、在栅极绝缘层41上进行淀积,形成栅极5,所述栅极5以及栅极绝缘层41的形状均为梯形;
步骤5、在夹断区3上重新形成阻挡层9,并对阻挡层9蚀刻形成源区通孔,通过源区通孔进行离子注入,形成源区31;
步骤6、在夹断区3上重新形成阻挡层9,并对阻挡层9蚀刻形成源区金属通孔,通过源区金属通孔进行淀积,形成源极金属层6;
步骤7、在夹断区3上重新形成阻挡层9,并对阻挡层9蚀刻栅极金属淀积区,淀积形成栅极金属层7;
步骤8、清除所有阻挡层9,在碳化硅衬底1的底面进行淀积,形成漏极金属层8。
如图9所示,上述制造方法得到的功率器件,包括:
一碳化硅衬底1,
一漂移层2,所述漂移层2设于所述碳化硅衬底1的上侧面,所述漂移层2上设有一掩蔽层21,所述掩蔽层21的厚度为0.3~0.5微米;
一夹断区3,所述夹断区3底部连接至所述漂移层2,所述夹断区3内设有源区31;
一梯形槽4,所述梯形槽4上宽下窄(该梯形为等腰梯形,梯形的短的一端朝下),所述梯形槽4底部设于所述漂移层2上,且连接至所述掩蔽层21,所述梯形槽4穿过所述夹断区3,所述梯形槽4内设有栅极绝缘层41,该栅极绝缘层41的底部与掩蔽层21顶部连接;
一栅极5,所述栅极5连接至所述栅极绝缘层41,所述栅极5以及栅极绝缘层41的形状均为梯形;
一源极金属层6,所述源极金属层6连接至所述源区31顶部以及夹断区3顶部;
一栅极金属层7,所述栅极金属层7连接至所述栅极5;
以及,一漏极金属层8,所述漏极金属层8连接至所述碳化硅衬底1下侧面。
所述夹断区3的掺杂浓度小于源区31的掺杂浓度,高于漂移层2的掺杂浓度;所述碳化硅衬底1、漂移层2以及源区31为N型,所述夹断区3为P型。
栅极5的形状为梯形,呈现与栅极金属层7相接处为梯形长边,在漂移层2内为梯形短边。因为短边相应的面积小,可以降低栅漏电容,对于提高器件开关速度有很好的改善;
其栅极5短边处有一层掩蔽层21,该掩蔽层21将随着梯形边减小导致的栅电场的集中通过寄生的pn结进行耐压的改善,从而优化功率器件的击穿电压;
其源区31是n型重掺杂,实现源区31和源极金属层6的欧姆接触。
其夹断区3为p型掺杂,掺杂浓度要小于源区,高于漂移层;蔽层21包围了栅极绝缘层41的电场最高的底端,有效降低了栅氧的电场强度,提高了栅氧可靠性。同时降低了栅和漏的交叠面积,有效降低了栅电容,提高了器件的开关速度。
虽然以上描述了本发明的具体实施方式,但是熟悉本技术领域的技术人员应当理解,我们所描述的具体的实施例只是说明性的,而不是用于对本发明的范围的限定,熟悉本领域的技术人员在依照本发明的精神所作的等效的修饰以及变化,都应当涵盖在本发明的权利要求所保护的范围内。
Claims (5)
1.一种低栅漏电容梯型栅沟槽型的功率器件的制造方法,其特征在于,包括如下步骤:
步骤1、在具备有漂移层的碳化硅衬底上形成阻挡层,并对阻挡层蚀刻形成掩蔽层通孔,通过掩蔽层通孔进行离子注入,形成掩蔽层;
步骤2、清除阻挡层,在漂移层上进行离子注入,形成夹断区;
步骤3、在夹断区上重新形成阻挡层,并对阻挡层、夹断区、漂移层和掩蔽层蚀刻形成梯形槽,所述梯形槽上宽下窄,然后氧化栅极区,形成栅极绝缘层;
步骤4、在栅极绝缘层上进行淀积,形成栅极;
步骤5、在夹断区上重新形成阻挡层,并对阻挡层蚀刻形成源区通孔,通过源区通孔进行离子注入,形成源区;
步骤6、在夹断区上重新形成阻挡层,并对阻挡层蚀刻形成源区金属通孔,通过源区金属通孔进行淀积,形成源极金属层;
步骤7、在夹断区上重新形成阻挡层,并对阻挡层蚀刻栅极金属淀积区,淀积形成栅极金属层;
步骤8、清除所有阻挡层,在碳化硅衬底的底面进行淀积,形成漏极金属层。
2.如权利要求1所述的一种低栅漏电容梯型栅沟槽型的功率器件的制造方法,其特征在于,所述掩蔽层的厚度为0.3~0.5微米。
3.如权利要求1所述的一种低栅漏电容梯型栅沟槽型的功率器件的制造方法,其特征在于,所述栅极以及栅极绝缘层的形状均为梯形。
4.如权利要求1所述的一种低栅漏电容梯型栅沟槽型的功率器件的制造方法,其特征在于,所述夹断区的掺杂浓度小于源区的掺杂浓度,高于漂移层的掺杂浓度。
5.如权利要求1所述的一种低栅漏电容梯型栅沟槽型的功率器件的制造方法,其特征在于,所述碳化硅衬底、漂移层以及源区为N型,所述夹断区为P型。
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