CN114864704A - 具有终端保护装置的碳化硅jbs及其制备方法 - Google Patents

具有终端保护装置的碳化硅jbs及其制备方法 Download PDF

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CN114864704A
CN114864704A CN202210807542.4A CN202210807542A CN114864704A CN 114864704 A CN114864704 A CN 114864704A CN 202210807542 A CN202210807542 A CN 202210807542A CN 114864704 A CN114864704 A CN 114864704A
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王中健
曹远迎
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Abstract

本发明公开了具有终端保护装置的碳化硅JBS及其制备方法,所述装置包括碳化硅衬底,在碳化硅衬底上生长有第一外延层,在第一外延层内间隔分布有多个改善设施,在第一外延层上表面生长有第二外延层,在第二外延层内设有注入区、过渡区、保护环,保护环与改善设施在纵向方向上分布一致,环间距依次递增,在碳化硅衬底背面覆盖有欧姆金属电极,第二外延层上方覆盖有肖特基金属电极和氧化层,解决了现有技术存在的电场尖峰问题,其应用时可有效改善终端区的电场分布,缓解电场尖峰现象,提升器件的反向耐压以及可靠性。

Description

具有终端保护装置的碳化硅JBS及其制备方法
技术领域
本发明涉及半导体器件技术领域,具体涉及具有终端保护装置的碳化硅JBS及其制备方法。
背景技术
碳化硅作为宽禁带材料,可以实现较低的导通损耗,同时具有优异的耐高温性和导热特性,可满足多种应用需求。碳化硅材料的高临界场特性,使碳化硅功率器件与相同电压下的常规硅器件相比,能有更高的掺杂浓度和更薄的漂移层厚度,从而实现更低的导通电阻。碳化硅JBS结构,可在满足较高的反向耐压前提下,保持较低的导通损耗,且具有独特的零反向恢复特性,适合高频应用。
当前大多数碳化硅JBS结构,为了提升终端耐压能力,都设计了终端保护结构,包括JTE、场限环等。但对于反向耐压性能的提升依旧有限,实际使用过程中仍有部分器件发生了终端击穿现象。本发明通过二次外延,在终端结构下设置了能够优化电场分布的缓解机构,可以改善终端的电场分布,缓解电场尖峰的存在。
发明内容
本发明提供了具有终端保护装置的碳化硅JBS及其制备方法,解决了现有技术存在的电场尖峰问题,其应用时可有效改善终端区的电场分布,缓解电场尖峰现象,提升器件的反向耐压以及可靠性。
为了解决该技术问题,本发明提供了如下技术方案:
具有终端保护装置的碳化硅JBS,其特征在于,包括碳化硅衬底,在碳化硅衬底上生长有第一外延层,在第一外延层内间隔分布有多个改善设施,在第一外延层上表面生长有第二外延层,在第二外延层内设有注入区、过渡区、保护环,保护环与改善设施在纵向方向上分布一致,环间距依次递增,在碳化硅衬底背面覆盖有欧姆金属电极,第二外延层上方覆盖有肖特基金属电极和氧化层;
其中,碳化硅衬底、第一外延层、第二外延层掺杂类型为第一导电类型,注入区、过渡区、保护环的掺杂类型都为第二导电类型。
优选的,第一导电类型为N型,第二导电类型为P型。
优选的,第一导电类型为P型,第二导电类型为N型。
本方案还提供了上述具有终端保护装置的碳化硅JBS的制备方法,包括以下步骤:
S1,在碳化硅衬底上外延生长形成第一外延层;
S2,在第一外延层上表面通过介质薄膜沉积、光刻和刻蚀,形成沟槽结构,再通过沉积的方式进行填充,形成改善设施;完成沉积工艺后对掩模层进行剥离;
S3,在第一外延层上外延生长形成第二外延层;
S4,通过介质薄膜沉积、光刻,形成掩膜氧化层,通过离子注入形成注入区;
通过介质薄膜沉积、光刻,形成掩膜氧化层,通过注入形成过渡区;
使用S2相同的光刻板,通过介质薄膜沉积、光刻,形成掩膜氧化层,在第二外延层上通过离子注入形成保护环;
每次离子注入完成后对掩模层进行剥离;
S5,在第一外延层下表面通过欧姆接触方式形成欧姆金属电极,并进行退火;之后通过光刻生成的掩膜层,沉积氧化层,以保护终端结构;
在第二外延层103上表面通过肖特基接触方式形成肖特基金属电极,并进行退火处理。
优选的,步骤S2填充材料选自多晶硅、金属、氧化物中的任意一种。
优选的,所述步骤S4通过铝或硼离子注入形成P型注入区,掺杂浓度为1×1016 cm-3~5×1019 cm-3
通过铝或硼离子注入形成P型过渡区,掺杂浓度为1×1017 cm-3~1×1019 cm-3
通过铝或硼离子注入形成P型保护环,掺杂浓度为1×1018 cm-3~1×1020 cm-3
优选的,所述步骤S4通过氮或磷离子注入形成N型注入区,掺杂浓度为1×1016 cm-3~5×1019 cm-3
通过氮或磷离子注入形成N型过渡区,掺杂浓度为1×1017 cm-3~1×1019 cm-3
通过氮或磷离子注入形成N型保护环,掺杂浓度为1×1018 cm-3~1×1020 cm-3
本发明的碳化硅JBS工作时,在肖特基金属电极上施加正压或负压即可实现器件的导通,注入区、过渡区、保护环与第一外延层、第二外延层形成pin结构,增强器件的反向耐压能力。氧化层为终端结构起到保护隔离作用,改善设施则可改善终端电场分布,使其更加均匀。
本发明和现有技术相比,具有以下优点:
本发明提供了一种具有终端保护装置的碳化硅JBS,通过二次外延,在终端结构下方设计了改善设施,可有效改善终端区的电场分布,缓解电场尖峰现象,提升器件的反向耐压以及可靠性。
附图说明
此处所说明的附图用来提供对本发明实施例的进一步理解,构成本申请的一部分,并不构成对本发明实施例的限定。在附图中:
图1为本发明步骤S1完成后的碳化硅JBS结构示意图;
图2为本发明步骤S2完成后的碳化硅JBS结构示意图;
图3为本发明步骤S3完成后的碳化硅JBS结构示意图;
图4为本发明步骤S4完成后的碳化硅JBS结构示意图;
图5为本发明步骤S5完成后的碳化硅JBS结构示意图;
附图中标记及对应的零部件名称:
101、碳化硅衬底;102、第一外延层;103、第二外延层;104、注入区;105、过渡区;106、保护环;107、改善设施;108、氧化层;109、肖特基金属电极;110、欧姆金属电极。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白,下面结合实施例,对本发明作进一步的详细说明,本发明的示意性实施方式及其说明仅用于解释本发明,并不作为对本发明的限定。
实施例1
如图1所示,以第一导电类型为N,第二导电类型为P为例,本发明的具有终端保护装置的碳化硅JBS的制备方法包括以下步骤:
S1,在碳化硅衬底101上外延生长形成第一外延层102,具体如图1所示;
S2,在第一外延层102上表面通过介质薄膜沉积、光刻和刻蚀,形成沟槽结构,再通过沉积的方式进行填充,形成改善设施107。填充材料可为多晶硅、金属、氧化物,完成沉积工艺后对掩模层进行剥离,具体如图2所示;
S3,在第一外延层102上外延生长形成第二外延层103,具体如图3所示;
S4,通过介质薄膜沉积、光刻,形成掩膜氧化层,通过铝Al或硼B离子注入形成P型注入区104,掺杂浓度为1×1016 cm-3~5×1019 cm-3。同样地,形成P型过渡区105,掺杂浓度为1×1017 cm-3~1×1019 cm-3。使用S2相同的光刻板,通过介质薄膜沉积、光刻,形成掩膜氧化层,在第二外延层103上通过铝Al或硼B离子注入形成P型保护环106,掺杂浓度为1×1018 cm-3~1×1020 cm-3,该保护环与S2中的改善设施107在纵向方向上分部一致,一一对应,环间距依次递增。每次离子注入完成后都需要对掩模层进行剥离,具体如图4所示;
S5,为了防止肖特基接触在高温下损伤,需要先在第一外延层102下表面通过欧姆接触方式形成欧姆金属电极110,并进行高温退火。之后通过光刻生成的掩膜层,沉积氧化层108,以保护终端结构。另外,在第二外延层103上表面通过肖特基接触方式形成肖特基金属电极109,并进行退火处理,具体如图5所示。
通过上述方法制备得到的具有终端保护装置的碳化硅JBS如图5所示,包括碳化硅衬底101,在碳化硅衬底101上生长有第一外延层102,在第一外延层102内间隔分布有多个改善设施107,在第一外延层102上表面生长有第二外延层103,在第二外延层103内设有注入区104、过渡区105、保护环106,保护环106与改善设施107在纵向方向上分布一致,环间距依次递增,在碳化硅衬底101背面覆盖有欧姆金属电极110,第二外延层103上方覆盖有肖特基金属电极109和氧化层108;
在肖特基金属电极109上施加正压即可实现器件的导通,注入区104、过渡区105、保护环106与第一外延层102、第二外延层103形成pin结构,增强器件的反向耐压能力。氧化层108为终端结构起到保护隔离作用,改善设施107则可改善终端电场分布,使其更加均匀。
实施例2
本实施例和实施例1的区别在于,第一导电类型为P,第二导电类型为N,具体的,本发明的具有终端保护装置的碳化硅JBS的制备方法包括以下步骤:
S1,在碳化硅衬底101上外延生长形成第一外延层102,具体如图1所示;
S2,在第一外延层102上表面通过介质薄膜沉积、光刻和刻蚀,形成沟槽结构,再通过沉积的方式进行填充,形成改善设施107。填充材料可为多晶硅、金属、氧化物,完成沉积工艺后对掩模层进行剥离,具体如图2所示;
S3,在第一外延层102上外延生长形成第二外延层103,具体如图3所示;
S4,通过介质薄膜沉积、光刻,形成掩膜氧化层,通过氮N或磷P离子注入形成N型注入区104,掺杂浓度为1×1016 cm-3~5×1019 cm-3。同样地,形成N型过渡区105,掺杂浓度为1×1017 cm-3~1×1019 cm-3。使用S2相同的光刻板,通过介质薄膜沉积、光刻,形成掩膜氧化层,在第二外延层103上通过氮N或磷P离子注入形成N型保护环106,掺杂浓度为1×1018 cm-3~1×1020 cm-3,该保护环与S2中的改善设施107在纵向方向上分部一致,一一对应,环间距依次递增。每次离子注入完成后都需要对掩模层进行剥离,具体如图4所示;
S5,为了防止肖特基接触在高温下损伤,需要先在第一外延层102下表面通过欧姆接触方式形成欧姆金属电极110,并进行高温退火。之后通过光刻生成的掩膜层,沉积氧化层108,以保护终端结构。另外,在第二外延层103上表面通过肖特基接触方式形成肖特基金属电极109,并进行退火处理,具体如图5所示。
在肖特基金属电极109上施加负压即可实现器件的导通,注入区104、过渡区105、保护环106与第一外延层102、第二外延层103形成pin结构,增强器件的反向耐压能力。氧化层108为终端结构起到保护隔离作用,改善设施107则可改善终端电场分布,使其更加均匀。
以上所述的具体实施方式,对本发明的目的、技术方案和有益效果进行了进一步详细说明,所应理解的是,以上所述仅为本发明的具体实施方式而已,并不用于限定本发明的保护范围,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。

Claims (7)

1.具有终端保护装置的碳化硅JBS,其特征在于,包括碳化硅衬底(101),在碳化硅衬底(101)上生长有第一外延层(102),在第一外延层(102)内间隔分布有多个改善设施(107),在第一外延层(102)上表面生长有第二外延层(103),在第二外延层(103)内设有注入区(104)、过渡区(105)、保护环(106),保护环(106)与改善设施(107)在纵向方向上分布一致,环间距依次递增,在碳化硅衬底(101)背面覆盖有欧姆金属电极(110),第二外延层(103)上方覆盖有肖特基金属电极(109)和氧化层(108);
其中,碳化硅衬底(101)、第一外延层(102)、第二外延层(103)掺杂类型为第一导电类型,注入区(104)、过渡区(105)、保护环(106)的掺杂类型都为第二导电类型。
2.根据权利要求1所述的具有终端保护装置的碳化硅JBS,其特征在于,第一导电类型为N型,第二导电类型为P型。
3.根据权利要求1所述的具有终端保护装置的碳化硅JBS,其特征在于,第一导电类型为P型,第二导电类型为N型。
4.根据权利要求1-3任一项所述的具有终端保护装置的碳化硅JBS的制备方法,其特征在于,包括以下步骤:
S1,在碳化硅衬底(101)上外延生长形成第一外延层(102);
S2,在第一外延层(102)上表面通过介质薄膜沉积、光刻和刻蚀,形成沟槽结构,再通过沉积的方式进行填充,形成改善设施(107);完成沉积工艺后对掩模层进行剥离;
S3,在第一外延层(102)上外延生长形成第二外延层(103);
S4,通过介质薄膜沉积、光刻,形成掩膜氧化层,通过离子注入形成注入区(104);
通过介质薄膜沉积、光刻,形成掩膜氧化层,通过注入形成过渡区(105);
使用S2相同的光刻板,通过介质薄膜沉积、光刻,形成掩膜氧化层,在第二外延层(103)上通过离子注入形成保护环(106);
每次离子注入完成后对掩模层进行剥离;
S5,在第一外延层(102)下表面通过欧姆接触方式形成欧姆金属电极(110),并进行退火;之后通过光刻生成的掩膜层,沉积氧化层(108),以保护终端结构;
在第二外延层103上表面通过肖特基接触方式形成肖特基金属电极(109),并进行退火处理。
5.根据权利要求4所述的具有终端保护装置的碳化硅JBS的制备方法,其特征在于,步骤S2填充材料选自多晶硅、金属、氧化物中的任意一种。
6.根据权利要求4所述的具有终端保护装置的碳化硅JBS的制备方法,其特征在于,
所述步骤S4通过铝(Al)或硼(B)离子注入形成P型注入区(104),掺杂浓度为1×1016 cm-3~5×1019 cm-3
通过铝(Al)或硼(B)离子注入形成P型过渡区(105),掺杂浓度为1×1017 cm-3~1×1019 cm-3
通过铝(Al)或硼(B)离子注入形成P型保护环(106),掺杂浓度为1×1018 cm-3~1×1020 cm-3
7.根据权利要求4所述的具有终端保护装置的碳化硅JBS的制备方法,其特征在于,
所述步骤S4通过氮(N)或磷(P)离子注入形成N型注入区(104),掺杂浓度为1×1016 cm-3~5×1019 cm-3
通过氮(N)或磷(P)离子注入形成N型过渡区(105),掺杂浓度为1×1017 cm-3~1×1019 cm-3
通过氮(N)或磷(P)离子注入形成N型保护环(106),掺杂浓度为1×1018 cm-3~1×1020 cm-3
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115295614A (zh) * 2022-10-08 2022-11-04 成都功成半导体有限公司 一种碳化硅jfet结构及其制备方法

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006122252A2 (en) * 2005-05-11 2006-11-16 Cree, Inc. Silicon carbide junction barrier schottky diodes with suppressed minority carrier injection
US20130020671A1 (en) * 2011-07-19 2013-01-24 Alpha & Omega Semiconductor, Inc. Termination of high voltage (HV) devices with new configurations and methods
US20130249043A1 (en) * 2012-03-21 2013-09-26 Pfc Device Corp. Wide trench termination structure for semiconductor device
US20140034965A1 (en) * 2012-07-31 2014-02-06 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing same
CN103918081A (zh) * 2011-12-07 2014-07-09 住友电气工业株式会社 制造半导体器件的方法
CN104641469A (zh) * 2012-09-18 2015-05-20 株式会社电装 具有结势垒肖特基二极管的碳化硅半导体装置
EP2945192A1 (en) * 2014-05-14 2015-11-18 Nxp B.V. Semiconductive device and associated method of manufacture
CN105280723A (zh) * 2014-07-14 2016-01-27 西安永电电气有限责任公司 4H-SiC浮结结势垒肖特基二极管及其制备方法
CN108010958A (zh) * 2017-12-08 2018-05-08 北京世纪金光半导体有限公司 一种具有掩埋悬浮结和周边深沟槽保护结构的碳化硅sbd器件
CN108369963A (zh) * 2015-12-15 2018-08-03 通用电气公司 碳化硅超结功率器件的边缘终端设计
WO2019003861A1 (ja) * 2017-06-29 2019-01-03 三菱電機株式会社 酸化物半導体装置、および、酸化物半導体装置の製造方法
CN109742136A (zh) * 2018-12-30 2019-05-10 芜湖启迪半导体有限公司 一种肖特基二极管结构及其制造方法
US20210091237A1 (en) * 2019-09-24 2021-03-25 Texas Instruments Incorporated Schottky diode
CN113140639A (zh) * 2020-01-19 2021-07-20 珠海零边界集成电路有限公司 一种碳化硅功率二极管及其制作方法
CN214898450U (zh) * 2021-05-26 2021-11-26 四川蓝彩电子科技有限公司 用于超结mos器件的介质埋层保护终端
CN114497182A (zh) * 2021-12-16 2022-05-13 陕西半导体先导技术中心有限公司 一种基于体内多区终端结构的功率器件及制备方法

Patent Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006122252A2 (en) * 2005-05-11 2006-11-16 Cree, Inc. Silicon carbide junction barrier schottky diodes with suppressed minority carrier injection
CN101223647A (zh) * 2005-05-11 2008-07-16 克里公司 具有抑制的少数载流子注入的碳化硅结势垒肖特基二极管
US20130020671A1 (en) * 2011-07-19 2013-01-24 Alpha & Omega Semiconductor, Inc. Termination of high voltage (HV) devices with new configurations and methods
CN103918081A (zh) * 2011-12-07 2014-07-09 住友电气工业株式会社 制造半导体器件的方法
US20130249043A1 (en) * 2012-03-21 2013-09-26 Pfc Device Corp. Wide trench termination structure for semiconductor device
US20140034965A1 (en) * 2012-07-31 2014-02-06 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing same
CN104641469A (zh) * 2012-09-18 2015-05-20 株式会社电装 具有结势垒肖特基二极管的碳化硅半导体装置
EP2945192A1 (en) * 2014-05-14 2015-11-18 Nxp B.V. Semiconductive device and associated method of manufacture
CN105280723A (zh) * 2014-07-14 2016-01-27 西安永电电气有限责任公司 4H-SiC浮结结势垒肖特基二极管及其制备方法
CN108369963A (zh) * 2015-12-15 2018-08-03 通用电气公司 碳化硅超结功率器件的边缘终端设计
WO2019003861A1 (ja) * 2017-06-29 2019-01-03 三菱電機株式会社 酸化物半導体装置、および、酸化物半導体装置の製造方法
CN108010958A (zh) * 2017-12-08 2018-05-08 北京世纪金光半导体有限公司 一种具有掩埋悬浮结和周边深沟槽保护结构的碳化硅sbd器件
CN109742136A (zh) * 2018-12-30 2019-05-10 芜湖启迪半导体有限公司 一种肖特基二极管结构及其制造方法
US20210091237A1 (en) * 2019-09-24 2021-03-25 Texas Instruments Incorporated Schottky diode
CN113140639A (zh) * 2020-01-19 2021-07-20 珠海零边界集成电路有限公司 一种碳化硅功率二极管及其制作方法
CN214898450U (zh) * 2021-05-26 2021-11-26 四川蓝彩电子科技有限公司 用于超结mos器件的介质埋层保护终端
CN114497182A (zh) * 2021-12-16 2022-05-13 陕西半导体先导技术中心有限公司 一种基于体内多区终端结构的功率器件及制备方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
黄健华: "高压4H-SiC结势垒肖特基二极管的研究", 《中国优秀硕士学位论文全文数据库》 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115295614A (zh) * 2022-10-08 2022-11-04 成都功成半导体有限公司 一种碳化硅jfet结构及其制备方法
CN115295614B (zh) * 2022-10-08 2023-02-03 成都功成半导体有限公司 一种碳化硅jfet结构及其制备方法

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