CN1148262A - 半导体器件及其制造方法 - Google Patents
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Abstract
本发明揭示一种内装以大介电常数电介质或强电介质为电容绝缘膜的电容元件的半导体器件及其制造方法中，包括将电容绝缘膜(6)的烧结工序的烧结温度保持在650℃，利用以5℃/分或10℃/分为到达烧结温度的升温率进行烧结，形成结晶粒(7)的平均粒径为12.8nm、粒径离散的标准偏差几乎为2.2nm的结晶大小的厚度约185nm的Ba0.7Sr0.3TiO3组成的电容绝缘膜(6)。提供了可靠性好的半导体器件及其制造方法。
Description
本发明涉及内装以强电介质膜或大介电常数电介质膜为电容绝缘膜的电容元件的半导体器件及其制造方法。
近几年，随着电子设备的高速化和低电压动作化，从电子设备发出的电磁辐射的噪声成为重大的课题。作为降低这种不需要的电磁辐射的手段之一，在半导体集成电路中组装进用强电介质膜或大介电常数电介质膜(下面称为大介电常数膜)为电容绝缘膜的大容量电容元件的技术引人注目。此外，利用强电介质膜的磁滞特性，盛行着能低电压动作和高速读写的非易失性存储器的实用化研究。
下面，参照图6—图10对内装以往的电容元件的半导体器件进行说明。如图6所示，内装以往的电容元件的半导体器件主要由在制作集成电路的(未图示)支承基片1的表面上有选择地形成的白金组成的第一电极2、在该第一电极2的表面上形成的由钡锶钛氧化物(Ba0.7Sr0.3TiO3)等大介电常数组成的电容绝缘膜3和在该电容绝缘膜3的表面上不与第一电极2接触所形成的白金组成的第二电极4构成。
在这种制造方法中，首先，利用溅射或者电子束蒸镀、在支承基板1的表面上相同地形成第一电极2，接着，利用自旋喷涂法、溅射法或者化学汽相淀积(CVD)法、在其面上形成Ba0.7Sr0.3TiO3。在含氧气体的炉内以70℃/分的升温率、将其升温至650℃、并保持该温度约一个小时，使Ba0.7Sr0.3TiO3烧结、形成电容绝缘膜3。
此外，利用溅射或者电子束蒸镀、在其电容绝缘膜3的表面上相同地形成第二电极4后，利用等离子蚀刻法或者化学溶液的湿式触刻法、对第一电极2、电容绝缘膜3和第二电极4去除不要部分、形成电容元件。
图6表示由内装这种用以往的制造方法形成的电容元件的半导体器件的Ba0.7Sr0.3TiO3组成的电容绝缘膜的微细结构，图7表示放大图6所示的电容元件的部分剖面后的图。在图中，电容绝缘膜3的厚度约为185nm，电容绝缘膜3由粒径不同的大介电常数的结晶粒5构成。结晶粒5的粒径在接近第一电极2的地方小、相反地在接近第二电极4的地方大，电容绝缘膜3具有各种粒径的结晶粒。这种结晶粒5的平均粒径如图8所示大约为12nm，粒径离散的标准偏差是3.9nm。
图9是关于具备内装有这种结晶粒的微细结构的以往的电容绝缘膜3的电容元件的半导体器件、在电容元件上加上电场时得到的电流—电场特性图。在以用电场除以电流的值为纵轴、以电场的平方根为横轴的场合，用室温、100℃和150℃各温度测定时的各曲线变化成直线的区域，如图中斜线所示，在室温时出现在0.44MV/cm以上的电场区域、在100℃时出现在0.24MV/cm以上的电场区域以及在150℃时出现在0.07MV/cm以上的电场区域。下面，将该直线部分的起始电场的值称为临界电场。
在图9中用斜线覆盖的电场区域中，电容元件的电容绝缘膜中截流子的传导、受Frenkel—Poole型的跳动传导支配(例如参考嶋田等、第12次强电介质应用会议、26—Tc—11、京都、1995年)。
然而，在以往的半导体器件中，因内装的电容元件的电容绝缘膜的结晶粒径的离散性大，所以在其可靠性方面是个大课题。也就是说，为了评估具备以往的电容元件的半导体器件的可靠性，在高温条件下对电容元件外加一定时间直流电场的应力，作为加速寿命测试(下面称为高温偏置测试)，并用某一时间间隔返回到室温测定漏电流，考察其漏电流和测试时间的关系。以温度100℃、外加电场0.32MV/cm(6V电压)作为应力条件。其结果如图10所示。在图中，曲线A是具备以往的电容元件的半导体器件的测试结果，当测试时间超过数百小时时，电容元件的漏电流急剧地上升。
同样地，图10中曲线B是关于普通的标准5V动作的硅系列半导体器件，进行相同的测试、例如在MOS晶体管的栅板和漏板间加上相同的电场和温度、加速寿命测试的结果。当超过1000小时时，也几乎不见MOS晶体管阈值电压变化。
在这种内装以往的电容元件的半导体器件中，与一般的硅系列半导体器件相比，有在可靠性、也就是说稳定性方面显著劣化的课题。
本发明的目的是为解决前述以往课题、提供能最小地抑制长期间地经过内装在半导体器件中的电容元件的漏电流、因而具有良好可靠性的半导体器件及其制造方法。
为达到前述目的，本发明在内装由形成集成电路的支承基片、在该支承基片的上面有选择地形成的第一电极、在该第一电极的上面形成的由大介电常数的电介质组成的电容绝缘膜和在该电容绝缘膜的上面形成不与所述第一电极接触的第二电极组成的电容元件的半导体器件中，内装具有由所述大介电常数的电介质组成的电容绝缘膜的结晶粒平均粒径在5—20nm范围并且其平均粒径的粒径分布在标准偏差3nm以内的电容绝缘膜的电容元件。进而，为得到这种半导体器件，半导体器件的制造方法包括，在形成集成电路的支承基片的上面有选择地形成第一电极、在该第一电极的上面被复大介电常数的电介质后、在含氧气体中以0.1—10℃/分范围的任一升温度上升至烧结温度、使大介电常数的电介质结晶化、在形成电容绝缘膜后、在该电容绝缘膜的上面形成不与所述第一电极接触的第二电极的工序。
因此，采用本发明，因将大介电常数电介质在含氧气体中以0.1℃—10℃/分范围的任一升温率上升至烧结温度、使大介电常数电介质结晶化、形成电容绝缘膜、所以能在标准偏差3nm内抑制用该条件得到的结晶粒的平均粒径为中心的粒径分布，并且在高温高电场的应力下，也能降低漏电流并能确保长时间稳定。
图1表示本发明一实施例的半导体器件的电容元件的部分放大剖视图。
图2表示构成同一实施例的半导体器件的电容绝缘的结晶粒径的次数分布图。
图3表示同一半导体器件的电容元件的电流—电场特性图。
图4表示对于同一半导体器件的电容绝缘膜结晶粒径分散的标准偏差和临界电场的关系图。
图5表示同一电容绝缘膜的烧结工序的升温率和临界电场的关系图。
图6表示与以往和本发明相关的半导体器件的关键部分的剖视图。
图7表示以往的半导体器件的电容元件的部分放大剖视图。
图8表示构成同一半导体器件的电容绝缘膜的结晶粒径的次数分布图。
图9表示同一半导体器件的电容元件的电流—电场特性图。
图10表示基于以往和一般的硅系列半导体器件的高温电场外加测试的漏电和测试时间的关系图。
下面，参照图1—图5并且在其与图6和7相同部分附以相同标号、对本发明的一实施例进行说明。
实施例
具有与本发明相关的电容元件的半导体器件的结构，除电容绝缘膜的结晶结构外，与以往的半导体器件的结构相比、基本上没有变化。因其制造方法除电容绝缘膜的烧结工序外，也与以往基本相同，所以省略详细说明、仅对不同点进行说明。
图1表示放大本发明一实施例的半导体器件的部分剖视面的图。对如图所示的由白金组成的第一电极2和由相同白金组成的第二电极4之间构成的电容绝缘膜6，在3nm内形成构成它的结晶粒7的粒径分布。关于达到构成这种电容绝缘膜的原委，下面参照本发明的一实施例的半导体器件的制造方法进行说明。
首先，发明者推断了基于高温偏置试验的漏电流增大，在其应力条件的电容绝缘膜中的载流子的传导机构中的关系，决定传导机构的因素推定为电容绝缘膜的微细构造。在这里，将电容绝缘膜的烧结工序的烧结温度保持在650℃，利用分别变换到达烧结温度的升温率为5℃/分、10℃/分、20℃/分、50℃/分和70℃/分，考察得到的电容绝缘膜的各种结晶的微细结构。
其结果，能得到有在升温率为5℃/分或10℃/分烧结的场合，如图1所示，结晶粒7的大小为几乎整齐的厚度约185nm的Ba0.7Sr0.3TiO3组成的电容绝缘膜的电容元件。然后，在本实施例得到的半导体器件的漏电流的负载寿命测试结果，如图10所示，可见与用曲线B表示的一般的硅系列半导体器件的稳定特征，有几乎相同的结果。
在本实施例中，构成得到的电容绝缘膜6的结晶粒7的粒径的次数分布，表示在图2中。由图可见，结晶粒7的平均粒径是12.8nm，虽然与以往的电容绝缘膜几乎相同，但标准偏差为2.2nm，比图8所示的以往的电容绝缘膜的标准偏差要小。
图3表示关于本实施例的半导体器件在电容元件上加上电场时得到的电流—电场特性图。150℃的临界电场强度，从以往的电容元件的0.07MV/cm大幅度地上升到0.38MV/cm。此外，100℃的临界电场强度为0.43MV/cm、室温的临界电场强度为0.5MV/cm，比任何以往的内装在半导体器件中的电容元件的临界电场强度都要上升。由图3可见，前述高温偏置测试条件(6V、125℃)，为本实施例具有的临界电场强度以下，因此，内装本实施例的电容元件的半导体器件，具有稳定的漏电流特性。
这样，虽然漏电流特性是否稳定，基于高温偏置测试条件是否为临界电场强度以下，但因临界电场强度高的话，高稳定的区域增加，所以关于用于提高临界电场强度的要素进行了考察。
如前述实施例所见，本发明的结构与以往的电容绝缘膜的不同点在于，大介电常数电介质的结晶粒径的标准偏差，对于以往为3.9，在本实施例中为2.2，发明者为了解释对其不同点给与的影响，考察了对结晶粒径分散标准偏差和150℃的临界电场的相互关系。其结果如图4所示。由图可见，虽然临界电场强度在电容绝缘膜的结果粒径的标准偏差到3nm为至几乎不变，但超过3nm时，急剧地减小。也就是说，在高温偏置测试中为得到稳定的漏电流特性，有必要将结晶粒径的标准偏差抑制在3nm以下。
图5表示电容绝缘膜6的烧结工序的升温率和150℃的临界电场强度的关系图。由图可见，当烧结时的升温率超过10℃/分时，临界电场强度急剧地减小。也就是说，结晶粒径分散的标准偏差减小，为得到稳定的漏电流特性，电容绝缘膜的烧结工序的升温率必需在0.1—10℃/分的范围内。
此外，关于本实施例的半导体器件，虽然关于用Ba0.7Sr0.3TiO3作为电容绝缘膜6的例子进行了说明，但Ba和Sr的克分子比，不仅能得到在本实施例的数值，而且也能得到何种配合比能有相同的效果。而且，不限于Ba0.7Sr0.3TiO3，能使用多种钙钛矿型大介电常数材料作为电容绝缘膜。此外，在本发明的实施例中，虽然以Frenkel—Poole型的跳动传导为支配的临界电场进行定义并演绎作为与电容绝缘膜的稳定性相关的解析理论，但电容绝缘膜的稳定性，以时间依存绝缘破坏(TDDB)和绝缘耐压作为评价的指标进行解析，也能得到相同的结果。
这样，采用前述实施例，将构成电容绝缘膜的大介电常数电介质，在含氧气体中以5℃或者10℃/分的升温率，上升到达烧结温度，使大介电常数电介质结晶化，形成电容绝缘膜，并且以结晶粒的平均粒径为中心的粒径分为在标准偏差2.2nm，在高温高电场的应力下，也能降低漏电流并能确保长时间稳定。
本发明因在内装由形成集成电路的支承基片、在该支承基片的上面有选择地形成的第一电极、在该第一电极的上面形成的由大介电常数的电介质组成的电容绝缘膜和在该电容绝缘膜的上面形成不与所述第一电极接触的第二电极组成的电容元件的半导体器件中，内装具有由所述大介电常数的电介质组成的电容绝缘膜的结晶粒平均粒径在5—20nm范围并且其平均粒径的粒径分布在标准偏差3nm以内的电容绝缘膜的电容元件，所以能长时间地经过该电容元件的漏电流并保持稳定，能显著地改善半导体器件的可靠性。
Claims (2)
1.一种半导体器件，包括：内装由形成集成电路的支承基片、在该支承基片的上面有选择地形成的第一电极、在该第一电极的上面形成的由大介电常数电介质组成的电容绝缘膜和在该电容绝缘膜的上面形成不与所述第一电极接触的第二电极组成的电容元件，其特征在于，具有由所述大介电常数电介质组成的电容绝缘膜的结晶粒平均粒径在5—20nm范围并且其平均粒径的粒径分布在标准偏差3nm以内的电容绝缘膜的电容元件。
2.一种半导体器件的制造方法，其特征在于，在形成集成电路的支承基片的上面有选择地形成第一电极、在该第一电极的上面被复大介电常数电介质后、在含氧气体中以0.1—10℃/分范围的任一升温率上升至烧结温度、使大介电常数电介质结晶化、在形成电容绝缘膜后、在该电容绝缘膜的上面形成不与所述第一电极接触的第二电极。
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| Application Number | Priority Date | Filing Date | Title |
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| JP07155921A JP3135483B2 (ja) | 1995-06-22 | 1995-06-22 | 半導体装置およびその製造方法 |
| JP155921/95 | 1995-06-22 |
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| CN1148262A true CN1148262A (zh) | 1997-04-23 |
| CN1082718C CN1082718C (zh) | 2002-04-10 |
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| CN96107136A Expired - Fee Related CN1082718C (zh) | 1995-06-22 | 1996-06-21 | 半导体器件及其制造方法 |
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| US (2) | US5828098A (zh) |
| EP (1) | EP0755070B1 (zh) |
| JP (1) | JP3135483B2 (zh) |
| KR (1) | KR100240819B1 (zh) |
| CN (1) | CN1082718C (zh) |
| DE (1) | DE69625132T2 (zh) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1315191C (zh) * | 2003-09-02 | 2007-05-09 | 松下电器产业株式会社 | 电容元件及半导体存储装置 |
| CN1321442C (zh) * | 2003-03-26 | 2007-06-13 | 精工爱普生株式会社 | 强电介质膜、电容器及它们的制造方法及强电介质存储器 |
| US7910981B2 (en) | 2006-10-03 | 2011-03-22 | Macronix International Co., Ltd. | Semiconductor device and method of manufacturing the same |
| CN111063672A (zh) * | 2018-10-17 | 2020-04-24 | 三星电子株式会社 | 电容器和具有其的半导体装置 |
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| JP3022328B2 (ja) * | 1996-06-19 | 2000-03-21 | 日本電気株式会社 | 薄膜形成方法 |
| GB2338962B (en) * | 1996-06-19 | 2000-11-29 | Nec Corp | Thin film formation method |
| KR100275121B1 (ko) * | 1997-12-30 | 2001-01-15 | 김영환 | 강유전체 캐패시터 제조방법 |
| KR100277845B1 (ko) * | 1998-01-14 | 2001-02-01 | 김영환 | 비휘발성강유전체메모리소자및그제조방법 |
| TW404021B (en) * | 1998-04-09 | 2000-09-01 | Hitachi Ltd | Semiconductor memory device and manufacturing method thereof |
| JP2000236075A (ja) * | 1999-02-12 | 2000-08-29 | Sony Corp | 誘電体キャパシタの製造方法および半導体記憶装置の製造方法 |
| JP2002170938A (ja) * | 2000-04-28 | 2002-06-14 | Sharp Corp | 半導体装置およびその製造方法 |
| JP2004031728A (ja) * | 2002-06-27 | 2004-01-29 | Matsushita Electric Ind Co Ltd | 記憶装置 |
| JP2005294314A (ja) * | 2004-03-31 | 2005-10-20 | Tdk Corp | 積層セラミックコンデンサ |
| EP1693840A1 (en) * | 2005-02-17 | 2006-08-23 | Samsung Electronics Co., Ltd. | Data recording medium including ferroelectric layer and method of manufacturing the same |
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| US4466177A (en) * | 1983-06-30 | 1984-08-21 | International Business Machines Corporation | Storage capacitor optimization for one device FET dynamic RAM cell |
| JPH04206872A (ja) * | 1990-11-30 | 1992-07-28 | Matsushita Electric Ind Co Ltd | 半導体装置 |
| US5514822A (en) * | 1991-12-13 | 1996-05-07 | Symetrix Corporation | Precursors and processes for making metal oxides |
| JP3206105B2 (ja) * | 1992-06-09 | 2001-09-04 | セイコーエプソン株式会社 | 誘電体素子の製造方法及び半導体記憶装置 |
| JPH0629462A (ja) * | 1992-07-07 | 1994-02-04 | Fujitsu Ltd | 誘電体薄膜の形成方法 |
| JPH0777237B2 (ja) * | 1993-01-04 | 1995-08-16 | 日本電気株式会社 | 半導体記憶装置及びその製造方法 |
| EP0739030A3 (en) * | 1995-04-19 | 1998-07-08 | Nec Corporation | Highly-integrated thin film capacitor with high dielectric constant layer |
| KR100209748B1 (ko) * | 1996-01-10 | 1999-07-15 | 구본준 | 반도체 장치의 축전기 제조방법 |
| US5930639A (en) * | 1996-04-08 | 1999-07-27 | Micron Technology, Inc. | Method for precision etching of platinum electrodes |
-
1995
- 1995-06-22 JP JP07155921A patent/JP3135483B2/ja not_active Expired - Fee Related
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1996
- 1996-06-20 US US08/667,913 patent/US5828098A/en not_active Expired - Fee Related
- 1996-06-21 EP EP96110025A patent/EP0755070B1/en not_active Expired - Lifetime
- 1996-06-21 CN CN96107136A patent/CN1082718C/zh not_active Expired - Fee Related
- 1996-06-21 DE DE69625132T patent/DE69625132T2/de not_active Expired - Fee Related
- 1996-06-22 KR KR1019960023034A patent/KR100240819B1/ko not_active IP Right Cessation
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1321442C (zh) * | 2003-03-26 | 2007-06-13 | 精工爱普生株式会社 | 强电介质膜、电容器及它们的制造方法及强电介质存储器 |
| CN1315191C (zh) * | 2003-09-02 | 2007-05-09 | 松下电器产业株式会社 | 电容元件及半导体存储装置 |
| US7910981B2 (en) | 2006-10-03 | 2011-03-22 | Macronix International Co., Ltd. | Semiconductor device and method of manufacturing the same |
| US8207571B2 (en) | 2006-10-03 | 2012-06-26 | Macronix International Co., Ltd. | Non-volatile memory device with a threshold voltage change rate controlled by gate oxide phase |
| US8378410B2 (en) | 2006-10-03 | 2013-02-19 | Macronix International Co., Ltd. | Semiconductor device and method of manufacturing the same |
| CN111063672A (zh) * | 2018-10-17 | 2020-04-24 | 三星电子株式会社 | 电容器和具有其的半导体装置 |
| CN111063672B (zh) * | 2018-10-17 | 2024-05-14 | 三星电子株式会社 | 电容器和具有其的半导体装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| KR970003930A (ko) | 1997-01-29 |
| US6033920A (en) | 2000-03-07 |
| CN1082718C (zh) | 2002-04-10 |
| DE69625132T2 (de) | 2003-10-09 |
| DE69625132D1 (de) | 2003-01-16 |
| EP0755070B1 (en) | 2002-12-04 |
| JPH098246A (ja) | 1997-01-10 |
| JP3135483B2 (ja) | 2001-02-13 |
| EP0755070A3 (en) | 1997-08-13 |
| KR100240819B1 (ko) | 2000-01-15 |
| EP0755070A2 (en) | 1997-01-22 |
| US5828098A (en) | 1998-10-27 |
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