CN114765124A - 用于制造半导体封装件的夹具和半导体封装件的制造方法 - Google Patents
用于制造半导体封装件的夹具和半导体封装件的制造方法 Download PDFInfo
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Abstract
用于制造半导体封装件的夹具包括底部件和上部件。底部件包括基底、支撑板和至少一个弹性连接件。支撑板位于基底的中心区域中。至少一个弹性连接件介于支撑板和基底之间。上部件包括帽和外法兰。当上部件设置在底部件上时,帽位于支撑板上面。外法兰设置在帽的边缘处,与帽连接。当上部件设置在底部件上时,外法兰接触底部件的基底。帽包括开口,该开口是通孔。当上部件设置在底部件上时,开口的垂直投影完全落在支撑板上。本申请的实施例还涉及半导体封装件的制造方法。
Description
技术领域
本申请的实施例涉及用于制造半导体封装件的夹具和半导体封装件的制造方法。
背景技术
通常在单个半导体晶圆上制造在诸如手机和其它移动电子设备的各种电子设备中使用的半导体器件和集成电路。晶圆的管芯可以与晶圆级的其它半导体器件或管芯一起处理和封装,并且已经开发了用于晶圆级封装的各种技术和应用。多个半导体器件的集成已经成为该领域中的挑战。为了响应对小型化、更高速度和更好的电性能(例如,更低的传输损耗和插入损耗)的日益增长的需求,积极研究了更具创造性的封装和组装技术。
发明内容
本申请的一些实施例提供了一种用于制造半导体封装件的夹具,包括:底部件包括:基底;支撑板,位于所述基底中心区域中;以及至少一个弹性连接件,介于所述支撑板和所述基底之间;以及上部件,包括:帽,当所述上部件设置在所述底部件上时,位于所述支撑板上面;以及外法兰,设置在所述帽的边缘处,与所述帽连接,并且当所述上部件设置在所述底部件上时接触所述底部件的所述基底,其中,所述帽包括开口,所述开口是通孔,并且,当所述上部件设置在所述底部件上时,所述开口的竖直投影完全落在所述支撑板上。
本申请的另一些实施例提供了一种制造半导体封装件的方法,包括:将半导体管芯接合至电路衬底;将具有所述接合的半导体管芯的所述电路衬底放置在夹具的底部件的支撑板上;将所述夹具的上部件放置在所述底部件上以关闭所述夹具,从而将所述半导体管芯压靠在所述夹具的上部件上,其中,所述夹具的所述上部件包括开口,并且所述半导体管芯的背面由所述开口暴露;在所述开口内的所述半导体管芯的所述背面上沉积导热材料;以及去除所述上部件以打开所述夹具。
本申请的另一些实施例提供了一种制造半导体封装件的方法,包括:在接合至所述电路衬底的至少一个半导体管芯旁边的所述电路衬底上设置粘合材料;将金属覆盖物放置在所述粘合材料上,由此所述金属覆盖物在所述半导体管芯上方延伸;将所述电路衬底设置在夹具的底部件上;将所述夹具的上部件设置在所述夹具的所述底部件上方;将所述夹具的所述上部件拧紧至所述夹具的所述底部件,从而将所述金属覆盖物压靠在所述电路衬底和所述半导体管芯上;以及在所述夹具将所述金属覆盖物压靠在所述电路衬底和所述半导体管芯上的同时固化所述粘合材料。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各个方面。应该指出,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1A至图1M是示出根据本发明的一些实施例的在半导体封装件的制造工艺期间产生的结构的示意性截面图。
图2A至图2G是根据本发明的一些实施例的用于制造半导体封装件的夹具的示意性立体图。
图3是根据本发明的一些实施例的设置在载体上的夹具的示意性顶视图。
图4是根据本发明的一些实施例的用于制造半导体封装件的夹具的示意性立体图。
图5是根据本发明的一些实施例的用于制造半导体封装件的夹具的示意性立体图。
图6A至图6C是示出根据本发明的一些实施例的在半导体封装件的制造工艺期间产生的结构的示意性截面图。
图7是根据本发明的一些实施例的用于制造半导体封装件的夹具的示意性立体图。
图8是根据本发明的一些实施例的用于制造半导体封装件的夹具的示意性截面图。
图9A至图9C是根据本发明的一些实施例的用于制造半导体封装件的夹具的一些组件的示意性截面图。
图10A和图10B是根据本发明的一些实施例的用于制造半导体封装件的夹具的示意性截面图。
图11A至图11F是根据本发明的一些实施例的在半导体封装件的制造方法期间形成的结构的示意性截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为了便于描述,在此可以使用诸如“在…之下”、“在…下方”、“底部件”、“在…上方”、“上部”等空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其它方式定向(旋转90度或在其它方位上),而本文使用的空间相对描述符可以同样地作出相应的解释。
也可以包括其它部件和工艺。例如,可以包括测试结构以帮助对3D封装件或3DIC器件进行验证测试。测试结构可以包括例如形成在再分布层中或衬底上的测试焊盘,它允许测试3D封装件或3DIC器件、使用探针和/或探针卡等。验证测试可以在中间结构以及最终结构上实施。此外,本文公开的结构和方法可以与结合了已知良好管芯的中间验证的测试方法结合使用,以增加良率并且降低成本。
图1A至图1M是示出根据本发明的一些实施例的在半导体封装件SP10的制造工艺期间产生的结构的示意性截面图。参考图1A,提供了载体C。在一些实施例中,载体C是玻璃衬底、金属板、塑料支撑板等,但是可以使用其它合适的衬底材料,只要该材料能够承受该工艺的随后步骤。在一些实施例中,可以在载体C上方形成剥离层(未示出)。在一些实施例中,剥离层包括光热转换(LTHC)释放层,当制造工艺需要时,该剥离层有助于将载体C从半导体封装件剥离。
在一些实施例中,在载体C上形成外部再分布层100。在一些实施例中,外部再分布层100包括与一个或多个金属化层120交替堆叠的介电层110。在一些实施例中,介电层110至少包括两个介电层。金属化层120包括夹在成对的相邻介电层110之间的布线导电迹线。在一些实施例中,介电层110的材料包括聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂,苯并环丁烯(BCB)、聚苯并恶唑(PBO)、任何其它合适的基于聚合物的介电材料或它们的组合。介电层110可以通过诸如旋涂、化学汽相沉积(CVD)等的合适的制造技术来形成。在一些实施例中,金属化层120的材料包括铜、铝等。在一些实施例中,金属化层120的材料包括铜。在整个说明书中,术语“铜”旨在包括基本纯的元素铜、包含不可避免的杂质的铜以及包含诸如钽、铟、锡、锌、锰、铬、钛、锗、锶、铂、镁、铝或锆的元素的铜合金。金属化层120可以通过例如电镀、沉积和/或光刻和蚀刻来形成。在一些可选实施例中,可以形成比图1A所示的更多的金属化层120和更多的介电层110,取决于生产需求。在这些实施例中,每个金属化层夹在一对连续的介电层之间。在一些实施例中,图案化进一步远离载体C的介电层110以包括暴露金属化层120的更远离载体C的部分的开口130。在一些实施例中,可以在重构晶圆水平实施该工艺,使得以重构晶圆的形式处理多个封装单元PU。在图1A的截面图中,为简单起见示出了两个封装单元PU,但是,当然,这仅是出于说明的目的,并且本发明不限于在重构晶圆中生产的封装单元PU的数量。
参考图1B,在一些实施例中,在外部再分布层100上提供TIV 210和半导体桥220。在一些实施例中,TIV 210可以通过利用导电材料填充图案化掩模(未示出)的开口来形成。在一些实施例中,TIV 210的导电材料包括钴(Co)、钨(W)、铜(Cu)、钛(Ti)、钽(Ta)、铝(Al)、锆(Zr)、铪(Hf)、它们的组合或其它合适的金属材料。在一些实施例中,导电材料可以通过镀工艺形成。镀工艺可以是例如电镀、化学镀、浸镀等。在一些实施例中,可以在晶种层(未示出)上沉积导电材料。在一些实施例中,可以跳过晶种层的形成,因为金属化层120可以作为沉积导电材料的晶种。但是,本发明不限于此。在一些可选实施例中,其它合适的方法可以用于形成TIV 210。例如,可以拾取和放置接合至外部再分布层100上的预制的TIV 210(例如,预制的导电柱)。
在一些实施例中,半导体桥220设置在TIV 210之间的外部再分布层100上。半导体桥220接合至金属化层120的一些布线导电迹线。在一些实施例中,半导体桥220包括半导体衬底221,具有穿过其形成的半导体通孔(TSV)222和互连导电图案223。介电层224可以设置在半导体桥220的底面220b处,更靠近外部再分布层100。半导体衬底221可以由合适的半导体材料制成,诸如元素周期表的III-V族的半导体材料。在一些实施例中,半导体衬底221包括:元素半导体材料,诸如硅或锗;化合物半导体材料,诸如碳化硅、砷化镓、砷化铟或磷化铟;或合金半导体材料,诸如硅锗、碳化硅锗、磷砷化镓或磷化铟镓。互连导电图案223与形成在半导体桥220的底面220b处的介电层224上的导电端子225电接触。导电端子225可以是微凸块。例如,导电端子225可以包括导电杆和设置在导电杆上的焊帽。在一些实施例中,导电杆可以是铜杆。但是,本发明不限于此,并且诸如焊料凸块或金属凸块(例如,金凸块)的其它导电结构也可以用作导电端子225。在一些实施例中,半导体桥220设置为底面220b指向外部再分布层100,使得导电端子225可以接合至金属化层120。导电端子225可以例如通过回流工艺接合至金属化层120。
在一些实施例中,在外部再分布层100上形成密封剂230,从而密封TIV 210和半导体桥220。在一些实施例中,密封剂230通过过模制工艺(例如,通过压缩模制工艺)形成。密封剂230可以最初覆盖TIV 210和半导体桥220的顶面220t。在一些实施例中,密封剂230的材料包括模塑料、聚合材料,诸如聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、苯并环丁烯(BCB)、聚苯并恶唑(PBO)、它们的组合或其它合适的基于聚合物的介电材料。在一些实施例中,密封剂230可以通过过模制工艺形成,首先覆盖TIV 210和半导体桥220,并且随后可以减薄直至暴露TIV 210和半导体桥220的顶面220t。例如,可以实施平坦化工艺,从顶面220t、210t的侧去除密封剂230的部分以及(如果需要)半导体桥220的部分和/或TIV 210的部分。在一些实施例中,平坦化密封剂230包括实施机械研磨工艺和/或化学机械抛光(CMP)工艺。在平坦化之后,TIV 210的顶面210t、半导体桥220的顶面220t以及密封剂230的顶面230t可以相对于彼此基本齐平(处于基本相同的水平高度,相对于彼此共面)。在一些实施例中,TIV 210、半导体桥220和密封剂230被认为是桥接层200的堆叠在外部再分布层100上的部分。即,半导体桥220和TIV 210嵌入在桥接层200中。
参考图1C,在桥接层200上形成内部再分布层300。内部再分布层300包括介电层310、一个或多个金属化层320以及(可选地)凸块下金属330。内部再分布层300可以具有与先前针对外部再分布层100所描述的结构类似的结构并且按照与先前针对外部再分布层100所描述的工艺类似的工艺形成。在一些实施例中,图案化(最上部)介电层310以暴露下面的金属化层320。可选地在(最上部)介电层310的暴露金属化层320的开口中共形形成可以进一步在(最上部)介电层310的暴露表面的部分上方延伸的凸块下金属330。在一些实施例中,凸块下金属330包括导电材料的多个堆叠层。例如,凸块下金属330可以包括堆叠在晶种层上的一个或多个金属层。在一些实施例中,外部再分布层100、桥接层200和内部再分布层300可以统称为再分布结构。
参考图1D,在一些实施例中,半导体管芯410、420利用拾取和放置工艺并排设置在内部再分布层300上方。在一些实施例中,半导体管芯410、420是密封的芯片。例如,半导体管芯410可以包括具有在其上接合的芯片413的一个或多个堆叠件的基底芯片411。芯片413可以垂直堆叠,并且通过微凸块415在堆叠件内互连。密封剂417可以设置在基底芯片411上,以密封芯片413的堆叠件和微凸块415。连接件419可以在相对于芯片413的相对侧处设置在基底芯片411上。半导体管芯420可以具有与半导体管芯410类似的结构,包括基底芯片421、由微凸块425互连的堆叠芯片423、密封芯片423和微凸块425的密封剂427以及连接件429。
在一些实施例中,在内部再分布层300上放置半导体管芯410、420,其中在其上形成的基底芯片411、421的具有连接件419、429的侧指向内部再分布层300。半导体管芯410、420的背面410r、420r可以包括堆叠件的最顶部芯片413、423的背面和密封剂417、427的顶面。在一些实施例中,包括在半导体封装件中的半导体管芯410、420可以具有不同的尺寸、包括不同的组件和/或包括不同尺寸的组件。例如,半导体管芯410、420可以因包括的芯片413、423的数量、包括的堆叠芯片413、423或基底芯片411、421的类型等等而不同。每个半导体管芯410、420可以独立地是或包括逻辑管芯,诸如中央处理单元(CPU)管芯、图形处理单元(GPU)管芯、微控制单元(MCU)管芯、输入/输出(I/O)管芯、基带(BB)管芯或应用处理器(AP)管芯。在一些实施例中,半导体管芯410、420中的一个或两个可以是存储器管芯。
在一些实施例中,半导体桥220的互连导电图案223电连接相同封装单元PU的半导体管芯410和420。即,半导体管芯410和420之间的电连接通过内部再分布层300和互连导电图案223来建立。在一些实施例中,内部再分布层300不直接互连半导体管芯410、420。在一些实施例中,半导体桥220将金属化层320的电连接至半导体管芯410的至少一个导电迹线连接至金属化层320的连接至半导体管芯420的另一导电迹线。在一些实施例中,半导体桥220将与半导体管芯410重叠的一个或多个导电迹线与与半导体管芯420重叠的一个或多个导电迹线连接。在一些实施例中,在相邻半导体管芯410、420之间存在间隙的情况下,半导体桥220在该间隙上方延伸。在一些实施例中,半导体桥220用作用于相邻半导体管芯410、420的互连结构,并且在相邻半导体管芯410、420之间提供较短电连接路径。
在一些实施例中,在内部再分布层300上方形成密封剂500,以密封半导体管芯410、420。密封剂500横向环绕半导体管芯410、420,也在半导体管芯410、420之间的间隙中延伸。在一些实施例中,可以如以上针对密封剂230所描述的那样选择密封剂500的材料。密封剂500可以通过一系列的过模制和平坦化步骤来形成。例如,密封剂500最初可以通过模制工艺(诸如压缩模制工艺)或旋涂工艺形成,以完全覆盖半导体管芯410、420。在一些实施例中,平坦化密封剂500包括实施机械研磨工艺和/或化学机械抛光(CMP)工艺。在一些实施例中,实施平坦化工艺,直至暴露半导体管芯410、420的背面410r、420r。在一些实施例中,在平坦化工艺之后,半导体管芯410、420的背面410r、420r和密封剂500的顶面500t沿Z方向可以基本处于相同的水平高度(基本共面)。
参考图1D和图1E,在一些实施例中,第二载体C1可以接合在密封剂的顶面500t的侧上,可以翻转重构晶圆,可以去除原始载体C以暴露外部再分布层100用于进一步处理。当包括剥离层(例如,LTHC释放层)时,可以利用UV激光照射剥离层,使得载体C和剥离层易于从重构晶圆剥离。然而,剥离工艺不限于此,并且在一些可选实施例中可以使用其它合适的剥离方法。可以在外部再分布层100中形成开口,以在相对于TIV 210和半导体桥220的相对侧处暴露金属化层120。在外部再分布层100上提供连接端子600之前,可以在开口中可选地形成与金属化层120接触的凸块下金属140。可以在凸块下金属140(如果包括)或金属化层120的暴露的部分上形成连接端子600。在一些实施例中,在凸块下金属140上形成通过外部再分布层100、半导体桥220(例如,穿过TSV 222)、TIV 210和内部再分布层300连接至半导体管芯410、420的连接端子600。在一些实施例中,连接端子600通过助焊剂附接至凸块下金属140。在一些实施例中,连接端子600是可控塌陷芯片连接(C4)凸块。在一些实施例中,连接端子600包括具有低电阻率的导电材料,诸如Sn、Pb、Ag、Cu、Ni、Bi或它们的合金。
在一些实施例中,参考图1E和图1F,例如,通过沿布置在各个封装单元PU之间的划线道SC切割,实施分割步骤以将多个封装的管芯10中的各个封装单元PU分离。在一些实施例中,分割工艺通常包括利用旋转刀片和/或激光束实施晶圆切割工艺。在一些实施例中,在分割之后,载体C1与封装的管芯10分离。
参考图1G,在一些实施例中,封装的管芯10可以通过连接端子600连接至电路衬底700。例如,封装的管芯10可以设置在电路衬底700上,并且可以实施焊接步骤。在一些实施例中,电路衬底700包括具有嵌入在其中的导电迹线720的芯介电层710。上焊料掩模730可以设置在电路衬底700的上侧700a上,在设置封装的管芯10的相同侧700a处。焊料掩模730可以在芯介电层710上延伸,并且可以包括暴露最外导电迹线720的开口。封装的管芯10的连接端子600可以设置在焊料掩模730的开口中以接触导电迹线720。在一些实施例中,可选地在封装的管芯10和电路衬底700之间提供底部填充物800。底部填充物800可以横向包裹连接端子600,例如,以保护连接端子600免受机械应力。在一些实施例中,另一焊料掩模740可以设置在电路衬底700的底侧700b处的芯介电层710上。
在一些实施例中,在电路衬底700的在封装的管芯10旁边的上侧700a上提供无源器件900。在一些实施例中,通过拾取和放置方法将无源器件900放置在电路衬底700上方。在一些实施例中,无源器件900是集成无源器件的芯片,并且用作电容器、电感器、电阻器等。在一些实施例中,每个无源器件900可以独立地用作具有不同电容值、谐振频率和/或不同尺寸的电容器、电感器等。在一些实施例中,无源器件900设置为正面指向电路衬底700,以便与电路衬底700的导电迹线720连接。在一些实施例中,封装的管芯10、电路衬底700、底部填充物800和无源器件900可以统称为封装模块PM1。半导体管芯410、420的背面410r、420r可以是封装模块PM1的顶面的一部分。虽然为了说明的目的在图1G中仅在封装模块PM1内呈现了两个无源器件900,但是本发明不限于封装模块PM1中包括的无源器件900的数量。实际上,本发明不限制封装模块PM1的可能结构。虽然在附图中示出了封装模块PM1以呈现本发明的一些方面,但是与图1A至图1G中针对封装模块PM1示出的不同的结构或利用不同的制造工艺制造的封装模块在本发明的范围内。
图2A是根据本发明的一些实施例的用于制造半导体封装件的夹具1000A的示意性立体图。图3是根据本发明的一些实施例的设置在载体C2上的夹具1000A的示意性顶视图。参考图1H、图2A和图3,在一些实施例中,夹具1000A的一个或多个底部件1010可以例如以阵列方式设置在载体C2上。显而易见,虽然在图3中示出了六个夹具1000A,但是本发明不限于设置在载体C2上的夹具1000A的数量。在一些实施例中,夹具1000A包括底部件1010、舟形件1030和上部件1040。夹具1000A的底部件1010可以最初设置在载体C2上,并且对应的舟形件1030可以设置在底部件1010上。一个或多个封装模块PM1可以设置在夹具1000A的底部件1010上,并且可以由舟形件1030保持在适当的位置。在一些实施例中,封装模块PM1设置在夹具1000A的底部件1010上,其中电路衬底700指向夹具1000A的底部件1010。例如,当封装模块PM1设置在夹具1000A上时,电路衬底700可以延伸通过舟形件1030以接触夹具1000A的底部件1010。虽然在图3中八个封装模块PM1设置在夹具1000A上,但是每个夹具1000A的封装模块PM1的数量不受限制。在一些可选实施例中,更少或更多的封装模块PM1可以设置在同一夹具1000A上。在一些实施例中,图1H至图1M的截面图可以被认为是在对应于图3中的线I-I’的位置处截取。
在一些实施例中,夹具1000A的底部件1010包括基底1012,并且可以包括形成在基底1012的中心区域中的一个或多个平台1014。在一些实施例中,平台1014相对于基底1012的顶面升高(沿Z方向)。在一些实施例中,基底1012呈现出环绕平台1014的外围区域。在一些实施例中,基底1012的外围区域可以被认为是在夹具1000A的外边缘附近环绕平台1014的环形区域。在一些实施例中,基底1012的在相邻的平台1014之间的平坦区域也可以被认为是基底1012的外围区域的一部分。在一些实施例中,弹簧1016可以设置在每个平台1014上,以支持支撑板1018。在一些实施例中,设置在平台1014上的弹簧1016的数量不受特别限制,并且可以例如在0和200之间。在一些实施例中,封装模块PM1设置在弹簧1016上方的支撑板1018上。在一些实施例中,具有对应的支撑板1018的平台1014可以与要设置在夹具1000A上的封装模块PM1的数量一样多,使得每个封装模块PM1可以具有专用的平台1014和支撑板1018。在一些实施例中,磁体1020可以嵌入在基底1012中。例如,磁体1020可以固定在基底1012的环形外围区域中。在一些实施例中,磁体设置为彼此以规则的间隔沿基底1012的边缘。在一些实施例中,磁体1020的一个表面与基底1012的顶面相对应地暴露。但是,磁体1020可以嵌入在基底1012中,使得基底1012的顶面除了平台1014之外可以基本平坦,即使在暴露磁体1020的地方。
在一些实施例中,在设置封装模块PM1之前,舟形件1030设置在底部件1010上。舟形件1030包括具有形成在其中的一个或多个封装开口1034的主体1032。主体1032可以是整体块,例如具有矩形覆盖区的平行六面体块。封装开口1034是具有与封装模块PM1的覆盖区基本匹配的覆盖区的通孔。封装开口1034可以比封装模块PM1稍大,使得封装模块PM1可以容纳在封装开口1034内并且保持在底部件1010上的适当的位置。在一些实施例中,夹具1000A的舟形件1030可以包括与平台1014和支撑板1018一样多的封装开口1034。例如,附图中所示的舟形件1030包括八个封装开口1034。在一些实施例中,可以在底部件1010和舟形件1030之间提供对准机构。例如,可以在支撑板1018上形成对准销1019,在支撑板1018的一个或多个角处。可以在主体1032中形成对准孔1036,在选择的准置处,以便当对准销1019插入对准孔1036中时在底部件1010和舟形件1030之间提供正确的对准。在图2A中,在封装开口1034的四个角处形成对准孔1036,在支撑板1018的四个角处形成对准销1019。但是,本发明不限于此。在一些可选实施例中,可以在支撑板1018上形成更少的对准销1019(和对应的对准孔1036)。例如,可以仅在支撑板1018的一些角处(例如,在一个、两个或三个角处)形成对准销1019。作为实例,在图2B中示出了根据本发明的一些实施例的夹具1000B的立体图。夹具1000B类似于图2A的夹具1000A。夹具1000B和图2A的夹具1000A之间的区别可以是在支撑板1018上形成两个对准销1019。如图2B所示,可以在支撑板1018的不同位置处形成对准销1019。在一些实施例中,对准销1019可以按照对称方案设置在支撑板1018上,使得舟形件1030B可以根据多于一个的取向定位在底部件1010B上。例如,对准销1019和对准孔1036的图案可以使得舟形件1030B可以绕X、Y或Z方向的每一个旋转180度,并且仍然正确地插入在底部件1010B上。在一些实施例中,通过采用较高对称性的配置,可以简化夹具1000B的自动组装。在一些可选实施例中,可以不在所有的支撑板1018上而是仅在它们的几个上形成对准销1019。例如,在图2C的夹具1000C中,底部件1010C包括:支撑板10181,其中形成有一个或多个对准销1019(例如,一个、两个、三个、四个等);以及支撑板10182,其中不形成对准销。在一些实施例中,对准销1019可以以不对称或较低对称的图案形成。在一些可选实施例中,可以在支撑板1018上不形成而是直接在基底1012上形成对准销1019。在又一些可选实施例中,可以在舟形件1030D上形成可以容纳在形成在底部件1010D的基底1012D中的对准孔1017(或对准套筒,未示出)中的对准销,如图2D的夹具1000D所示。如上面实例所示,本发明不限制对准销和对应的对准孔的位置和数量。
在一些实施例中,在封装模块PM1设置在夹具1000A上之后,在对应的底部件1010上放置夹具1000A的上部件1040,例如如图1I所示。参考图1I和图2A,夹具1000A的上部件1040的覆盖区基本与对应的基底1012的覆盖区匹配。在底部件1010上方放置上部件1040。在一些实施例中,在放置上部件1040之前,上部件1040与底部件1010垂直对准,使上部件1040的覆盖区与底部件1010的覆盖区匹配。在一些实施例中,上部件1040包括帽1042和外法兰1044。外法兰1044可以设置在帽1042的外围处。即,外法兰1044可以位于帽1042的边缘处,并且朝向基底1012突出。在一些实施例中,帽1042位于支撑板1018和设置在其上的封装模块PM1上面。在一些实施例中,如果外法兰1044沿垂直方向(例如,Z方向)从帽1042延伸至基底1012,则可以认为帽1042沿正交的X和Y方向延伸以覆盖基底1012的覆盖区。在一些实施例中,整体形成外法兰1044和帽1042。即,外法兰1044和帽1042可以形成为彼此接合而在两者之间没有清晰界面的单个部件。
在一些实施例中,外法兰1044到达设置磁体1020的基底1012。在一些实施例中,外法兰1044对应于基底1012的环形外围区域接触基底1012。在一些实施例中,磁体1050嵌入在外法兰1044中对应于磁体1020的位置中。在一些实施例中,可以极化磁体1020和磁体1050以便相互吸引。在一些实施例中,夹具1000A的上部件1040可以通过由磁体1020、1050产生的吸引力而固定至底部件1010。在一些实施例中,磁体1020可以相对于相邻的磁体1020具有不同的极化。例如,鉴于以行连续设置的三个磁体1020,中心磁体1020可以相对于另两个磁体1020具有相反的极化。在上部件1040中,也可以极化对应的三个磁体1050,使得中心磁体1050被吸引至中心磁体1020,而另外两个磁体1050被吸引至另外两个磁体1020。在一些实施例中,可以采用磁体1020、1050的极化图案,使得磁体1020、1050将夹具1000A的上部件1040和底部件1010保持在一起,并且也确保上部件1040和底部件1010之间的正确对准。但是,本发明不限于此。在一些可选实施例中,可以省略磁体1020、1050,并且可以通过其它紧固件(例如,诸如螺钉或夹钳的机械紧固件)将上部件1040和底部件1010保持在一起。例如,在图2E所示的夹具1000E中,底部件1010E的基底1012E包括形成在环形外围区域中的螺纹孔1020E。螺钉1050E从帽1042E上方延伸穿过上部件1040E的外法兰1044E,以容纳在螺纹孔1020E中。夹具1000E的其它方面可以类似于先前针对图2A的夹具1000A所描述的那样。
在一些实施例中,外法兰1044朝向基底1012延伸,并且环绕平台1014和设置在基底1012上的封装模块PM1。在一些实施例中,外法兰1044、帽1042和基底1012限定了容纳封装模块PM1的中空空间。即,封装模块PM1可以包含在夹具1000A内。在一些实施例中,形成穿过帽1042的开口1046,使得封装模块PM1的顶面至少部分由夹具1000A暴露。例如,半导体管芯410、420的背面410r、420r通过开口1046露出。在一些实施例中,可以在帽1042中形成开口1046,使得帽1042仍然沿开口1046的边缘接触封装模块PM1。在一些实施例中,开口1046的XY平面中的面积小于下面的封装模块PM1和支撑板1018的跨度。在一些实施例中,开口1046的区域的垂直投影可以完全落在下面的支撑板1018上。在一些实施例中,开口1046的区域的垂直投影可以完全落在下面的支撑板1018的由封装开口1034露出的部分上。在一些实施例中,通过弹簧1016的作用,封装模块PM1可以推靠在帽1042上,使得封装模块PM1密封开口1046的底部。例如,密封剂500可以在开口1046的边缘处接触并且推靠在帽1042上。但是,本发明不限于此。例如,在封装模块的背面与芯片的背面基本重合(例如,对应于半导体衬底的背面)的封装模块(未示出)中,芯片的背面的边缘可以接触开口1046周围的帽1042,并且芯片的背面的剩余部分可以由开口1046暴露。在一些实施例中,可以沿Z方向选择外法兰1044的高度,使得封装模块PM1密封开口1046。在一些实施例中,可以省略弹簧1016,并且封装模块PM1上的压缩力可以通过封装模块PM1和外法兰1044的相对高度来产生。例如,在图2F所示的夹具1000F中,直接在基底1012F上形成支撑板1018,而没有如图2A的夹具1000A中的弹簧或平台。可以通过选择外法兰1040F的高度来调节封装模块上的压缩力。在一些实施例中,上部件1040F和底部件1010F可以通过容纳在形成在基底1012F中的螺纹孔1020F中的螺钉1050F连接,以进一步调整由夹具1000F产生的压缩力。但是,本发明不限于此,并且在一些可选实施例中,可以采用其它紧固件(例如,如图2A的夹具1000A中的磁体、夹钳等)。在又一些可选实施例中,可以包括除弹簧之外的其它弹性元件,以将封装模块PM1推靠在上部件1040上。例如,诸如橡胶焊盘的弹性焊盘1016G可以设置在平台1014和支撑板1018之间,如图2G的夹具1000G的底部件1010G所示。可以选择弹性焊盘1016G的弹性性能,使得足够的推力作用在封装模块PM1上。在一些实施例中,开口1046与包围在夹具1000A中的封装模块PM1的数量一样多,每个封装模块PM1一个开口1046。
在一些实施例中,夹具1000A的底部件1010、舟形件1030和上部件1040可以由任何合适的材料独立地形成。例如,用于底部件1010、舟形件1030和上部件1040的材料可以独立地包括不锈钢、铁、铜、钛、其它金属、陶瓷材料或任何能够承受制造工艺的随后步骤的材料。在一些实施例中,夹具1000A可以经受阳极氧化或钝化处理(例如,利用镍),以增强其耐环境性并且减少随后制造步骤中的干扰。
在一些实施例中,在封装模块PM1的顶面的由开口1046暴露的部分上形成背侧金属化层1110,如图1J所示。在一些实施例中,背侧金属化层1110可以包括导热材料,例如钴(Co)、钨(W)、铜(Cu)、钛(Ti)、钽(Ta)、铝(Al)、锆(Zr)、铪(Hf)、镍(Ni)、银(Ag)、金(Au)、锌(Zn)、NiV、它们的组合或其它合适的金属材料。在一些实施例中,背侧金属化层1110通过诸如溅射或蒸发的合适的沉积工艺来形成。在一些实施例中,因为封装模块PM1压靠在帽1042上以密封开口1046(例如,通过弹簧1016的作用),所以可以在封装模块PM1的顶面上选择性形成背侧金属化层1110的材料,而不会渗入并且沉积在封装模块PM1的其它区域中(例如,在电路衬底700上)。即,包括开口1046的上部件1040可以在形成背侧金属化层1110期间用作沉积掩模,从而保护封装模块PM1的不需要背侧金属化层1110的区域。在一些实施例中,可以最初在夹具1000A的上部件1040上以及开口1046内沉积背侧金属化层1110的材料。参考图1J和图1K,在一些实施例中,可以从夹具1000A回收封装模块PM1。例如,夹具1000A可以通过去除上部件1040来打开,并且封装模块PM1可以从打开的夹具1000A拾取。在一些实施例中,可以在夹具1000A的底部件1010上简单放置封装模块PM1,而没有额外的粘合剂,由舟形件1030保持在适当的位置。在这样的实施例中,可以方便地从夹具1000A回收具有形成在其上的背侧金属化层1110的封装模块PM1,而不需要额外的工艺以处理粘合材料、去除保护胶等。在一些实施例中,可以在形成背侧金属化层1110之后从夹具1000A回收封装模块PM1。然后可以清洁夹具1000A以去除背侧金属化层1110的形成在上部件1040上的材料,以便重新用于制造其它封装模块PM1。
参考图1L,在一些实施例中,然后热界面材料(TIM)1120可以设置在背侧金属化层1110上,如图1K所示。在一些实施例中,TIM 1120是粘合材料。在一些实施例中,TIM 1120包括基于油脂的材料、相变材料、凝胶、粘合剂、聚合物、金属材料或它们的组合。在一些实施例中,TIM 1120包括基于铅锡的焊料(PbSn)、无铅焊料、银浆(Ag)、金、锡、镓、铟、碳复合材料、石墨、碳纳米管或其它合适的导热材料。在一些实施例中,TIM 1120是凝胶型材料。根据所使用的材料的类型,TIM 1120可以通过沉积、层压、印刷、镀或任何其它合适的技术来形成。例如,可以在封装模块PM1上分配凝胶型材料。在一些可选实施例中,TIM 1120可以是膜型材料。例如,TIM 1120可以是导电材料片(例如,碳纳米管、石墨烯或石墨)或具有导电材料的复合膜,诸如嵌入在基底材料中的填充物(例如,粉末、片状颗粒、纳米管、纤维等)。
在一些实施例中,粘合剂1200设置在电路衬底700的上侧700a上,靠近电路衬底100的外边缘700e。在一些实施例中,电路衬底700的外边缘700e是将上侧700a连接至相对的底侧700b的外围表面。在一些实施例中,粘合剂1200按照电路衬底700的外边缘700e的轮廓形成框架。例如,如果电路衬底700具有矩形覆盖区,则粘合剂1200可以具有矩形框架的形状。类似地,如果电路衬底700具有圆形覆盖区,则粘合剂1200可以具有圆形框架的形状。在一些实施例中,粘合剂1200的多个部分设置在电路衬底700上。即,由粘合剂1200形成的框架可以是不连续的,从而在粘合剂1200的连续部分之间存在暴露电路衬底700的间隙。封装的管芯10和无源器件900设置在由粘合剂1200形成的框架内。在一些实施例中,粘合剂1200包括热固性粘合剂、光固性粘合剂、导热粘合剂、热固性树脂、防水粘合剂、层压粘合剂或它们的组合。在一些实施例中,粘合剂1200包括导热粘合剂。在一些实施例中,粘合剂1200包括其上沉积有焊膏(未示出)的金属层(未示出)。根据所使用的材料的类型,粘合剂1200可以通过沉积、层压、印刷、镀或任何其它合适的技术来形成。
图1M是根据本发明的一些实施例的半导体封装件SP10的截面图。在一些实施例中,制造半导体封装件SP10包括在电路衬底700上设置金属覆盖物1300,例如在图1L所示的结构上。在一些实施例中,金属覆盖物1300可以由导电材料制成。例如,金属覆盖物1300可以包括金属材料,诸如铜。在一些实施例中,金属覆盖物1300可以在其安装在电路衬底700上之前经受阳极氧化或钝化处理(例如,利用镍),以增强其耐环境性。在一些实施例中,金属覆盖物1300的覆盖区与电路衬底700的覆盖区基本匹配。在一些实施例中,金属覆盖物1300包括盖1310和法兰1320。在电路衬底700上方放置金属覆盖物1300。在一些实施例中,在放置金属覆盖物1300之前,金属覆盖物1300与电路衬底700垂直对准,并且金属覆盖物1300的覆盖区与电路衬底700的覆盖区匹配。法兰1320可以设置在盖1310的外围处。即,法兰1320可以位于盖1310的边缘处,并且朝向电路衬底700突出。在一些实施例中,盖1310设置在电路衬底100和半导体封装件200上方。在一些实施例中,如果法兰1320沿垂直方向(例如,Z方向)从盖1310延伸至电路衬底700,则可以认为盖1310沿X和Y方向延伸以覆盖电路衬底700的覆盖区。在一些实施例中,整体形成法兰1320和盖1310。即,法兰1320和盖1310可以形成为彼此接合而在两者之间没有清晰界面的单个部件。在一些实施例中,法兰1320朝向电路衬底700延伸并且环绕封装的管芯10和无源器件900。在一些实施例中,法兰1320到达设置粘合剂1200的电路衬底700。粘合剂1200可以将法兰1320固定至电路衬底700。在一些实施例中,粘合剂1200仅在法兰1320预期接触电路衬底700的地方设置在电路衬底700上。在一些实施例中,背侧金属化层1110、TIM 1120和金属覆盖物1300可以促进在半导体封装件SP10的使用期间产生的热的耗散。
如以上公开所示,在一些实施例中,最初可以以重构晶圆的形式处理封装的管芯10,并且可以在封装的管芯10从重构晶圆分割并且连接至电路衬底700以形成封装模块PM1(例如,如图1G所示)之后,形成背侧金属化层1110。因为当封装的管芯10被分割或连接至电路衬底700时尚未形成背侧金属化层1110,所以可以选择背侧金属化层1110的材料,而较少考虑锯切或回流工艺期间的材料行为。因此,背侧金属化层1110的材料可以从更宽的候选范围选择,例如,更多考虑材料的散热特性。在一些实施例中,可以在用于半导体制造的夹具1000A(例如,图2A中示出)中放置封装模块PM1,该夹具可以在形成背侧金属化层1110期间用作沉积掩模。通过这样做,夹具1000A可以保护封装模块PM1的不需要或不希望在其上沉积背侧金属化层1110的表面。在一些实施例中,夹具1000A的底部件1010和上部件1040可以通过成对的磁体1020、1050(或其它机械紧固件)的作用而保持在一起,使得夹具1000A的组装和拆卸可以在没有额外的固化、处理或清洗步骤的情况下实现。因此,可以简化半导体封装SP10的制造工艺,从而增大工艺良率并且降低制造成本。
图4是根据本发明的一些实施例的用于制造半导体封装件的夹具1400的示意性立体图。夹具1400具有与图2A的夹具1000A类似的结构。图2A的夹具1000A和图4的夹具1400之间的区别在于,图4的夹具1400适合于制造更大的半导体封装件(例如,具有较大覆盖区的半导体封装件)。因此,虽然夹具1400和1000A的底部件1410、1010具有基本相同的覆盖区(在XY平面中占据相同的空间),但是在夹具1400的基底1412上形成了较少(例如,四个而不是8个)但较大的平台1414。类似地,舟形件1430具有形成在主体1432中较少的的封装开口1434,但是封装开口1434的尺寸(例如,沿X和Y方向的尺寸DX和DY)可以大于图2A的封装开口1034的对应尺寸。类似地,上部件1440包括形成在帽1442中的较少但较大的开口1446。夹具1400和图2A的夹具1000A之间的另一区别在于,在基底1412上而不是在支撑板1418上形成对准销1419。例如,对准销1419位于基底1412的环形外围区域的四个内角处。因此,在舟形件1430的主体1432中形成四个对准孔1436。两个夹具1000A、1400的其它方面可以与先前描述的相同。例如,弹簧1416的阵列设置在平台1414和支撑板1418之间,并且磁体1420嵌入在基底1412中,例如在环形外围区域中,以通过与嵌入在上部件1440的外法兰1444中的磁体1450相互作用,将上部件1440和底部件1410保持在一起。
图5是根据本发明的一些实施例的用于制造半导体封装件的夹具1500的示意性立体图。夹具1500具有与图2A的夹具1000A类似的结构。图2A的夹具1000A和图5的夹具1500之间的区别在于,图5的夹具1500适合于制造一个更大的半导体封装件(例如,大规模半导体封装件)。因此,虽然夹具1500和1000A的底部件1510、1010具有基本相同的覆盖区(在XY平面中占据相同的空间),但是夹具1500包括单个支撑板1515。在一些实施例中,支撑板1515可选地设置在弹簧或其它弹性元件(未示出)上,类似于上面关于图2A的支撑板1018所讨论的那样。在一些可选实施例中,支撑板1515直接设置在基底1512上,并且甚至可以与基底1512整体形成。在一些实施例中,夹具1500的底部件1510不包括平台(诸如图2A的平台1014)。相反,基底1512在环形外围区域中具有比对应于支撑板1515大的厚度,使得形成支撑板1515位于其中的凹槽1518。弹性元件(未示出)(当包括时)设置在凹槽1518的底部处以支持支撑板1515。在一些实施例中,夹具1500不包括舟形件(诸如图2A的舟形件1030)。在一些实施例中,因为支撑板1515位于凹槽1518内,所以当封装模块(未示出)设置在夹具1500内时,凹槽1518可以保持封装模块在适当的位置。但是,本发明不限于此,并且在一些可选实施例中,夹具1500中也可以包括舟形件(未示出),例如以使夹具1500适合于制造不同尺寸的半导体封装件和/或一起制造多个半导体封装件。在一些实施例中,舟形件可以容纳在凹槽1518中,使得不需要包括进一步的对准机构。但是,本发明不限于此,并且在一些可选实施例中,也可以包括对准机构(例如,销和对应的孔)。在一些实施例中,上部件1540具有与上部件1040类似的结构,但是用于在帽1542中包括更少(例如,单个)的开口1546。在一些实施例中,可以提供具有多个上部件1440的夹具1500,开口1446的尺寸或数量不同,使得不同尺寸的封装模块可以设置在夹具1500内,并且在形成背侧金属化层和/或TIM期间仍然密封开口1446。夹具1500的其它方面可以类似于先前针对图2A的夹具1000A所描述的那样。例如,磁体1520嵌入在基底1512中,例如在环形外围区域中,以通过与嵌入在上部件1540的外法兰1544中的磁体1550相互作用,将上部件1540和底部件1510保持在一起。
在本发明的一些实施例中,可以以各种方式组合图2A至图2G、图4和图5的夹具1000A-1000G、1400、1500的部件。例如,即使当如针对夹具1000A-1000G或1400所讨论的那样在相同的夹具内制造多个封装模块时,支撑板1018或1418可以设置在相应的基底1012、1412的凹槽内,如针对夹具1500所讨论的那样。类似地,即使当支撑板如图5的夹具1500那样容纳在基底的凹槽中,诸如1019或1419的对准销也可以被包括在支撑板上。作为进一步实例,可选的紧固装置可以用于夹具1400和1500,如上面针对图2E和图2F的夹具1000E、1000F所描述。而且,在夹具1000A-1000E、1400或1500中的任何一个中,弹簧可以由其它弹性元件代替,诸如图2G的弹性焊盘1016G。
图6A至图6C是根据本发明的一些实施例的在半导体封装件SP20的制造工艺期间产生的结构的示意性截面图。图7是在制造半导体封装件SP20中使用的夹具1600A的示意性立体图。在图6A中示出了根据本发明的一些实施例的具有形成在其上的TIM 1120的封装模块PM2。封装模块PM2可以具有与先前关于图1G的封装模块PM1所讨论类似的结构,并且可以按照与先前参考图1A至图1G描述的类似工艺来制造。在一些实施例中,图6A的结构可以通过在半导体管芯410、420的背面410r、420r上形成TIM 1120,并且通过在电路衬底700的上侧700a上设置粘合剂1200从图1G的结构获得。
在一些实施例中,参考图6A和图6B,金属覆盖物1300可以通过使用夹具1600A接合至电路衬底700。例如,金属覆盖物1300可以设置在电路衬底700上,其中法兰1320接触粘合剂1200。一旦金属覆盖物1300与粘合剂接触,则可以预固化粘合剂1200,例如在50-200℃之间的温度下,例如持续10s至900s范围内的时间。在一些实施例中,在预固化步骤期间,可以确定沿TIM 1120的Z方向的厚度。类似地,预固化步骤可以确定所得半导体封装件的翘曲。
图7是夹具1600A的示意性立体图。参考图6B和图7,在一些实施例中,其上具有金属覆盖物1300(可选地预接合)的封装模块PM2可以设置在夹具1600A的底部件1610上。在一些实施例中,夹具1600A的底部件1610包括基底1611和(可选地)平台1613。封装模块PM2设置在基底1611的中心区域中,当形成平台1613时设置在平台1613上。平台1613可以由基底1611的环形外围区域环绕。在一些实施例中,封装模块PM2设置为使得电路衬底700接触底部件1610。然后可以在夹具1600A的底部件1610上放置并且固定夹具1600A的上部件1620,以这种方式使得封装模块PM2和金属覆盖物1300通过夹具1600A的作用被压缩。在一些实施例中,上部件1620包括位于封装模块PM2和金属覆盖物1300上面的帽1621以及设置在帽1621的外围处的外法兰1622。在一些实施例中,外法兰1622位于基底1611的环形外围区域上面。在一些实施例中,外法兰1622的沿Z方向的厚度可以大于帽1621的沿Z方向的厚度。即,上部件1620可以存在对应于帽1621的凹槽。
弹簧1623的阵列可以设置在上部件1620的凹槽中。在一些实施例中,弹簧1623的一个端子附接至帽1621,并且弹簧1623的另一端子被附接至刚性板1624。在一些实施例中,每个刚性板1624有约0至200个弹簧1623。在一些实施例中,刚性板1624具有依次堆叠在相对于弹簧1623的相对侧上的弹性焊盘1625和释放层1626。在一些实施例中,弹性焊盘1625可以包括热塑性树脂,诸如聚醚酰亚胺(PEI)或聚醚醚酮(PEEK)、(甲基)丙烯酸树脂、环氧树脂、它们的组合等。在一些实施例中,如图8的夹具1600B所示,弹性焊盘1625B可以进一步包括分散在一种或多种上述树脂16252中的基于碳的填充物16251。在一些实施例中,基于碳的填充物16251可以是金刚石、石墨、无定形碳或它们的组合中的任何一种。在一些可选实施例中,弹性焊盘1625可以由例如包括石墨、无定形碳或碳纳米管的基于碳的材料形成。例如,图9A中示意性地示出了根据本发明的一些实施例的夹具1600C的刚性板1624和弹性焊盘1625C。在夹具1600C中,弹性焊盘1625C包括分散在树脂16252中的碳纳米管16253,例如,树脂16252可以选自上面列出的材料。在一些可选实施例中,弹性焊盘1625D可以由附接至刚性板1624而不分散在树脂中的碳纳米管16253形成,如图9B中的夹具1600D所示。碳纳米管16253可以在一端处附接至刚性板1624,并且在另一端处附接至释放层1626。即,碳纳米管16253可以垂直于刚性板1624和释放层1626的主延伸平面取向。在一些可选实施例中,如图9C的夹具1600E所示,弹性焊盘1625可以全部由碳纳米管16253形成。碳纳米管16253可以设置为彼此平行地位于刚性板1624的主延伸平面上,夹在刚性板1624和释放层1626之间。即,碳纳米管16253可以设置为使得壁沿长度尺寸在一侧处接触刚性板1624并且在相对侧处接触释放层1626。在一些实施例中,刚性板1624和弹性焊盘1625通过弹簧1623的作用在金属覆盖物1300上施加压力。在一些可选实施例中,除弹簧以外的弹性元件可以设置在刚性板1624和帽1621之间。例如,在图10A所示的夹具1600F中,上部件1620F包括设置在帽1621和刚性板1624之间的可压缩焊盘1623F。在又一些可选实施例中,如图10B的夹具1600G所示,刚性板1624可以直接连接至帽1621,并且可以通过设定上部件1620G和底部件1610的距离来调节封装模块PM2上的压力。在一些实施例中,包括释放层1626以防止或减小金属覆盖物1300粘合至弹性焊盘1625的可能性。在一些实施例中,释放层1626可以包括聚合材料,诸如聚酰亚胺、(甲基)丙烯酸酯或环氧树脂。在一些实施例中,夹紧力可以通过选择适当的弹簧(或弹性)常数的弹簧1623(或焊盘1623F)来控制。在一些实施例中,刚性板1624、橡胶焊盘1625和释放层1626在XY平面中具有与金属覆盖物1300类似的覆盖区,使得上部件1620可以施加基本均匀的压力。在一些实施例中,上部件1620例如通过带螺纹的螺钉1630拧紧至底部件1610。在一些实施例中,在外法兰1622中形成通孔1628,螺钉1630穿过通孔1628插入。螺钉1630的螺纹端容纳在形成在底部件1610的环形外围区域中的螺纹盲孔1615中。螺钉1630的帽位于外法兰1622上,可选地具有中间垫圈1640。在一些实施例中,垫圈1640可以防止档拧紧时螺钉1630咬住外法兰1622。通过调整拧紧螺钉1630的量,可以设定上部件1620在底部件1610上施加的压力。
在一些实施例中,对准和高度调节机构设置在基底1611和外法兰1622的环形外围区域上。例如,可以在螺纹盲孔1615周围形成高度设定套筒1617,以容纳螺钉1630。高度设定套筒1617可以是空心沟道,螺钉1630在容纳在螺纹盲孔1615中之前穿过该空心沟道。高度设定套筒1617可以由刚性材料制成,当拧紧螺钉1630以便设定夹具1600A的上部件1620和夹具1600A的底部件1610之间的距离时能够承受由上部件1620施加的压力。在一些实施例中,在底部件1610上形成对准销1619,例如在环形外围区域的角处。在一些实施例中,对准销1619可以容纳在形成在外法兰1622上的对准套筒1627中。在一些可选实施例中,对准销1619可以容纳在形成在外法兰1622中的对准孔(未示出)中。在一些实施例中,对准孔是盲孔。在一些可选实施例中,对准孔是通孔。
在一些实施例中,夹具1600A的底部件1610和上部件1620可以由任何合适的材料独立地形成。例如,用于底部件1610和上部件1620的材料可以独立地包括不锈钢、铁、铜、钛、其它金属、陶瓷材料或能够承受制造工艺的随后步骤的任何材料。在一些实施例中,夹具1600A可以经受阳极氧化或钝化处理(例如,利用镍),以增强其耐环境性并且减少随后制造步骤中的干扰。
在一些实施例中,封装模块PM2和金属覆盖物1300可以在固化粘合剂1200和TIM1120期间保持在夹具1600A中。在一些实施例中,在固化步骤期间,通过根据上述机制的夹具1600A的作用,在金属覆盖物1300和封装模块PM2上施加压力。在一些实施例中,固化可以在125至150℃范围内的温度下利用约0.1至150kgf的夹紧力实施。在一些实施例中,弹簧1623可以增加施加在金属覆盖物1300上的力的均匀性。在一些实施例中,高度设定套筒1617可以增加所施加的力的均匀性。在固化之后,可以例如通过松开螺钉1630并且去除上部件1620来打开夹具1600A,并且可以回收半导体封装件SP 20(例如,在图6C中示出)。在一些实施例中,通过在固化步骤期间将半导体封装件SP20保持在夹具1600A中,TIM 1120和金属覆盖物1300之间的接触面积可以增大。在一些实施例中,接触面积可以通过例如利用超声波扫描半导体封装件SP20来测量。在一些实施例中,增大的接触面积可以增强半导体封装件SP20的热性能。例如,相对于不使用夹具1600A的情况,在通过超声扫描测量的接合金属覆盖物1300之后的TIM 1120的面积覆盖率可以增大约40%。在一些实施例中,在使用夹具1600A接合金属覆盖物1300时观察到的TIM 1120的面积覆盖率可以接近100%,例如约99%。在一些实施例中,半导体封装件SP20的稳定性也可以增大。例如,当在固化步骤期间使用夹具1600A时,在对半导体封装件SP20进行应力测试后,可以观察到TIM 1120和金属覆盖物1300的较少分层。例如,对于使用诸如夹具1600A的夹具制造的半导体封装件,可以观察到TIM 1120的面积覆盖率减小约3%。相比之下,对于不使用诸如夹具1600A的夹具制造的封装件,在实施类似的压力测试时,可以观察到面积覆盖率降低至原始值的约30%。在一些实施例中,夹具1600A的使用与自动化工艺兼容。即,夹具1600A的组装和拆卸可以以自动化的方式实施,例如,无需人工干预。
应该指出,虽然在图7中夹具1600A示出为设计用于单个封装模块,但是本发明不限于此。例如,弹簧1623或可压缩焊盘1623F的多个阵列可以附接至帽1621,并且每个阵列可以连接至专用的刚性板1624、弹性焊盘1625和释放层1626。可以在基底1611上形成对应的平台1613。在一些实施例中,可以适当地组合上面描述的若干实施例的部件。例如,图7至图9B的弹性焊盘1625和1625B-1625E中的任一个可以用作图2G的弹性焊盘1016G。作为另一实例,类似于图2A至图2G和图4的夹具1000A-1000G、1400的舟形件1030、1030B、1030C、1030D、1430的舟形件(未示出)可以可选地包括在图7至图10B的夹具1600A-1600G的底部件1610上,以将封装模块保持在适当的位置。此外,虽然本发明关于与制造图7至图10B的夹具1600A-1600G不同的半导体封装件(例如,图1M的半导体封装件SP10和图6C的SP20)提出了图2A至图2G的夹具1000A-1000G以及图4和图5的夹具1400、1500,但是本发明不限于此。在一些实施例中,诸如夹具1000A-1000G、1400或1500中的一个的第一夹具可以用于在封装模块的顶面上形成背侧金属化层1100,并且在随后附接金属覆盖物的工艺期间,可以使用诸如夹具1600A-1600G中的一个的第二夹具。
图11A至图11F是根据本发明的一些实施例的在半导体封装件SP30的制造方法期间形成的结构的示意性截面图。制造半导体封装件SP30可以类似于先前针对半导体封装件SP10和SP20所讨论的那样,并且以下未明确解决的方面可以认为是类似的。在图11A中,提供了封装模块PM3。在一些实施例中,封装模块PM3可以在将封装的管芯12接合至电路衬底700时形成。在一些实施例中,封装的管芯12是晶圆上芯片封装件,包括例如通过微凸块1740接合至中介层1730的半导体管芯1710、1720。半导体管芯1710、1720可以具有与先前描述的半导体管芯410、420(例如,在图1D中示出)类似的结构并且实施与先前描述的半导体管芯410、420类似的功能。在一些实施例中,半导体管芯1710、1720设置在中介层1730上,其中相应的接触焊盘1713、1723以及(如果包括)接触杆1717、1727指向中介层1730。中介层1730可以包括:互连层1731,包括介电层1732;以及导电图案1733,延伸穿过介电层1732。微凸块1740可以将导电图案1733连接至导电焊盘1713、1723或导电杆1717、1727。可以在半导体通孔(TSV)1737延伸穿过的半导体衬底1735上形成互连层1731。接触焊盘1739可以相对于半导体管芯1710、1720设置在半导体衬底1735的相对侧上。TSV 1737可以在导电图案1733和接触焊盘1739之间建立电连接。底部填充物1750的一个或多个部分可以设置在半导体管芯1710、1720和中介层1730之间以围绕微凸块1740。可以在中介层1730上形成密封剂1760,以横向包裹半导体管芯1710、1720和底部填充物1750。在一些实施例中,半导体管芯1710、1720的背面1710r、1720r和密封剂1760的顶面1760t沿Z方向基本处于相同的水平高度。在一些实施例中,其上接合有半导体管芯1710、1720的中介层1730设置在电路衬底700上,并且例如通过连接端子1800连接至电路衬底700。底部填充物800可以设置在封装的管芯12和电路衬底700之间以围绕连接端子1800。在一些实施例中,无源器件900相对于封装的管芯12设置在电路衬底700的同一侧700a上。
在图11B中,一个或多个封装模块PM3设置在夹具1000A内类似于先前参考图1H和图1I所讨论的那样。简而言之,封装模块PM3设置在夹具1000A的底部件1010上,例如,每个支撑板1018一个封装模块PM3。封装模块PM3设置在底部件1010上,其中电路衬底700指向底部件1010。舟形件1030可以帮助将封装模块PM3保持在底部件1010上的适当的位置。类似于先前描述的那样,夹具1000A的上部件1040可去除地固定至底部件1010,例如通过分别嵌入在底部件1010的基底1012和上部件1040的外法兰1044中的成对的磁体1020、1050。同样对于封装模块PM3,半导体管芯1710、1720的背面1710r、1720r由形成在上部件1040的帽1042中的开口1046暴露。在一些实施例中,封装模块PM3压靠在上部件1040上,使得帽1042可以接触封装模块PM3的密封剂1760以密封开口1046的底部。
在图11C中,在开口1046中、在半导体管芯1710、1720的背面1710r、1720r上以及可能在密封剂1760上形成背侧金属化层1110。如先前所描述,因为封装模块PM3压靠在帽1042上以密封开口1046(例如,通过弹簧1016的作用),所以可以在封装模块PM3的顶面上选择性形成背侧金属化层1110的材料,而不会渗入并且沉积在封装模块PM3的其它区域中(例如,在电路衬底700上)。参考图11C和图11D,在一些实施例中,从夹具1000A回收封装模块PM3,并且然后TIM 1120设置在背侧金属化层1110上。在一些实施例中,粘合剂1200设置在电路衬底700的上侧700a上,靠近电路衬底700的外边缘700e。
在图11E中,金属覆盖物1300设置在电路衬底700上,接触粘合剂1200和TIM 1120。具有金属覆盖物1300(可能是预接合的)的封装模块PM3设置在诸如夹具1600A的夹具的底部件1610上。夹具1600A的上部件1620设置在底部件1610上以夹紧封装模块PM13以在固化粘合剂1200的同时施加压力,类似于先前参考图6B和图6C所描述的那样。参考图11F,在固化粘合剂1200之后,可以从夹具1600A回收半导体封装件SP30。
应该指出,虽然在图11A至图11F的工艺中示出了夹具1000A和1600A,但是本发明不限于此,并且根据生产要求可以使用根据本发明的任何其它夹具。
根据本发明的一些实施例,提供了用于制造半导体封装件的夹具。夹具包括适合于容纳在其间制造的封装件的上部件和底部件。当封装件设置在夹具的部件之间时,压缩力施加在封装件上。考虑到封装件的尺寸(例如,高度),压缩力可以通过设定夹具的上部件和底部件之间的距离来产生。在一些实施例中,可以包括弹性元件以将封装件压靠在夹具的上部件上。在一些实施例中,封装件上的压缩作用可以用于确保形成在上部件中的开口被密封,从而仅在它们的底部处暴露封装件的期望表面。通过这样做,在封装件的暴露表面上沉积材料期间,夹具可以用作掩模,同时保护其他表面。在一些实施例中,可以在固化期间对封装件施加压缩作用,以确保金属覆盖物和设置在封装件背面上的热界面材料之间的令人满意的粘合。
根据本发明的一些实施例,用于制造半导体封装件的夹具包括底部件和上部件。底部件包括基底、支撑板和至少一个弹性连接件。支撑板位于基底的中心区域中。至少一个弹性连接件介于支撑板和基底之间。上部件包括帽和外法兰。当上部件设置在底部件上时,帽位于支撑板上面。外法兰设置在帽的边缘处,与帽连接。当上部件设置在底部件上时,外法兰接触底部件的基底。帽包括开口,该开口是通孔。当上部件设置在底部件上时,开口的垂直投影完全落在支撑板上。
根据本发明的一些实施例,用于制造半导体封装件的夹具包括底部件和上部件以及螺钉。底部件包括基底。基底具有中心区域和环绕中心区域的外围区域。在基底的外围区域中形成螺纹孔。上部件包括帽、至少一个弹簧和外法兰。当上部件设置在底部件上方时,帽在基底的中心区域上方延伸。至少一个弹簧具有连接至帽的端子和连接至刚性板的另一端子。外法兰设置在帽的边缘处。在外法兰中形成通孔。当在底部件上方安装上部件时,螺钉会通过通孔横跨外法兰延伸,以拧紧在底部件的螺纹孔中。
根据本发明的一些实施例,半导体封装件的制造方法包括以下步骤。半导体管芯接合至电路衬底。将具有接合的半导体管芯的电路衬底放置在夹具的底部件的支撑板上。将夹具的上部件放置在底部件上以关闭夹具,从而将半导体管芯压靠在夹具的上部件上。夹具的上部件包括开口,并且半导体管芯的背面由开口暴露。在开口内的半导体管芯的背面上沉积导热材料。去除上部件以打开夹具。
根据本发明的一些实施例,半导体封装件的制造方法包括以下步骤。粘合材料设置在接合至电路衬底的至少一个半导体管芯旁边的电路衬底上。将金属覆盖物放置在粘合材料上。金属覆盖物在半导体管芯上方延伸。电路衬底设置在夹具的底部件上。夹具的上部件设置在夹具的底部件上方。夹具的上部件拧紧至夹具的底部件。通过这样做,金属覆盖物压靠在电路衬底和半导体管芯上。在夹具将金属覆盖物压靠在电路衬底和半导体管芯上的同时固化粘合材料。
本申请的一些实施例提供了一种用于制造半导体封装件的夹具,包括:底部件包括:基底;支撑板,位于所述基底中心区域中;以及至少一个弹性连接件,介于所述支撑板和所述基底之间;以及上部件,包括:帽,当所述上部件设置在所述底部件上时,位于所述支撑板上面;以及外法兰,设置在所述帽的边缘处,与所述帽连接,并且当所述上部件设置在所述底部件上时接触所述底部件的所述基底,其中,所述帽包括开口,所述开口是通孔,并且,当所述上部件设置在所述底部件上时,所述开口的竖直投影完全落在所述支撑板上。在一些实施例中,其中,所述底部件还包括对准销,并且用于半导体制造的所述夹具还包括具有封装开口和穿过其形成的对准孔的舟形件,其中,当所述舟形件设置在所述底部件上时,所述对准销容纳在所述对准孔中,并且所述封装开口至少露出所述支撑板的部分。在一些实施例中,所述开口的所述竖直投影完全落在所述支撑板的由所述封装开口露出的所述部分上。在一些实施例中,所述至少一个弹性连接件是弹性连接件的阵列中的一个,并且所述弹性连接件是弹簧。在一些实施例中,所述底部件具有形成在所述基底的中心区域中的平台,并且所述至少一个弹性连接件在一侧处接触所述平台并且在相对侧处接触所述支撑板。在一些实施例中,所述支撑板是位于所述基底的中心区域中的多个支撑板中的一个,并且所述帽的所述开口是形成在所述帽中的多个开口中的一个,并且,当所述上部件设置在所述底部件上时,所述帽的所述开口的竖直投影完全落在对应的下面的支撑板上。在一些实施例中,夹具还包括:第一磁体,固定在所述基底中并且具有在所述基底的顶面处暴露的一个表面;以及第二磁体,固定在所述外法兰中并且具有在所述外法兰的底面处暴露的一个表面,其中,当所述上部件设置在所述底部件上时,所述第二磁体与所述第一磁体重叠。在一些实施例中,所述支撑板和所述至少一个弹性连接件设置在所述基底的凹槽中。
本申请的另一些实施例提供了一种半导体封装件的制造方法,包括:将半导体管芯接合至电路衬底;将具有所述接合的半导体管芯的所述电路衬底放置在夹具的底部件的支撑板上;将所述夹具的上部件放置在所述底部件上以关闭所述夹具,从而将所述半导体管芯压靠在所述夹具的上部件上,其中,所述夹具的所述上部件包括开口,并且所述半导体管芯的背面由所述开口暴露;在所述开口内的所述半导体管芯的所述背面上沉积导热材料;以及去除所述上部件以打开所述夹具。在一些实施例中,所述导热材料包括金属材料。在一些实施例中,在所述夹具的所述上部件上进一步沉积所述导热材料。在一些实施例中,制造方法,还包括:将金属舟形件放置在所述夹具的所述底部件上,其中,所述金属舟形件包括暴露所述底部件的所述支撑板的开口,并且其中,具有所述接合的半导体管芯的所述电路衬底设置在所述舟形件的所述开口内的所述支撑板上。在一些实施例中,制造方法还包括:在所述导热材料上设置热界面材料;以及将金属覆盖物接合至所述电路衬底,其中,所述金属覆盖物接触所述热界面材料。在一些实施例中,将所述金属覆盖物接合至所述电路衬底包括:在所述电路衬底上设置粘合剂;将所述金属覆盖物放置在所述粘合剂上;在第二夹具中设置具有所述接合的半导体管芯、所述金属覆盖物和所述粘合剂的所述电路衬底;拧紧所述第二夹具以在所述金属覆盖物和所述电路衬底的堆叠方向上对所述金属覆盖物施加压力;以及实施加热步骤以固化所述粘合剂。
本申请的又一些实施例提供了一种制造半导体封装件的方法,包括:在接合至所述电路衬底的至少一个半导体管芯旁边的所述电路衬底上设置粘合材料;将金属覆盖物放置在所述粘合材料上,由此所述金属覆盖物在所述半导体管芯上方延伸;将所述电路衬底设置在夹具的底部件上;将所述夹具的上部件设置在所述夹具的所述底部件上方;将所述夹具的所述上部件拧紧至所述夹具的所述底部件,从而将所述金属覆盖物压靠在所述电路衬底和所述半导体管芯上;以及在所述夹具将所述金属覆盖物压靠在所述电路衬底和所述半导体管芯上的同时固化所述粘合材料。在一些实施例中,制造方法还包括:在将所述电路衬底设置在所述夹具中之前,预固化所述粘合材料。在一些实施例中,所述夹具的所述上部件包括依次堆叠在帽上方的刚性焊盘、弹性焊盘和释放层,其中,当所述夹具的所述上部件设置在所述夹具的所述底部件上时,所述释放层接触所述金属覆盖物。在一些实施例中,所述夹具的所述上部件还包括设置在所述帽和所述刚性焊盘之间的弹性连接件。在一些实施例中,所述弹性焊盘包括在相对侧处接触所述刚性焊盘和所述释放层的碳纳米管。在一些实施例中,制造方法还包括:在将所述金属覆盖物放置在所述电路衬底上之前,在所述管芯的背面上形成导热材料,其中,所述金属覆盖物接触所述导热材料。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解,它们可以容易地使用本发明作为基底来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中它们可以做出多种变化、替换以及改变。
Claims (10)
1.一种用于制造半导体封装件的夹具,包括:
底部件包括:
基底;
支撑板,位于所述基底中心区域中;以及
至少一个弹性连接件,介于所述支撑板和所述基底之间;以及上部件,包括:
帽,当所述上部件设置在所述底部件上时,位于所述支撑板上面;以及
外法兰,设置在所述帽的边缘处,与所述帽连接,并且当所述上部件设置在所述底部件上时接触所述底部件的所述基底,
其中,所述帽包括开口,所述开口是通孔,并且,当所述上部件设置在所述底部件上时,所述开口的竖直投影完全落在所述支撑板上。
2.根据权利要求1所述的夹具,
其中,所述底部件还包括对准销,并且
用于半导体制造的所述夹具还包括具有封装开口和穿过其形成的对准孔的舟形件,
其中,当所述舟形件设置在所述底部件上时,所述对准销容纳在所述对准孔中,并且所述封装开口至少露出所述支撑板的部分。
3.根据权利要求2所述的夹具,其中,所述开口的所述竖直投影完全落在所述支撑板的由所述封装开口露出的所述部分上。
4.根据权利要求1所述的夹具,其中,所述至少一个弹性连接件是弹性连接件的阵列中的一个,并且所述弹性连接件是弹簧。
5.根据权利要求1所述的夹具,其中,所述底部件具有形成在所述基底的中心区域中的平台,并且所述至少一个弹性连接件在一侧处接触所述平台并且在相对侧处接触所述支撑板。
6.根据权利要求1所述的夹具,其中,所述支撑板是位于所述基底的中心区域中的多个支撑板中的一个,并且所述帽的所述开口是形成在所述帽中的多个开口中的一个,并且,当所述上部件设置在所述底部件上时,所述帽的所述开口的竖直投影完全落在对应的下面的支撑板上。
7.根据权利要求1所述的夹具,还包括:
第一磁体,固定在所述基底中并且具有在所述基底的顶面处暴露的一个表面;以及
第二磁体,固定在所述外法兰中并且具有在所述外法兰的底面处暴露的一个表面,
其中,当所述上部件设置在所述底部件上时,所述第二磁体与所述第一磁体重叠。
8.根据权利要求1所述的夹具,其中,所述支撑板和所述至少一个弹性连接件设置在所述基底的凹槽中。
9.一种半导体封装件的制造方法,包括:
将半导体管芯接合至电路衬底;
将具有所述接合的半导体管芯的所述电路衬底放置在夹具的底部件的支撑板上;
将所述夹具的上部件放置在所述底部件上以关闭所述夹具,从而将所述半导体管芯压靠在所述夹具的上部件上,其中,所述夹具的所述上部件包括开口,并且所述半导体管芯的背面由所述开口暴露;
在所述开口内的所述半导体管芯的所述背面上沉积导热材料;以及
去除所述上部件以打开所述夹具。
10.一种半导体封装件的制造方法,包括:
在接合至所述电路衬底的至少一个半导体管芯旁边的所述电路衬底上设置粘合材料;
将金属覆盖物放置在所述粘合材料上,由此所述金属覆盖物在所述半导体管芯上方延伸;
将所述电路衬底设置在夹具的底部件上;
将所述夹具的上部件设置在所述夹具的所述底部件上方;
将所述夹具的所述上部件拧紧至所述夹具的所述底部件,从而将所述金属覆盖物压靠在所述电路衬底和所述半导体管芯上;以及
在所述夹具将所述金属覆盖物压靠在所述电路衬底和所述半导体管芯上的同时固化所述粘合材料。
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Family Cites Families (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61276237A (ja) * | 1985-05-31 | 1986-12-06 | Hitachi Ltd | 半導体パツケ−ジの気密封止方法およびその装置 |
US4988424A (en) | 1989-06-07 | 1991-01-29 | Ppg Industries, Inc. | Mask and method for making gradient sputtered coatings |
JP2933403B2 (ja) * | 1991-03-15 | 1999-08-16 | 株式会社日立製作所 | 半導体パッケージ気密封止方法及び半導体パッケージ気密封止装置 |
JP3446835B2 (ja) | 1991-03-27 | 2003-09-16 | Hoya株式会社 | ガラス光学素子用プレス成形型 |
KR20010023027A (ko) * | 1997-08-19 | 2001-03-26 | 가나이 쓰토무 | 범프 전극 형성 방법 및 반도체 장치 제조 방법 |
JP2000114900A (ja) | 1998-09-29 | 2000-04-21 | Seiko Epson Corp | 圧電振動素子の封止用治具及び封止方法 |
US7022211B2 (en) * | 2000-01-31 | 2006-04-04 | Ebara Corporation | Semiconductor wafer holder and electroplating system for plating a semiconductor wafer |
US6665187B1 (en) | 2002-07-16 | 2003-12-16 | International Business Machines Corporation | Thermally enhanced lid for multichip modules |
JP2005005614A (ja) | 2003-06-13 | 2005-01-06 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
US6870258B1 (en) * | 2003-06-16 | 2005-03-22 | Advanced Micro Devices | Fixture suitable for use in coupling a lid to a substrate and method |
US20060273450A1 (en) * | 2005-06-02 | 2006-12-07 | Intel Corporation | Solid-diffusion, die-to-heat spreader bonding methods, articles achieved thereby, and apparatus used therefor |
US8497162B1 (en) * | 2006-04-21 | 2013-07-30 | Advanced Micro Devices, Inc. | Lid attach process |
US7256067B1 (en) * | 2006-05-01 | 2007-08-14 | Advanced Micro Devices, Inc. | LGA fixture for indium assembly process |
US9048233B2 (en) | 2010-05-26 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems having interposers |
US9064879B2 (en) | 2010-10-14 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods and structures using a die attach film |
US8797057B2 (en) | 2011-02-11 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Testing of semiconductor chips with microbumps |
US8373269B1 (en) * | 2011-09-08 | 2013-02-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Jigs with controlled spacing for bonding dies onto package substrates |
JP5838065B2 (ja) * | 2011-09-29 | 2015-12-24 | 新光電気工業株式会社 | 熱伝導部材及び熱伝導部材を用いた接合構造 |
US9000584B2 (en) | 2011-12-28 | 2015-04-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged semiconductor device with a molding compound and a method of forming the same |
US9111949B2 (en) | 2012-04-09 | 2015-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus of wafer level package for heterogeneous integration technology |
US9343310B1 (en) | 2012-06-27 | 2016-05-17 | Nathaniel R Quick | Methods of forming conductors and semiconductors on a substrate |
US9443783B2 (en) | 2012-06-27 | 2016-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC stacking device and method of manufacture |
US9299649B2 (en) | 2013-02-08 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D packages and methods for forming the same |
US9263511B2 (en) | 2013-02-11 | 2016-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package with metal-insulator-metal capacitor and method of manufacturing the same |
US9048222B2 (en) | 2013-03-06 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating interconnect structure for package-on-package devices |
US8993380B2 (en) | 2013-03-08 | 2015-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for 3D IC package |
US9368460B2 (en) | 2013-03-15 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out interconnect structure and method for forming same |
US9281254B2 (en) | 2014-02-13 | 2016-03-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming integrated circuit package |
US9425126B2 (en) | 2014-05-29 | 2016-08-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy structure for chip-on-wafer-on-substrate |
US9496189B2 (en) | 2014-06-13 | 2016-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked semiconductor devices and methods of forming same |
US9666502B2 (en) | 2015-04-17 | 2017-05-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Discrete polymer in fan-out packages |
US9461018B1 (en) | 2015-04-17 | 2016-10-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out PoP structure with inconsecutive polymer layer |
US9735131B2 (en) | 2015-11-10 | 2017-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-stack package-on-package structures |
US9947560B1 (en) * | 2016-11-22 | 2018-04-17 | Xilinx, Inc. | Integrated circuit package, and methods and tools for fabricating the same |
US10541156B1 (en) * | 2018-10-31 | 2020-01-21 | International Business Machines Corporation | Multi integrated circuit chip carrier package |
US11062971B2 (en) * | 2019-01-08 | 2021-07-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method and equipment for forming the same |
US11652020B2 (en) * | 2019-05-29 | 2023-05-16 | Intel Corporation | Thermal solutions for multi-package assemblies and methods for fabricating the same |
US11842943B2 (en) * | 2019-08-06 | 2023-12-12 | Intel Corporation | Electronic systems with inverted circuit board with heat sink to chassis attachment |
US11804468B2 (en) * | 2021-01-15 | 2023-10-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Manufacturing method of semiconductor package using jig |
US11996345B2 (en) * | 2021-08-27 | 2024-05-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and manufacturing method thereof |
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