CN114743880B - 一种功率半导体沟槽尺寸控制方法和功率半导体结构 - Google Patents

一种功率半导体沟槽尺寸控制方法和功率半导体结构 Download PDF

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CN114743880B
CN114743880B CN202210377567.5A CN202210377567A CN114743880B CN 114743880 B CN114743880 B CN 114743880B CN 202210377567 A CN202210377567 A CN 202210377567A CN 114743880 B CN114743880 B CN 114743880B
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赵志
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Abstract

本发明涉及功率半导体领域，具体涉及一种功率半导体沟槽尺寸控制方法和功率半导体结构，所述方法包括如下步骤：提供基底，从所述基底上表面向下注入磷/砷；在所述基底上表面淀积硬掩膜，通过光刻在硬掩膜形成沟槽图形，然后对基底进行刻蚀，形成沟槽；湿法腐蚀去掉牺牲层和所述硬掩膜，在沟槽内壁中热生长一层氧化层；再在所述沟槽内回填氧化物，通过光刻和刻蚀形成矩形槽；通过化学机械抛光在所述矩形槽内抛磨出内壁为曲面的弧形沟槽；在所述弧形沟槽内淀积掺杂的导电多晶硅，向导电多晶硅中注入磷和硼并退火。本发明能够节省成本，极大的缩短流片周期；还能以更少的工程批调节沟槽尺寸及注入规格调整耐压。

Description

一种功率半导体沟槽尺寸控制方法和功率半导体结构
技术领域
本发明涉及功率半导体领域，具体涉及一种功率半导体沟槽尺寸控制方法和功率半导体结构。
背景技术
目前功率半导体的主流技术为DMOS，漏极金属在晶圆背面，做完正面金属要对晶圆背面进行减薄背金；而且DMOS流片周期较长，主要受制于外延片的采购周期过长，供货量紧缺，采购外延片的成本过高。另外，半导体器件击穿电压（BV）的调整工艺较为复杂，需要多个不同的工程批调节沟槽尺寸及注入规格方可实现。
发明内容
本发明提供一种功率半导体沟槽尺寸控制方法和功率半导体结构，不需要采购外延片，所有工艺步骤在硅衬底上进行，可以节省成本，极大的缩短流片周期，提高生产效率；另外还能通过版图及工艺即可调整，可以通过更少的工程批调节沟槽尺寸及注入规格，得到需要的耐压。为解决上述技术问题，本发明提供如下技术方案：
一种功率半导体沟槽尺寸控制方法，包括如下步骤：
提供基底，从所述基底上表面向下注入磷/砷；
在所述基底上表面淀积硬掩膜，通过光刻在硬掩膜形成沟槽图形，然后对基底进行刻蚀，形成沟槽；
湿法腐蚀去掉牺牲层和所述硬掩膜，在沟槽内壁中热生长一层氧化层；
再在所述沟槽内回填氧化物，通过光刻和刻蚀形成矩形槽；
通过化学机械抛光在所述矩形槽内抛磨出内壁为曲面的弧形沟槽；
在所述弧形沟槽内淀积掺杂的导电多晶硅，向导电多晶硅中注入磷和硼并退火。
较佳地，所述再在所述沟槽内回填氧化物具体为：采用高密度等离子体化学气相淀积工艺将回填的氧化物淀积在所述氧化层上。
较佳地，所述弧形沟槽为一侧为凸出弧形结构，一侧为内凹弧形结构。
本发明还提供一种功率半导体结构，包括基底，其特征在于，在所述基底上表面向下注入磷/砷后在所述基底上表面淀积有硬掩膜，在硬掩膜形成沟槽，所述沟槽内壁具有一层氧化层；所述氧化层被抛磨为曲面的弧形沟槽；所述弧形沟槽为一侧为凸出弧形结构，一侧为内凹弧形结构；所述弧形沟槽内淀积掺杂导电多晶硅。
本发明的有益效果是：
1、本发明去掉了外延片，常规MOS 都需要外延片，外延片的规格不能随意调节，造成了生产效率很低，可能需要多个工程批才能得到想要的电压值，本发明不需要外延片，仅通过版图及工艺控制沟槽的尺寸及注入的规格来调节BV ，可以通过多组分批，得到需要的耐压范围。
2、本发明的新型功率半导体结构的电压的调节更灵活，通过版图及工艺即可调整，可以仅仅调节弧形凹槽的内壁的曲率即可实现耐压调节，减少了光刻掩模的调整，通过更少的工程批调节沟槽尺寸及注入规格。
3、本发明不需要进行减薄背金，对减低成本及缩短生产周期也有非常好的提高。
4、导电多晶硅在沟槽一侧形成导电沟道，另一侧填充厚氧化层，金属电极都在芯片正面，该结构电流输入端和输出端都在正面，同时也可以保证MOS流通大电流。
附图说明
图1（a）-1（f）为功率半导体沟槽尺寸控制工艺流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例1
本实施例提供一种功率半导体沟槽尺寸控制方法，如图1（a）-1（f）所示，包括如下步骤：
S1、提供基底1，从所述基底1上表面向下注入磷/砷；
S2、在所述基底1上表面淀积硬掩膜，通过光刻在硬掩膜形成沟槽图形，然后对基底1进行刻蚀，形成沟槽2；沟槽分为元胞沟槽和终端沟槽；
S3、湿法腐蚀去掉牺牲层和所述硬掩膜，在沟槽2内壁中热生长一层氧化层3；
S4、再在所述沟槽2内回填氧化物4，所述氧化物4一般为SiO2，通过光刻和刻蚀形成矩形槽5；
S5、由于氧化物是在热生长的，要准确的控制厚度，就需要后续打磨；通过化学机械抛光（CMP）在所述矩形槽5内抛磨出内壁为曲面的弧形沟槽6，沟槽内部的氧化层要做成一侧厚，一侧薄，薄的一侧，薄的一侧作为栅氧，厚的一侧是为了隔离导电多晶硅7和体区，以便于后续步骤对导电多晶硅7的掺杂和生长；
S6、在所述弧形沟槽6内淀积掺杂的导电多晶硅7，向导电多晶硅7中注入磷和硼，并退火，之后用干法刻蚀去掉多余的导电多晶硅7。
本实施例中，所述弧形沟槽为一侧厚的为凸出弧形结构，一侧薄为内凹弧形结构。
实施例2
如图1所示，本实施例提供一种功率半导体结构，包括基底1，在所述基底1上表面向下注入磷/砷后在所述基底1上表面淀积有硬掩膜，在硬掩膜形成沟槽2，所述沟槽2内壁具有一层氧化层3；所述氧化层3被抛磨为曲面的弧形沟槽6；所述弧形沟槽6为一侧为凸出弧形结构，一侧为内凹弧形结构；所述弧形沟槽6内淀积掺杂导电多晶硅7。
综合上述实施例可知本发明的技术效果如下：本发明的功率半导体结构去掉了外延片，电压调节更灵活，通过版图及工艺即可调整，可以仅仅调节弧形凹槽的内壁的曲率即可实现耐压调节，减少了光刻掩模的调整，通过更少的工程批调节沟槽尺寸及注入规格。而且，本发明不需要进行减薄背金，对减低成本及缩短生产周期也有非常好的提高。导电多晶硅在沟槽一侧形成导电沟道，另一侧填充厚氧化层，金属电极都在芯片正面，该结构电流输入端和输出端都在正面，同时也可以保证MOS流通大电流。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由所附权利要求及其等同物限定。

Claims (3)

1.一种功率半导体沟槽尺寸控制方法，其特征在于，包括如下步骤：
提供基底，从所述基底上表面向下注入磷/砷；
在所述基底上表面淀积硬掩膜，通过光刻在硬掩膜形成沟槽图形，然后对基底进行刻蚀，形成沟槽；
湿法腐蚀去掉牺牲层和所述硬掩膜，在沟槽内壁中热生长一层氧化层；
再在所述沟槽内回填氧化物，通过光刻和刻蚀形成矩形槽；
通过化学机械抛光在所述矩形槽内抛磨出内壁为曲面的弧形沟槽；所述弧形沟槽为一侧为凸出弧形结构，一侧为内凹弧形结构；所述凸出弧形结构一侧的氧化层厚度大于所述内凹弧形结构一侧的氧化层厚度；
在所述弧形沟槽内淀积掺杂的导电多晶硅，向导电多晶硅中注入磷和硼并退火。
2.如权利要求1所述的功率半导体沟槽尺寸控制方法，其特征在于，所述再在所述沟槽内回填氧化物具体为：采用高密度等离子体化学气相淀积工艺将回填的氧化物淀积在所述氧化层上。
3.一种功率半导体结构，包括基底，其特征在于，在所述基底上表面向下注入磷/砷后在所述基底上表面淀积有硬掩膜，在硬掩膜形成沟槽图形，然后对基底进行刻蚀，形成沟槽，所述沟槽内壁具有一层氧化层；所述氧化层被抛磨为曲面的弧形沟槽；所述弧形沟槽为一侧为凸出弧形结构，一侧为内凹弧形结构；所述凸出弧形结构一侧的氧化层厚度大于所述内凹弧形结构一侧的氧化层厚度；所述弧形沟槽内淀积掺杂导电多晶硅。
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