CN111490094B - 一种带ESD保护结构的trench分离栅DMOS器件制作方法 - Google Patents
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Abstract
本发明公开一种带ESD保护结构的trench分离栅DMOS器件制作方法,属于半导体功率器件技术领域。在N型外延片生长氧化层、淀积氮化硅层和TEOS层,挖出若干个Trench结构;在Trench结构中制作一层氧化层,并填充掺杂N型多晶硅;对Trench结构中多晶硅进行刻蚀,再将有源区Trench结构侧壁的上部分氧化层去除掉;在Trench结构中填充介质,研磨外延片至表面平坦,使氮化硅层和氧化硅处于同一平面;形成保护二极管结构并实现P型掺杂;分离栅底部结构和保护二极管结构;完成栅极引出,阱工艺和源区引出;通过光刻和腐蚀实现通孔引出和金属互联。本发明基于目前低功耗分离栅Trench DMOS产品结构,把ESD保护结构集成在栅源两极之间,在满足使用中对功耗要求外,又保证器件性能和可靠性。
Description
技术领域
本发明涉及半导体功率器件技术领域,特别涉及一种带ESD保护结构的trench分离栅DMOS器件制作方法。
背景技术
随着VDMOS产品应用领域的不断扩大,器件所需的性能和可靠性要求就越来越高。VDMOS器件重要的性能指标参数FOM(figure of merit)为Qg*Ron(栅电荷和导通电阻乘积)。此参数表征器件在开关和导通过程中,功率损耗主要来自开关损耗和导通损耗。开关损耗主要于器件在开关过程中,对栅充放电过程中功率损耗,特别对于高频器件来说,此步损耗尤为显著。导通损耗为器件在工作状态下,整个器件串联电阻的损耗。
在器件开关过程中,栅上产生的浪涌电压一般会超出实际栅电压数倍以上。为了有效保护栅电极,需要在栅极和源极并联一个ESD保护二极管。当栅源之间有较高的浪涌电压时,电流可以通过ESD保护二极管流通,避免栅氧化层电流过大,烧毁栅极。一般的做法是增加一层场氧层次,把ESD保护结构的多晶放置在场氧上,见图1。利用场氧作为ESD多晶硅的垫层。此场氧为阱注入自对准的掩蔽层,为满足此阱注入自对准要求,对场氧厚度有要求,一般厚度约ESD多晶硅厚度一般在这两层总厚度在这就使得产品在介质平坦化时ESD多晶硅上介质一般都比较薄。金属互联刻蚀工艺需要把ESD多晶硅分别做栅源级引出,这时在多晶硅表面就会有金属打开区域,一般来说为保证多晶硅表面不被金属刻蚀损失,需要严格控制此步刻蚀介质损失量,工艺控制难度较大,可靠性有较大风险。
发明内容
本发明的目的在于提供一种带ESD保护结构的trench分离栅DMOS器件制作方法,以提升器件性能并改善产品可靠性品质。
为解决上述技术问题,本发明提供一种带ESD保护结构的trench分离栅DMOS器件制作方法,包括:
在N型外延片生长氧化层、淀积氮化硅层和TEOS层,挖出若干个Trench结构;
在Trench结构中制作一层氧化层,并填充掺杂N型多晶硅;
对Trench结构中多晶硅进行刻蚀,再将有源区Trench结构侧壁的上部分氧化层去除掉;
在Trench结构中填充介质,研磨外延片至表面平坦,使氮化硅层和氧化硅处于同一平面;
形成保护二极管结构并实现P型掺杂;分离栅底部结构和保护二极管结构;
完成栅极引出,阱工艺和源区引出;
通过光刻和腐蚀实现通孔引出和金属互联。
可选的,对Trench结构中多晶硅进行刻蚀包括:
通过刻蚀使所有Trench结构中多晶硅的高度低于外延片表面;
把外围隔离Trench结构,以及底部多晶需要引出的Trench结构覆盖光刻胶,对其余Trench结构中的多晶硅进行刻蚀。
可选的,形成保护二极管结构并实现P型掺杂包括:
把用于保护二极管的多晶硅淀积在外延片上,并且通过离子注入的方式,实现P型掺杂;
保留栅区用来做保护二极管结构的多晶硅,通过多晶腐蚀来刻蚀掉其他区域的多晶硅。
可选的,分离栅底部结构和保护二极管结构包括:
利用光刻和腐蚀,把有源区Trench结构中的氧化层腐蚀到需要保留的厚度。
可选的,完成栅极引出,阱工艺和源区引出;通过光刻和腐蚀实现通孔引出和金属互联包括:
生长栅氧化层和淀积N型多晶栅,并通过多晶栅回刻工艺完成栅级引出;
通过注入P型杂质和退火工艺,完成阱工艺;
利用源区光刻和注入,实现源区引出;
利用光刻和腐蚀实现通孔引出和金属互联。
可选的,所述Trench结构的深度为2~4μm。
本发明提供一种带ESD保护结构的trench分离栅DMOS器件制作方法,在N型外延片生长氧化层、淀积氮化硅层和TEOS层,挖出若干个Trench结构;在Trench结构中制作一层氧化层,并填充掺杂N型多晶硅;对Trench结构中多晶硅进行刻蚀,再将有源区Trench结构侧壁的上部分氧化层去除掉;在Trench结构中填充介质,研磨外延片至表面平坦,使氮化硅层和氧化硅处于同一平面;形成保护二极管结构并实现P型掺杂;分离栅底部结构和保护二极管结构;完成栅极引出,阱工艺和源区引出;通过光刻和腐蚀实现通孔引出和金属互联。
本发明基于目前低功耗分离栅Trench DMOS产品结构,把ESD保护结构集成在栅源两级之间,在满足使用中对功耗要求外,又保证器件性能和可靠性;能够有效降低栅电容,同时利用多晶场板结构降低外延电阻率,优化器件导通电阻。
附图说明
图1是普通带ESD结构DMOS器件示意图;
图2是Trench分离栅DMOS器件结构示意图;
图3是在外延片上形成氧化层、氮化硅层和TEOS层示意图;
图4是形成Trench工艺结构示意图;
图5是在Trench结构中形成氧化层和多晶硅示意图;
图6是两次刻蚀后的示意图;
图7是刻蚀侧壁氧化层的示意图;
图8是在Trench结构中填充介质并研磨平坦化的示意图;
图9是ESD多晶硅刻蚀后形貌图;
图10是分离栅底部结构和保护二极管结构示意图;
图11是完成栅极引出和阱工艺的示意图;
图12是实现源区引出的示意图;
图13是带ESD保护结构Trench分离栅器件整体示意图;
图14是Trench分离栅DMOS平面俯视图。
具体实施方式
以下结合附图和具体实施例对本发明提出的一种带ESD保护结构的trench分离栅DMOS器件制作方法作进一步详细说明。根据下面说明,本发明的优点和特征将更清楚。需说明的是,附图均采用非常简化的形式且均使用非精准的比例,仅用以方便、明晰地辅助说明本发明实施例的目的。
实施例一
目前为降低导通电阻和改善开关特性,已有分离栅DMOS产品,见图2。本发明在分离栅DMOS工艺基础上,把ESD多晶二极管保护结构集成上去,其中ESD保护结构放在栅极打线位置。本发明提供了一种带ESD保护结构的trench分离栅DMOS器件制作方法,在高密度低导通电阻的分离栅器件基础上,集成多晶保护二极管,这样就可以在性能优越的DMOS器件上提升了产品可靠性品质。本实施例一以N型器件为例,P型器件可以按相应方法得到,制作方法包括如下步骤:
利用trench光刻与腐蚀工艺挖出若干个Trench结构(包括图4中的Isolationtrench、Source trench和Gate trench),其深度为2~4μm,与产品实际需求相匹配,如图4;
完成Trench结构后,在Trench结构中制作一层SiO2氧化层,可以采用热生长或化学气相淀积等方式实现,Trench结构中的氧化层厚度根据实际产品耐压需求来确定;接着在Trench结构中填充掺杂N型多晶硅,厚度需要把Trench结构全部填满,如图5;
先做一次多晶刻蚀,使所有Trench结构中多晶硅的高度低于外延片表面,约接下来采用多晶光刻,把外围隔离Trench结构以及底部多晶需要引出的Trench结构覆盖光刻胶,其他位置打开,同样采用多晶刻蚀,把未覆盖光刻胶的Trench结构中多晶刻蚀0.8~1.5μm,如图6所示;
刻蚀多晶硅后,利用湿法腐蚀去除未覆盖光刻胶的Trench结构(即有源区Trench结构)中的上半部分侧壁氧化层,如图7;
利用高密度等离子体化学气相淀积,对所有Trench结构中进行介质填充,并进行化学机械研磨,实现表面平坦化,如图8;
把用于做保护二极管的多晶硅淀积在外延片上,并且通过离子注入的方式,实现P型掺杂;再通过多晶光刻和腐蚀,只保留栅区用来做保护二极管结构的多晶硅,其他区域全部通过多晶腐蚀来刻蚀掉,如图9所示;完成此工艺后,就把做多晶保护二极管的结构完成,并且实现了P型掺杂;在此之后我们利用湿法腐蚀,去除其他位置氮化硅;
完成保护二极管结构后,利用光刻和腐蚀,把有源区Trench结构中氧化层腐蚀到需要保留的厚度,至此完成了分离栅底部结构和保护二极管结构,如图10;
接下来和普通Trench DMOS器件工艺相同,生长栅氧化层和淀积N型多晶栅,并通过多晶栅回刻工艺完成栅极出;做完栅极后通过注入P型杂质和退火工艺,完成阱工艺,如图11;
阱工艺完成后,利用源区光刻和注入,实现源区引出,在此指出,多晶二极管N型注入和此步共用光刻版和注入工艺,至此就完成整个器件的前道工艺,如图12;
做完器件区域后,通过光刻和腐蚀来实现通孔引出和金属互联,这些工艺参考标准工艺即可,在此不再赘述,器件完成整体示意图见图13。
通过本发明提供的制作方法制作出的器件俯视图见图14,分成源区(Source)和栅区(Gate)两个部分,这两个区域与外界用trench方式隔离。器件的漏区(Drain)在晶圆的背面。本发明的工艺主要是针对晶圆栅源区域,漏区只需要做背面减薄镀金属引出即可。其中源区是做Trench原胞区,采用重复阵列Trench结构。栅区没有Trench结构,此处我们放置ESD保护结构。在源栅区域外围我们采用Trench隔离环来实现结终止。
上述描述仅是对本发明较佳实施例的描述,并非对本发明范围的任何限定,本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰,均属于权利要求书的保护范围。
Claims (5)
1.一种带ESD保护结构的trench分离栅DMOS器件制作方法,其特征在于,包括:
在N型外延片生长氧化层、淀积氮化硅层和TEOS层,挖出若干个Trench结构;
在Trench结构中制作一层氧化层,并填充掺杂N型多晶硅;
对Trench结构中多晶硅进行刻蚀,再将有源区Trench结构侧壁的上部分氧化层去除掉;
在Trench结构中填充介质,研磨外延片至表面平坦,使氮化硅层和氧化硅处于同一平面;
形成保护二极管结构并实现P型掺杂;分离栅底部结构和保护二极管结构;
完成栅极引出,阱工艺和源区引出;
通过光刻和腐蚀实现通孔引出和金属互联;
形成保护二极管结构并实现P型掺杂包括:把用于保护二极管的多晶硅淀积在外延片上,并且通过离子注入的方式,实现P型掺杂;
保留栅区用来做保护二极管结构的多晶硅,通过多晶腐蚀来刻蚀掉其他区域的多晶硅;
分离栅底部结构和保护二极管结构包括:
利用光刻和腐蚀,把有源区Trench结构中的氧化层腐蚀到需要保留的厚度。
3.如权利要求1所述的带ESD保护结构的trench分离栅DMOS器件制作方法,其特征在于,对Trench结构中多晶硅进行刻蚀包括:
通过刻蚀使所有Trench结构中多晶硅的高度低于外延片表面;
把外围隔离Trench结构,以及底部多晶需要引出的Trench结构覆盖光刻胶,对其余Trench结构中的多晶硅进行刻蚀。
4.如权利要求1所述的带ESD保护结构的trench分离栅DMOS器件制作方法,其特征在于,完成栅极引出,阱工艺和源区引出;通过光刻和腐蚀实现通孔引出和金属互联包括:
生长栅氧化层和淀积N型多晶栅,并通过多晶栅回刻工艺完成栅级引出;
通过注入P型杂质和退火工艺,完成阱工艺;
利用源区光刻和注入,实现源区引出;
利用光刻和腐蚀实现通孔引出和金属互联。
5.如权利要求1所述的带ESD保护结构的trench分离栅DMOS器件制作方法,其特征在于,所述Trench结构的深度为2~4μm。
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