CN114709307A - A flip-chip light-emitting diode chip and preparation method thereof - Google Patents

Abstract

The invention provides a flip-chip light-emitting diode chip and a preparation method thereof. The flip-chip light-emitting diode chip comprises an N-type semiconductor layer, an active light-emitting layer, a P-type semiconductor layer, a current blocking layer, a current spreading layer, and a Bragg reflection layer stacked in sequence. layer and a current transmission layer, the Bragg reflection layer includes a P-type Bragg reflection part and an N-type Bragg reflection part, the current transmission layer includes a P-type current transmission part and an N-type current transmission part, wherein, on the P-type Bragg reflection part A first through hole is opened, a second through hole is opened on the N-type Bragg reflector, and the first through hole is used to electrically connect the P-type current transmission part and the current spreading layer. The second through hole is used for the electrical connection between the N-type current transmission part and the N-type semiconductor layer, and the light absorption of the current transmission layer is reduced without changing the current transmission capability, thereby improving the brightness of the flip-chip LED chip .

Description

A flip-chip light-emitting diode chip and preparation method thereof

technical field

The invention relates to the field of semiconductor devices, in particular to a flip-chip light-emitting diode chip and a preparation method thereof.

Background technique

In recent years, the LED industry has developed and upgraded rapidly. With its advantages of energy saving, high efficiency and high reliability, it is used in general lighting, special lighting, plant lighting, landscape lighting, indoor display, outdoor display, backlight display, ultraviolet disinfection, ultraviolet curing and other scenarios, and LED chips play a huge role in it.

At present, the LED chip structure is mainly divided into three types, the most common is the front-mounted structure, followed by the vertical structure and the flip-chip structure. The front-mounted structure is prone to current crowding and high thermal resistance because the p and n electrodes are on the same side of the LED, while the vertical structure can solve these two problems well and achieve high current density and uniformity at the same time. In addition to the cost of materials, the reduction of the cost of lamps in the future is particularly important to reduce the number of LEDs while the power increases. The vertical structure can well meet such needs, which also leads to the vertical structure is usually used in high-power LED applications, while the formal installation The technology is generally used in small and medium-power LEDs. In addition, flip-chip technology can also be subdivided into two categories. One is flip-chip on the basis of sapphire, and the sapphire substrate is retained, which is good for heat dissipation, but the current density increase is not obvious; the other type is The flip-chip structure is adopted but the substrate material is peeled off, which can achieve a substantial increase in current density.

With the development of the industry, how to make the flip-chip light-emitting diode chip emit brighter and higher light efficiency without stripping the substrate material has become our infinite pursuit.

SUMMARY OF THE INVENTION

Based on this, the present invention provides a flip-chip light-emitting diode chip and a preparation method thereof, which aim to improve light-emitting brightness without peeling off the substrate material of the flip-chip light-emitting diode chip.

A flip-chip light-emitting diode chip according to an embodiment of the present invention includes an N-type semiconductor layer, an active light-emitting layer, a P-type semiconductor layer, a current blocking layer, a current spreading layer, a Bragg reflection layer, and a current transmission layer stacked in sequence, The Bragg reflection layer includes a P-type Bragg reflection part and an N-type Bragg reflection part, and the current transmission layer includes a P-type current transmission part and an N-type current transmission part, wherein the P-type Bragg reflection part is provided with a first through hole , the N-type Bragg reflector is provided with a second through hole, the first through hole is used to electrically connect the P-type current transmission part and the current spreading layer, and the second through hole is used for The N-type current transfer portion is electrically connected to the N-type semiconductor layer.

Preferably, the flip-chip LED chip further comprises a substrate, a buffer layer, an insulating protection layer and a bonding metal layer;

the buffer layer, the N-type semiconductor layer, the active light-emitting layer, the P-type semiconductor layer, the current blocking layer, the current spreading layer, the Bragg reflection layer, the current transport layer, The insulating protection layer and the bonding metal layer are sequentially stacked on the substrate.

Preferably, the current spreading layer is an indium tin oxide layer, and the thickness of the current spreading layer is

Preferably, the Bragg reflection layer is a periodic structure in which low refractive index layers and high refractive index layers are alternately stacked, wherein the low refractive index layer is a SiO ₂ layer, and the high refractive index layer is a Ti ₃ O ₅ layer .

Preferably, the area of the first through hole and the second through hole is 20um ² to 1000um ² .

Preferably, a plurality of the first through holes and the second through holes are respectively provided, and the interval between two adjacent first through holes is 10 μm˜200 μm, and two adjacent second through holes are spaced between 10 μm and 200 μm. The spacing between the through holes is 10 μm˜200 μm.

Preferably, the insulating protection layer includes a P-type insulating protection portion and an N-type insulating protection portion, the bonding metal layer includes a P-type bonding metal portion and an N-type bonding metal portion, and the P-type insulating protection portion is on the A third through hole is opened, a fourth through hole is opened on the N-type insulating protection part, the P-type insulating protection part and the P-type current transmission part are electrically connected through the third through hole, and the The N-type insulating protection part and the N-type current transmission part are electrically connected through the fourth through hole.

Preferably, the flip-chip light emitting diode chip is further provided with an isolation groove, and the angle of the isolation groove is 30°˜80°.

A method for preparing a flip-chip light-emitting diode chip according to an embodiment of the present invention is used to prepare the above-mentioned flip-chip light-emitting diode chip, and the preparation method includes:

providing a substrate required for growth;

A buffer layer, an N-type semiconductor layer, an active light-emitting layer, a P-type semiconductor layer, a current blocking layer, a current spreading layer, a Bragg reflection layer, a current transport layer, an insulating protective layer and a bonding metal are sequentially epitaxially grown on the substrate Floor;

Wherein, after the Bragg reflection layer is grown, a first through hole and a second through hole are etched on the Bragg reflection layer.

Preferably, the process of etching the first through hole and the second through hole is an inductively coupled plasma etching process.

Compared with the prior art: the present invention adopts the N-type semiconductor layer, the active light-emitting layer, the P-type semiconductor layer, the current blocking layer, the current spreading layer, the Bragg reflection layer and the current transmission layer stacked in sequence, because the Bragg reflection layer includes P Type Bragg reflection part and N type Bragg reflection part, and through holes are respectively opened on the P type Bragg reflection part and N type Bragg reflection part, at the same time, the current transmission layer is placed on the Bragg reflection layer, so that the current transmission layer The P-type current transmission part and the N-type current transmission part are electrically connected to the current spreading layer and the N-type semiconductor layer respectively through vias, which reduce the light absorption of the current transmission layer without changing the current transmission capability, thereby improving the flip chip LED chip brightness.

Description of drawings

FIG. 1 is a schematic structural diagram of a flip-chip light-emitting diode chip in Embodiment 1 of the present invention;

FIG. 2 is a schematic top view of the flip-chip LED chip in the first embodiment of the present invention;

3 is a flow chart of a method for fabricating a flip-chip light-emitting diode chip in Embodiment 2 of the present invention;

4 is a schematic top view of a flip-chip light-emitting diode chip in Embodiment 4 of the present invention;

FIG. 5 is a schematic top view of a flip-chip light-emitting diode chip in Embodiment 5 of the present invention;

FIG. 6 is a schematic structural diagram of a flip-chip light emitting diode chip in Embodiment 5 of the present invention.

Detailed ways

In order to facilitate understanding of the present invention, the present invention will be described more fully hereinafter with reference to the related drawings. Several embodiments of the invention are presented in the accompanying drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It should be noted that when an element is referred to as being "fixed to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and similar expressions are used herein for illustrative purposes only.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Example 1

Please refer to FIGS. 1 and 2. FIG. 1 is a schematic structural diagram of a flip-chip LED chip in Embodiment 1 of the present invention, and FIG. 2 is a schematic top view of the flip-chip LED chip in Embodiment 1 of the present invention. The light-emitting diode chip includes a substrate 21, a buffer layer 221, an N-type semiconductor layer 222, an active light-emitting layer 223, a P-type semiconductor layer 224, a current blocking layer 23, a current spreading layer 24, Bragg reflection layer 25, current transport layer, insulating protective layer 27 and bonding metal layer.

示例而非限定，在一些实施例当中，电流扩展层24的厚度可以为，例如

等，其中，氧化铟锡是一种混合物，由90％浓度的In₂O₃和10％浓度的SnO₂混合而成。另外，布拉格反射层25为低折射率层与高折射率层交替层叠的周期性结构，其中，所述低折射率层为SiO₂层，所述高折射率层为Ti₃O₅层，需要说明的是，布拉格反射层25中低折射率层与高折射率层交替层叠的周期性为10个～30个，例如为15个，即布拉格反射层25中的低折射率层和高折射率层分别有15层，可以理解的，布拉格反射层25中低折射率层首先沉积于电流扩展层24上，其次再在低折射率层上沉积高折射率层。In this embodiment, the substrate 21 may be a sapphire substrate 21 , the material of the current blocking layer 23 may be one or more of SiO ₂ , SiN and Ti ₃ O ₅ , and the current spreading layer 24 is an indium tin oxide layer , the thickness of the current spreading layer 24 is

By way of example and not limitation, in some embodiments, the thickness of the current spreading layer 24 may be, for example,

etc., where indium tin oxide is a mixture consisting of 90% concentration of _In2O3 and ₁₀ % concentration of _SnO2 . In addition, the Bragg reflection layer 25 is a periodic structure in which low-refractive index layers and high-refractive index layers are alternately stacked, wherein the low-refractive index layer is a SiO ₂ layer, and the high-refractive index layer is a Ti ₃ O ₅ layer. It should be noted that the periodicity of alternately stacking low-refractive index layers and high-refractive-index layers in the Bragg reflection layer 25 is 10 to 30, for example, 15, that is, the low-refractive-index layers and the high-refractive-index layers in the Bragg reflection layer 25 There are 15 layers respectively. It can be understood that the low refractive index layer in the Bragg reflection layer 25 is first deposited on the current spreading layer 24, and then the high refractive index layer is deposited on the low refractive index layer.

Further, the material of the current transport layer is one or more of Cr, Al, Ti, Ni, Pt, and Au, and the material of the insulating protective layer 27 is one or more of SiO ₂ , SiN, and Ti ₃ O ₅ . The material of the bonding metal layer is one or more of Cr, Al, Ti, Ni, Pt, and Au.

It should be noted that the Bragg reflection layer 25 includes a P-type Bragg reflection part and an N-type Bragg reflection part, the P-type Bragg reflection part is provided with a first through hole 131, and the N-type Bragg reflection part is provided with a second through hole 132, Among them, the P-type Bragg reflector is deposited on the current spreading layer 24. After the P-type semiconductor layer 224 is grown, the MESA step 12 is formed by etching, and part of the N-type semiconductor layer 222 is exposed, so the N-type Bragg reflector is made. Part of the N-type semiconductor layer 222 is deposited on the N-type semiconductor layer 222. After the MESA step 12 is etched, part of the N-type semiconductor layer 222 and the buffer layer 221 need to be etched on the basis of the MESA step 12 until the substrate 21 is exposed. After the etching, an isolation trench 11 will be formed between the substrate 21 and the etched inclined buffer layer 221. The isolation trench 11 is used to separate the chips. The angle of the isolation trench 11 is 30° to 80°. To define, in some embodiments, the angle of the isolation groove 11 may be, for example, 40°, 50°, 60°, and the like.

In addition, the current transfer layer deposited on the Bragg reflection layer 25 includes a P-type current transfer portion 261 and an N-type current transfer portion 262. It can be understood that the P-type current transfer portion 261 is electrically connected to the current spreading layer 24 through the first through hole 131 , the N-type current transmission part 262 is electrically connected to the N-type semiconductor layer 222 through the second through hole 132 .

Specifically, a plurality of first through holes 131 and second through holes 132 are respectively provided, and the interval between two adjacent first through holes 131 is 10 μm˜200 μm, and the distance between two adjacent second through holes 132 is 10 μm˜200 μm. The interval is 10 μm˜200 μm, wherein the straight line formed by the side-by-side arrangement of the plurality of first through holes 131 is parallel to the line formed by the side-by-side arrangement of the plurality of second through holes 132 , which is an example but not a limitation. In a preferred embodiment, the interval between two adjacent first through holes 131 is, for example, 20 μm, 30 μm, 40 μm, etc., and the interval between two adjacent second through holes 132 is, for example, 20 μm, 30 μm, 40 μm, etc. etc., in this embodiment, there are seven first through holes 131, and the first through holes 131 are spaced 20 μm apart. The positions of the first through holes 131 at the other end are 0 μm, 20 μm, 40 μm, 60 μm, 80 μm, 100 μm, and 120 μm, respectively.

In addition, by way of example but not limitation, in some preferred embodiments of this embodiment, the area of the first through hole 131 is 20 μm ² to 1000 μm ² , such as 100 μm ² , 200 μm ² , 300 μm ² , etc. The area is 20 μm ² to 1000 μm ² , for example, 100 μm ² , 200 μm ² , 300 μm ² or the like.

It should be noted that an insulating protective layer 27 and a bonding metal layer are sequentially deposited on the current transport layer, wherein the insulating protective layer 27 includes a P-type insulating protective portion and an N-type insulating protective portion, and the bonding metal layer includes a P-type insulating protective portion. The bonding metal portion 281 and the N-type bonding metal portion 282, the P-type insulating protection portion is provided with a third through hole 141, the N-type insulating protection portion is provided with a fourth through hole 142, the P-type bonding metal portion 281 and the The P-type current transmission portion 261 is electrically connected through the third through hole 141 , and the N-type bonding metal portion 282 and the N-type current transmission portion 262 are electrically connected through the fourth through hole 142 . It can be understood that the P-type bonding metal portion 281 is electrically connected to the P-type current transmission part 261 through the third through hole 141, the P-type current transmission part 261 is electrically connected to the current spreading layer 24 through the first through hole 131, and the N-type bonding metal part 282 is electrically connected through the first through hole 131. The four through holes 142 are electrically connected to the N-type current transmission portion 262 , and the N-type current transmission portion 262 is further electrically connected to the N-type semiconductor layer 222 through the second through hole 132 . In addition, in this embodiment, the number of the third through hole 141 and the fourth through hole 142 is one, respectively.

To sum up, in the present invention, the N-type semiconductor layer 222, the active light-emitting layer 223, the P-type semiconductor layer 224, the current blocking layer 23, the current spreading layer 24, the Bragg reflection layer 25 and the current transmission layer are sequentially stacked. 25 includes a P-type Bragg reflection part and an N-type Bragg reflection part, and through holes are respectively opened on the P-type Bragg reflection part and the N-type Bragg reflection part, and at the same time, the current transmission layer is placed on the Bragg reflection layer 25, so that The P-type current transfer portion 261 and the N-type current transfer portion 262 of the current transfer layer are electrically connected to the current spreading layer 24 and the N-type semiconductor layer 222 through vias, respectively, and the current transfer layer is reduced without changing the current transfer capability. light absorption, thereby improving the brightness of the flip-chip light-emitting diode chip.

Embodiment 2

Please refer to FIG. 3 , which shows a method for preparing a flip-chip light-emitting diode chip according to the second embodiment of the present invention, which is used to prepare the flip-chip light-emitting diode chip in the above-mentioned first embodiment. The method specifically includes steps S201 to S207 . in:

Step S201, providing a substrate required for growth.

Wherein, the substrate may be a sapphire substrate.

Step S202, a buffer layer, an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer are sequentially epitaxially grown on the substrate.

Step S203, forming MESA steps.

In this embodiment, first, a pattern is formed on the surface of the P-type semiconductor layer using photolithography technology, and then an inductively coupled plasma etching process is used to etch from the P-type semiconductor layer to the substrate direction to remove part of the N-type semiconductor layer, The active light-emitting layer and the P-type semiconductor layer are then removed, and the photoresist residue is removed, and the N-type semiconductor layer is partially exposed to form MESA steps.

In step S204, a current blocking layer is deposited, and an isolation trench is formed.

Specifically, a PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition) process is used to deposit SiO ₂ on the surface of the P-type semiconductor layer and the MESA step surface, and then a photolithography process is used to form a pattern, and a part of the SiO is etched away by the BOE solution. ₂ , forming a current blocking layer.

Then, a pattern is formed on the surface of the MESA step by photolithography, and then the inductively coupled plasma etching process is used to etch from the MESA step to the substrate, and part of the N-type semiconductor layer and buffer layer are removed until the substrate is exposed. The photoresist is removed to form an isolation trench. In this embodiment, the opening angle of the isolation trench is 50°.

Step S205, depositing a current spreading layer and a Bragg reflection layer, and opening holes on the Bragg reflection layer.

It should be noted that the magnetron sputtering technology is used to deposit the current spreading layer, wherein the current spreading layer is an indium tin oxide layer, and then a pattern is formed on the current spreading layer by using a photolithography technique, and further, an indium tin oxide etching solution is used to corrode Part of the current spreading layer is removed. It is understandable that the current spreading layer is only deposited on the P-type semiconductor layer and the current blocking layer, while the current spreading layer is not deposited on the MESA steps. Finally, the excess photoresist is removed to form the current spreading layer.

After the current spreading layer is deposited, the Bragg reflection layer is deposited by electron beam evaporation. Specifically, a Bragg reflection layer is deposited on the substrate, MESA steps and the current spreading layer, and then a pattern is formed on the surface of the Bragg reflection layer, and then an inductor is used. The coupled plasma etching process removes part of the Bragg reflection layer and removes the photoresist to form through holes in the Bragg reflection layer, wherein the Bragg reflection layer includes a P-type Bragg reflection part and an N-type Bragg reflection part, and the P-type Bragg reflection part is deposited On the current spreading layer, the N-type Bragg reflector is deposited on the MESA step. Further, the P-type Bragg reflector is provided with a first through hole, and the N-type Bragg reflector is provided with a second through hole.

In this embodiment, the first through hole and the second through hole are both circular, and in some other embodiments, the shape of the first through hole and the second through hole may also be other shapes, such as a square, etc., wherein , the areas of the first through holes and the second through holes are both 314.15 μm ² , the interval between the first through holes is 50 μm, and the interval between the second through holes is 50 μm.

Step S206, depositing a current transport layer.

Specifically, a negative photoresist is coated on the Bragg reflection layer, a pattern is formed by exposure and development, and then metal Cr, Al, Ti, Pt, Au, Pt, and Ti are evaporated by an electron beam evaporation process, and then Lift- The Off process (metal stripping process) peels off part of the metal to form a current transmission layer. It should be noted that the current transmission layer includes a P-type current transmission part and an N-type current transmission part, wherein the P-type current transmission part is deposited on the P-type Bragg reflection On the part, the N-type current transmission part is deposited on the N-type Bragg reflector. It can be understood that the P-type current transmission part fills the first through hole, and the N-type current transmission part fills the second through hole. Then, the first through hole is filled. The hole realizes the electrical connection between the P-type current transmission part and the current spreading layer, and the second through hole realizes the electrical connection between the N-type current transmission part and the N-type semiconductor layer, that is, contacts with the MESA step.

Step S207, depositing an insulating protective layer and a bonding metal layer.

It should be noted that, after the current transport layer is deposited, SiO ₂ is deposited by PECVD process to form an insulating protective layer, wherein the insulating protective layer includes a P-type insulating protective portion and an N-type insulating protective portion, and then a photolithography process is used to form the insulating protective layer. A pattern is formed on the protective layer, and then part of the insulating protective layer is etched away by using the BOE solution, that is, the P-type insulating protective part and the N-type insulating protective part are respectively opened to form the third through hole and the fourth through hole. It can be understood that, The third through hole is arranged above the P-type current transmission part, and the fourth through hole is arranged above the N-type current transmission part.

Specifically, after the insulating protective layer is deposited and the holes are opened, a negative photoresist is coated, exposed and developed to form a pattern, and then metal Cr, Al, Ti, Pt, Au, Pt are evaporated by an electron beam evaporation process. , Ti, and then use the Lift-Off process to peel off part of the metal, and remove the excess photoresist to obtain a bonding metal layer. The bonding metal layer includes a P-type bonding metal part and an N-type bonding metal part, which can be It is understood that the P-type bonding metal part fills the third through hole, and the N-type bonding metal part fills the fourth through hole, then the P-type bonding metal part and the P-type current transmission part pass through the third through hole For electrical connection, the N-type bonding metal part and the N-type current transmission part are electrically connected through the fourth through hole.

Embodiment 3

Referring to FIG. 1 and FIG. 2 , the third embodiment of the present invention provides a flip-chip light-emitting diode chip. In this embodiment, a buffer layer 221 , an N-type semiconductor layer 222 , a buffer layer 221 , an N-type semiconductor layer 222 , and a sapphire substrate 21 are epitaxially grown on the provided sapphire substrate 21 in sequence. The source light-emitting layer 223, the P-type semiconductor layer 224, and the MESA step 12 is formed, then the current blocking layer 23 is deposited, and the isolation trench 11 is formed, the current spreading layer 24 and the Bragg reflection layer 25 are deposited again, and the Bragg reflection layer 25 is opened. hole, then deposit a current transport layer, and finally deposit an insulating protective layer 27 and a bonding metal layer, wherein the area of the current transport layer deposited on the Bragg reflection layer through hole is not larger than that of the Bragg reflection layer through hole.

Embodiment 4

Please refer to FIG. 4 , which is a schematic top view of the flip-chip light-emitting diode chip in the fourth embodiment of the present invention. The fourth embodiment of the present invention provides a flip-chip light-emitting diode chip. In this embodiment, the provided sapphire substrate A buffer layer 221, an N-type semiconductor layer 222, an active light-emitting layer 223, and a P-type semiconductor layer 224 are sequentially epitaxially grown on 21, and the MESA step 12 is formed, then the current blocking layer 23 is deposited, and the isolation trench 11 is formed, and then the current spread is deposited layer 24 and Bragg reflection layer 25, and opening holes on the Bragg reflection layer 25, then depositing a current transport layer, and finally depositing an insulating protective layer 27 and a bonding metal layer, wherein the current transport layer deposited on the Bragg reflection layer through holes The area of the layer is larger than the area of the through hole of the Bragg reflection layer, which reduces the contact resistance between the current transmission layer and the current spreading, and reduces the working voltage of the chip.

Embodiment 5

Please refer to FIGS. 5 and 6 , FIG. 5 is a schematic top view of a flip-chip LED chip in Embodiment 5 of the present invention, and FIG. 6 is a schematic structural diagram of a flip-chip LED chip in Embodiment 5 of the present invention. Fifth, a flip-chip light-emitting diode chip is provided. In this embodiment, a buffer layer 221 , an N-type semiconductor layer 222 , an active light-emitting layer 223 , and a P-type semiconductor layer 224 are epitaxially grown on the provided sapphire substrate 21 in sequence. Form MESA step 12, then deposit current blocking layer 23, and form isolation trench 11, then deposit current spreading layer 24 and Bragg reflection layer 25, and open holes on Bragg reflection layer 25, then deposit current transport layer, and finally deposit insulation protection layer 27 and bonding metal layer, wherein the current blocking layer 23 is discontinuous and is only provided under the through holes of the Bragg reflection layer 25, which not only plays the role of current blocking, but also reduces the distance between the through holes of the Bragg reflection layer 25. The light absorption of SiO ₂ can effectively improve the luminous brightness.

The performance test results of the flip-chip light-emitting diode chips prepared in each embodiment are shown in Table 1:

Table 1

It can be seen from the table that, compared with the existing products, the flip-chip light-emitting diode chips prepared by the present invention have improved luminous brightness to different degrees under the same test current.

The above-mentioned embodiments only represent several embodiments of the present invention, and the descriptions thereof are specific and detailed, but should not be construed as a limitation on the scope of the patent of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can also be made, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention should be subject to the appended claims.

Claims (10)

1. A flip-chip light emitting diode chip is characterized by comprising an N-type semiconductor layer, an active light emitting layer, a P-type semiconductor layer, a current blocking layer, a current expansion layer, a Bragg reflection layer and a current transmission layer which are sequentially stacked, wherein the Bragg reflection layer comprises a P-type Bragg reflection part and an N-type Bragg reflection part, the current transmission layer comprises a P-type current transmission part and an N-type current transmission part, a first through hole is formed in the P-type Bragg reflection part, a second through hole is formed in the N-type Bragg reflection part, the first through hole is used for electrically connecting the P-type current transmission part with the current expansion layer, and the second through hole is used for electrically connecting the N-type current transmission part with the N-type semiconductor layer.

2. The flip light emitting diode chip of claim 1, wherein the flip light emitting diode chip further comprises a substrate, a buffer layer, an insulating protection layer, and a bonding metal layer;

the buffer layer, the N-type semiconductor layer, the active light emitting layer, the P-type semiconductor layer, the current blocking layer, the current spreading layer, the Bragg reflection layer, the current transmission layer, the insulating protection layer and the bonding metal layer are sequentially stacked on the substrate.

3. The flip-chip light emitting diode chip of claim 1, wherein the current spreading layer is an indium tin oxide layer, and the thickness of the current spreading layer is

4. The flip chip light emitting diode chip of claim 1, wherein the bragg reflective layer is a periodic structure in which low refractive index layers and high refractive index layers are alternately stacked, wherein the low refractive index layers are SiO₂A layer of Ti as the high refractive index layer₃O₅And (3) a layer.

5. The flip chip led chip of claim 1, wherein the first and second vias have an area of 20um²～1000um²。

6. The flip chip light emitting diode chip of claim 1, wherein the first through holes and the second through holes are respectively provided in plural, and an interval between two adjacent first through holes is 10 μm to 200 μm, and an interval between two adjacent second through holes is 10 μm to 200 μm.

7. The flip-chip light emitting diode chip of claim 2, wherein the insulating protection layer includes a P-type insulating protection portion and an N-type insulating protection portion, the bonding metal layer includes a P-type bonding metal portion and an N-type bonding metal portion, a third through hole is formed in the P-type insulating protection portion, a fourth through hole is formed in the N-type insulating protection portion, the P-type bonding metal portion is electrically connected to the P-type current transmission portion through the third through hole, and the N-type bonding metal portion is electrically connected to the N-type current transmission portion through the fourth through hole.

8. The flip chip led chip of claim 6, wherein the flip chip led chip further defines an isolation trench, and an angle of the isolation trench is 30 ° to 80 °.

9. A method for manufacturing a flip-chip light-emitting diode chip, for manufacturing the flip-chip light-emitting diode chip of any one of claims 1 to 8, the method comprising:

providing a substrate required by growth;

sequentially epitaxially growing a buffer layer, an N-type semiconductor layer, an active light-emitting layer, a P-type semiconductor layer, a current blocking layer, a current expansion layer, a Bragg reflection layer, a current transmission layer, an insulating protection layer and a bonding metal layer on the substrate;

and after the Bragg reflection layer grows, etching a first through hole and a second through hole on the Bragg reflection layer.

10. The method for manufacturing the flip chip light emitting diode chip as claimed in claim 9, wherein the process for etching the first through hole and the second through hole is an inductively coupled plasma etching process.

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