CN106848027B - The preparation method of the vertical flip LED chips of high reliability - Google Patents
The preparation method of the vertical flip LED chips of high reliability Download PDFInfo
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- CN106848027B CN106848027B CN201510881813.0A CN201510881813A CN106848027B CN 106848027 B CN106848027 B CN 106848027B CN 201510881813 A CN201510881813 A CN 201510881813A CN 106848027 B CN106848027 B CN 106848027B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0025—Processes relating to coatings
Abstract
The present invention provides a kind of preparation method of the vertical flip LED chips of high reliability, the preparation method of the vertical flip LED chips of the high reliability passes through after forming the first deep hole, the second deep hole and aisle, extraordinary first insulating layer of film quality is formed in the bottom in the second deep hole and aisle and side wall, the luminescent layer multiple quantum wells exposed for coating etching, the exception for having evaded caused residual the graphical sapphire substrate marking and metal backwash in subsequent n-type GaN layer etching, is effectively promoted the reliability of flip LED chips in use.
Description
Technical field
The invention belongs to technical field of semiconductors, more particularly to a kind of preparation of the vertical flip LED chips of high reliability
Method.
Background technique
Light emitting diode (Light Emitting Diode, abbreviation LED) is a kind of semiconductor solid-state luminescent device, is utilized
Semiconductor P-N junction electroluminescent principle is made.LED component is low, small in size with cut-in voltage, response is fast, stability is good, the service life
The good photoelectric properties such as long, pollution-free, therefore have increasingly in fields such as outdoor room lighting, backlight, display, traffic instructions
It is widely applied.
Vertical flip-chip combines the structural advantage of both flip-chip and vertical chip, has both guaranteed in performance good
Current spread, shine the advantages of being evenly distributed a little, in turn ensuring axial intensity, good heat dissipation, be used in more demanding
Extraordinary application environment in (such as Projecting Lamp, mine lamp etc.).But at present in the preparation process of vertical flip-chip, usual situation
Under, the structure of flip-chip and vertical chip is combined in the structure design of vertical flip-chip, i.e. leading portion is flip-chip
Preparation process includes Mesa-ITO-REF-Barrier-PA (table top-tin indium oxide-reflecting layer-reflecting layer protective layer-insulating layer)
It include Bonding layers of metal evaporation-Bonding (bonding)-LLO (laser lift-off)-Deng the preparation process that, back segment is vertical chip
ICP (inductively coupled plasma body) and N-shaped GaN etching-PAD vapor deposition etc., but needed when back segment N-shaped GaN etching
Full etching falls epitaxial layer, until metal layer is etched into, it in this way can be there are two problem, one is that etching can replicate PSS (graphical indigo plant
Jewel substrate) the marking on metal, appearance is poor, the other is will continue to after having etched epitaxial layer etching metal, metal meeting
On backwash to the side wall of etching, if it is subsequent cleaning it is sordid can cause in test or client's use process leak electricity it is different
Often, the reliable sexual abnormalities such as failure are caused.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of vertical upside-down mountings of high reliability
The preparation method of LED chip, the marking for solving caused PSS in n-type GaN layer etching in the prior art can be copied to gold
On category so that when the poor problem of appearance and etching sheet metal metal can backwash to the side wall etched so that subsequent used
The problem of causing electric leakage exception in journey, causing the reliable sexual abnormalities such as failure.
In order to achieve the above objects and other related objects, the present invention provides a kind of vertical flip LED chips of high reliability
Preparation method, the preparation method comprises the following steps:
1) growth substrates are provided, in the growth substrates surface successively growing n-type GaN layer, luminescent layer multiple quantum wells and p-type
GaN layer；
2) first through the p-type GaN layer and the luminescent layer multiple quantum wells is formed in the structure that step 1) obtains
Deep hole, the second deep hole and aisle, the bottom of first deep hole, second deep hole and the aisle are respectively positioned on the N-shaped GaN
In layer；
3) the first insulating layer, the first insulating layer covering described second are formed in second deep hole and the aisle
The bottom and side wall in deep hole and the aisle；
4) Ohmic contact and current extending and reflecting layer are sequentially formed from the bottom to top on the p-type GaN layer surface；
5) p exposed between the surface in the reflecting layer and side wall, first deep hole and second deep hole
Type GaN layer surface and first surface of insulating layer form reflecting layer protective layer；
6) second insulating layer is formed in the body structure surface that step 5) obtains, and is corresponding to first deep hole region
The second insulating layer in form opening, the opening exposes the n-type GaN layer positioned at first deep hole bottom；
7) N mesoporous metal, the upper surface of the N mesoporous metal and the upper surface of the second insulating layer are filled in the opening
Flush；
8) bonded substrate is provided, is respectively formed first on the surface of the positive and described second insulating layer of the bonded substrate
Metal bonding layer and the second metal bonding layer, the bonded substrate pass through first metal bonding layer and second metallic bond
Close the surface that layer is bonded to the second insulating layer；Later and remove the growth substrates；
9) successively removal corresponds to the n-type GaN layer and described the of the aisle and second deep hole region
One insulating layer, to expose the reflecting layer protective layer；
10) P electrode is formed in the reflecting layer protective layer for corresponding to second deep hole region.
A kind of preferred embodiment of preparation method as the vertical flip LED chips of high reliability of the invention, the growth
Substrate is Sapphire Substrate, GaN substrate, silicon substrate or silicon carbide substrates.
A kind of preferred embodiment of preparation method as the vertical flip LED chips of high reliability of the invention, utilizes PECVD
Technique forms first insulating layer in second deep hole and the aisle, and the material of first insulating layer is titanium dioxide
Silicon, silicon nitride or silicon oxynitride；First insulating layer with a thickness of 3000 angstroms~30000 angstroms.
A kind of preferred embodiment of preparation method as the vertical flip LED chips of high reliability of the invention, utilizes magnetic control
Sputtering or reaction and plasma depositing operation expand in p-type GaN layer surface deposition ito thin film as the Ohmic contact and electric current
Open up layer, the ito thin film with a thickness of 50 angstroms~3000 angstroms, the area of the Ohmic contact and current extending is less than the p
The area of type GaN layer.
A kind of preferred embodiment of preparation method as the vertical flip LED chips of high reliability of the invention, utilizes magnetic control
Sputtering technology or MOCVD technique in p-type GaN layer surface deposition ZnO film as the Ohmic contact and current extending,
The ZnO film with a thickness of 50 angstroms~3000 angstroms, the area of the Ohmic contact and current extending is less than the p-type GaN
The area of layer.
A kind of preferred embodiment of preparation method as the vertical flip LED chips of high reliability of the invention, utilizes magnetic control
Sputtering technology forms the reflecting layer in the Ohmic contact and current expansion layer surface, and the material in the reflecting layer is Ag-TiW
Or Ag-TiW-Pt.
A kind of preferred embodiment of preparation method as the vertical flip LED chips of high reliability of the invention, using magnetic control
Sputtering technology or electron-beam vapor evaporation technology are deep on the surface in the reflecting layer and side wall, first deep hole and described second
The exposed p-type GaN layer surface and first surface of insulating layer form reflecting layer protective layer between hole, and the reflecting layer is protected
The material of sheath is the combination of one or more of Cr, Al, TiW, Pt, Ti, Au, Ni, the thickness of the reflecting layer protective layer
It is 20 angstroms~20000 angstroms.
A kind of preferred embodiment of preparation method as the vertical flip LED chips of high reliability of the invention, utilizes PECVD
Technique forms the second insulating layer in the body structure surface that the step 5) obtains, and the material of the second insulating layer is titanium dioxide
Silicon, silicon nitride or silicon oxynitride；First insulating layer with a thickness of 3000 angstroms~30000 angstroms.
A kind of preferred embodiment of preparation method as the vertical flip LED chips of high reliability of the invention, is opened described
The N mesoporous metal filled in mouthful is the combination of one or more of Cr, Al, Pt, Ti, Au, Ni, the thickness of the N mesoporous metal
Degree is 2000 angstroms~50000 angstroms.
A kind of preferred embodiment of preparation method as the vertical flip LED chips of high reliability of the invention, the bonding
The back side of substrate is formed with N electrode.
A kind of preferred embodiment of preparation method as the vertical flip LED chips of high reliability of the invention, utilizes inductance
The removal of coupled plasma etch technique corresponds to the n-type GaN layer of the aisle and second deep hole region；Benefit
Correspond to first insulating layer of the aisle and second deep hole region with the removal of BOE solution skill.
A kind of preferred embodiment of preparation method as the vertical flip LED chips of high reliability of the invention, removal correspond to
After the n-type GaN layer of the aisle and second deep hole region, removal corresponds to the aisle and described the
It further include the step that roughening treatment is carried out to the n-type GaN layer surface before first insulating layer of two deep hole regions
Suddenly.
A kind of preferred embodiment of preparation method as the vertical flip LED chips of high reliability of the invention, it is molten using KOH
The step of liquid or developer solution carry out roughening treatment to the n-type GaN layer surface.
As described above, the preparation method of the vertical flip LED chips of high reliability of the invention, has the advantages that
After forming the first deep hole, the second deep hole and aisle, it is non-that film quality is formed in the bottom in the second deep hole and aisle and side wall
The first often good insulating layer, the luminescent layer multiple quantum wells exposed for coating etching, has evaded and having etched in subsequent n-type GaN layer
When it is caused residual the graphical sapphire substrate marking and metal backwash exception, flip LED chips, which are effectively promoted, to be made
With reliability in the process.
Detailed description of the invention
Fig. 1 is shown as the flow chart of the preparation method of the vertical flip LED chips of high reliability of the present invention.
Fig. 2 is shown as the structure that S1 step is presented in the preparation method of the vertical flip LED chips of high reliability of the present invention and shows
It is intended to.
Fig. 3 to Fig. 4 is shown as the knot that S2 step is presented in the preparation method of the vertical flip LED chips of high reliability of the present invention
Structure schematic diagram, wherein Fig. 3 is top view, and Fig. 4 is cross section structure schematic diagram of the Fig. 3 along the direction AA '.
Fig. 5 is shown as the structure that S3 step is presented in the preparation method of the vertical flip LED chips of high reliability of the present invention and shows
It is intended to.
Fig. 6 to Fig. 7 is shown as the knot that S4 step is presented in the preparation method of the vertical flip LED chips of high reliability of the present invention
Structure schematic diagram.
Fig. 8 is shown as the structure that S5 step is presented in the preparation method of the vertical flip LED chips of high reliability of the present invention and shows
It is intended to.
Fig. 9 is shown as the structure that S6 step is presented in the preparation method of the vertical flip LED chips of high reliability of the present invention and shows
It is intended to.
Figure 10 is shown as the structure that S7 step is presented in the preparation method of the vertical flip LED chips of high reliability of the present invention and shows
It is intended to.
Figure 11 to Figure 13 is shown as what S8 step in the preparation method of the vertical flip LED chips of high reliability of the present invention was presented
Structural schematic diagram.
Figure 14 to Figure 16 is shown as what S9 step in the preparation method of the vertical flip LED chips of high reliability of the present invention was presented
Structural schematic diagram.
Figure 17 is shown as the structure that S10 step is presented in the preparation method of the vertical flip LED chips of high reliability of the present invention
Schematic diagram.
Component label instructions
100 growth substrates
101 n-type GaN layers
102 luminescent layer multiple quantum wells
103 p-type GaN layers
104 first deep holes
105 second deep holes
106 aisle
107 first insulating layers
108 Ohmic contacts and current extending
109 reflecting layer
110 reflecting layer protective layers
111 second insulating layers
112 openings
113 N mesoporous metals
114 bonded substrates
115 P electrodes
116 first metal bonding layers
117 second metal bonding layers
118 pyramidal structures
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Fig. 1 to Figure 17 is please referred to it should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, though only show in diagram with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout kenel may also be increasingly complex.
Referring to Fig. 1, the present invention provides a kind of preparation method of the vertical flip LED chips of high reliability, it is described highly reliable
The preparation methods of the vertical flip LED chips of property the following steps are included:
1) growth substrates are provided, in the growth substrates surface successively growing n-type GaN layer, luminescent layer multiple quantum wells and p-type
GaN layer；
2) first through the p-type GaN layer and the luminescent layer multiple quantum wells is formed in the structure that step 1) obtains
Deep hole, the second deep hole and aisle, the bottom of first deep hole, second deep hole and the aisle are respectively positioned on the N-shaped GaN
In layer；First deep hole is located at the inside for the structure that the step 1) obtains, and the aisle is located at what the step 1) obtained
The edge of structure, and the structure obtained along the step 1) circumferentially around one week, second deep hole is close to the step 1)
The edge of obtained structure, and it is located at the inside in the aisle；
3) the first insulating layer, the first insulating layer covering described second are formed in second deep hole and the aisle
The bottom and side wall in deep hole and the aisle；
4) Ohmic contact and current extending and reflecting layer are sequentially formed from the bottom to top on the p-type GaN layer surface；
5) p exposed between the surface in the reflecting layer and side wall, first deep hole and second deep hole
Type GaN layer surface and first surface of insulating layer form reflecting layer protective layer；
6) second insulating layer is formed in the body structure surface that step 5) obtains, and is corresponding to first deep hole region
The second insulating layer in form opening, the opening exposes the n-type GaN layer positioned at first deep hole bottom；
7) N mesoporous metal, the upper surface of the N mesoporous metal and the upper surface of the second insulating layer are filled in the opening
Flush；
8) bonded substrate is provided, is respectively formed first on the surface of the positive and described second insulating layer of the bonded substrate
Metal bonding layer and the second metal bonding layer, the bonded substrate pass through first metal bonding layer and second metallic bond
Close the surface that layer is bonded to the second insulating layer；The growth substrates are removed later；
9) successively removal corresponds to the n-type GaN layer and described the of the aisle and second deep hole region
One insulating layer, to expose the reflecting layer protective layer；
10) P electrode is formed in the reflecting layer protective layer for corresponding to second deep hole region.
In step 1), S1 step and Fig. 2 in Fig. 1 are please referred to, growth substrates 100 are provided, in the growth substrates 100
On successively growing n-type GaN layer 101, luminescent layer multiple quantum wells 102 and p-type GaN layer 103.
As an example, the growth substrates 100 can be but be not limited only to be suitble to GaN and its semiconductor epitaxial Material growth
Sapphire Substrate, GaN substrate, silicon substrate or silicon carbide substrates.
As an example, successively n-type GaN layer 101, the luminescent layer described in epitaxial growth are more in the growth substrates 100
Quantum Well 102 and the p-type GaN layer 103.
In step 2), the S2 step and Fig. 3 to Fig. 4 in Fig. 1 are please referred to, is formed and is run through in the structure that step 1) obtains
First deep hole 104 of the p-type GaN layer 103 and the luminescent layer multiple quantum wells 102, the second deep hole 105 and aisle 106, it is described
The bottom of first deep hole 104, second deep hole 105 and the aisle 106 is respectively positioned in the n-type GaN layer 101；Described
One deep hole 104 is located at the inside for the structure that the step 1) obtains, and the aisle 106 is located at the structure that the step 1) obtains
Edge, and the structure obtained along the step 1) circumferentially around one week, second deep hole 105 is obtained close to the step 1)
Structure edge, and be located at the aisle 106 inside.
As an example, referring to Fig. 3, Fig. 3 is the overlooking structure diagram for the structure that step 2) obtains, as shown in Figure 2, institute
State the first deep hole 104 be it is multiple, multiple first deep holes 104 are distributed evenly in the interior of the structure that the step 1) obtains
Portion；The quantity of second deep hole 105 can be two but not be limited according to this that second deep hole 105 is located at the step 1)
The edge two corners of obtained structure；The aisle 106 is located at the edge for the structure that the step 1) obtains, and surround along its periphery
One week.The cross-sectional shape of first deep hole 104 can be but be not limited only to circle, 105 cross section of the second deep hole
Shape can be but be not limited only to square, and the lateral dimension of first deep hole 104 is less than the transverse direction of second deep hole 105
Size, i.e., herein, the diameter of round first deep hole 104 are less than the side length of square second deep hole 105.
As an example, being formed in the structure that step 1) obtains through the p-type GaN layer 103 using photoetching, etching technics
And first deep hole 104, second deep hole 105 and the aisle 106 of the luminescent layer multiple quantum wells 102, specific side
Method are as follows: firstly, photoresist layer (not shown) is coated on the p-type GaN layer surface, using the graphical photoresist of photoetching process
Layer, to define the figure of first deep hole 104, second deep hole 105 and the aisle 106 in the photoresist layer
Shape；Secondly, using BCl according to the patterned photoresist layer3、Cl2And Ar plasma selectivity etches the p-type GaN layer
103, the luminescent layer multiple quantum wells 102 and the n-type GaN layer 101 are to form first deep hole 104, second deep hole
105 and the aisle 106；Finally, removing the photoresist layer.
In step 3), S3 step and Fig. 5 in Fig. 1 are please referred to, in second deep hole 105 and the aisle 106
The first insulating layer 107 is formed, first insulating layer 107 covers the bottom and side in second deep hole 105 and the aisle 106
Wall.
As an example, form the first insulating layer 107 in second deep hole 105 and the aisle 106, specific method
Are as follows: firstly, using pecvd process in the p-type GaN layer surface 103, first deep hole 104, second deep hole 105
And one layer of dielectric isolation layer is formed in the aisle；Secondly, it is dielectrically separated from layer surface coating photoresist layer (not shown) described,
Using the graphical photoresist layer of photoetching process, to define the figure of first insulating layer 107 in the photoresist layer
Shape；Then, it according to the patterned photoresist layer, etches away positioned at the p-type GaN layer surface 103 and first deep hole
The dielectric isolation layer in 104, to form first insulating layer 107, finally, removing the photoresist layer.
As an example, the material of first insulating layer 107 can be but be not limited only to silica, silicon nitride or nitrogen oxygen
SiClx；The thickness of first insulating layer can be but be not limited only to 3000 angstroms~30000 angstroms.
After forming first deep hole 104, second deep hole 105 and the aisle 106, in second deep hole
105 and the aisle 106 bottom and side wall formed extraordinary first insulating layer 107 of film quality, described first absolutely
The luminescent layer multiple quantum wells 102 that the cladding etching of edge layer 107 exposes, has evaded and having etched in the subsequent n-type GaN layer 101
When it is caused residual the graphical sapphire substrate marking and metal backwash exception, the flip LED chips are effectively promoted
Reliability in use.
It should be noted that in order to enable 107 pairs of first insulating layer etch expose be located at second deep trouth
105 and the luminescent layer Quantum Well 102 of 106 side wall of the aisle preferably protected, first insulating layer 107 in addition to
The bottom and side wall in second deep trouth 105 and the aisle 106 is completely covered, first insulating layer 107 also extends to
The p-type GaN layer surface on 106 periphery of second deep trouth 105 and the aisle.
In step 4), please refer to the S4 step and Fig. 6 to Fig. 7 in Fig. 1,103 surface of p-type GaN layer by down toward
On sequentially form Ohmic contact and current extending 108 and reflecting layer 109.
As an example, as shown in fig. 6, forming the Ohmic contact and current extending on 103 surface of p-type GaN layer
108 method particularly includes: firstly, using magnetron sputtering technique or reaction and plasma depositing operation in 103 table of p-type GaN layer
Face deposits ITO (tin indium oxide) film；Secondly, photoresist layer (not shown) is coated on the ito thin film surface, using photoetching work
The graphical photoresist layer of skill, to define the figure of the Ohmic contact and current extending 108 in the photoresist layer
Shape；Then, the ito thin film is etched to form the Ohmic contact and current extending according to the patterned photoresist layer
108, finally, removing the photoresist layer.
As an example, heavy on 108 surface of p-type GaN layer using magnetron sputtering technique or reaction and plasma depositing operation
The thickness of the long-pending ITO (tin indium oxide) film can be but be not limited only to 50 angstroms~3000 angstroms.
As an example, forming the specific side of the Ohmic contact and current extending 108 on 103 surface of p-type GaN layer
Method are as follows: firstly, depositing ZnO film on 103 surface of p-type GaN layer using magnetron sputtering technique or MOCVD technique；Secondly,
The ZnO film surface coats photoresist layer (not shown), using the graphical photoresist layer of photoetching process, in the light
The figure of the Ohmic contact and current extending 108 is defined in photoresist layer；Then, according to the patterned photoresist layer
The ZnO film is etched to form the Ohmic contact and current extending 108, finally, removing the photoresist layer.
As an example, heavy on 103 surface of p-type GaN layer using magnetron sputtering technique or reaction and plasma depositing operation
The thickness of the long-pending ZnO film can be but be not limited only to 50 angstroms~3000 angstroms.
As an example, the area of the Ohmic contact and current extending 108 is less than the area of the p-type GaN layer 103.
The Ohmic contact on 103 surface of the p-type GaN layer between first deep hole 104 and second deep hole 105 and
Current extending 108 is not desired to contact with first insulating layer 107, is separated by certain spacing therebetween.
As an example, referring to Fig. 7, using magnetron sputtering technique on 108 surface of the Ohmic contact and current extending
Form the reflecting layer, 109, the material in the reflecting layer 109 can be but be not limited only to for Ag-TiW (Ag and TiW) or Ag-
TiW-Pt (Ag, TiW and Pt), wherein the thickness of Ag can be but be not limited only to 750 angstroms~3000 angstroms, and the thickness of TiW can be
But 100 angstroms~1000 angstroms are not limited only to, the thickness of Pt can be but be not limited only to 100 angstroms~1000 angstroms.
As an example, the area in the reflecting layer 109 is slightly larger than the Ohmic contact and the area of current extending 108.
In step 5), S5 step and Fig. 8 in Fig. 1 are please referred to, in the surface in the reflecting layer 109 and side wall, described
Exposed 103 surface of the p-type GaN layer and first insulating layer 107 between first deep hole 104 and second deep hole 105
Surface forms reflecting layer protective layer 110.
As an example, using magnetron sputtering technique or electron-beam vapor evaporation technology on the surface in the reflecting layer 109 and
Exposed 103 surface of the p-type GaN layer and described first between side wall, first deep hole 104 and second deep hole 105
107 surface of insulating layer forms the reflecting layer protective layer 110, and the material of the reflecting layer protective layer 110 can be but not only limit
In the combination of one or more of Cr, Al, TiW, Pt, Ti, Au, Ni.
As an example, the thickness of the reflecting layer protective layer 110 can be but be not limited only to 20 angstroms~20000 angstroms, wherein
TiW with a thickness of 20 angstroms~5000 angstroms, Cr with a thickness of 20 angstroms~500 angstroms, Pt with a thickness of 200 angstroms~1000 angstroms, the thickness of Ti
Spending range is 200 angstroms~1000 angstroms, Au with a thickness of 2000 angstroms~5000 angstroms, Ni with a thickness of 200 angstroms~2000 angstroms.
As an example, being Ni layers positioned at top layer when the reflecting layer protective layer 110 is multilayered structure.
In step 6), S6 step and Fig. 9 in Fig. 1 are please referred to, forms second absolutely in the body structure surface that step 5) obtains
Edge layer 111, and opening 112, institute are formed in the second insulating layer 111 for corresponding to 104 region of the first deep hole
It states opening 112 and exposes the n-type GaN layer 101 positioned at 104 bottom of the first deep hole.
As an example, forming the second insulating layer in the body structure surface that the step 5) obtains using pecvd process
111, the material of the second insulating layer 111 can be but be not limited only to silica, silicon nitride or silicon oxynitride；Described first
The thickness of insulating layer 111 can be but be not limited only to 3000 angstroms~30000 angstroms.
As an example, described in being formed in the second insulating layer 111 for corresponding to 104 region of the first deep hole
Opening 112 method particularly includes: firstly, photoresist layer (not shown) is coated on 111 surface of second insulating layer, using photoetching
The graphical photoresist layer of technique, to define the figure of the opening 112 in the photoresist layer；Then, according to figure
The photoresist layer of shape etches the second insulating layer 111 to form the opening 112, finally, removing the photoresist
Layer.
In step 7), S7 step and Figure 10 in Fig. 1 are please referred to, fills N mesoporous metal 113, institute in the opening 112
State the upper surface of N mesoporous metal 113 and the upper surface flush of the second insulating layer 111.
As an example, in the opening 112 the N mesoporous metal 113 filled can be but be not limited only to Cr, Al, Pt,
The combination of one or more of Ti, Au, Ni, the N mesoporous metal 113 fill up the opening 112, the thickness of the N mesoporous metal 113
Degree can be but be not limited only to 2000 angstroms~50000 angstroms.
In step 8), the S8 step and Figure 11 to Figure 13 in Fig. 1 are please referred to, bonded substrate 114 is provided, in the bonding
The surface of the positive and described second insulating layer 111 of substrate 114 is respectively formed the first metal bonding layer 116 and the second metal bonding
Layer 117, the bonded substrate 114 are bonded to institute by first metal bonding layer 116 and second metal bonding layer 117
State the surface of second insulating layer 111；The growth substrates 100 are removed later.
As an example, the bonded substrate 114 is bonded to 111 surface of second insulating layer method particularly includes: first
First, the second metal bonding layer 117 is formed on the surface of the second insulating layer 111, as shown in figure 11；Secondly, in the bonding
The first metal bonding layer 116 of front and formation of substrate 114, passes through first metal bonding layer for the bonded substrate 114
116 and second metal bonding layer 117 be bonded to the surface of the second insulating layer 111, as shown in figure 12.After bonding, need
Ensure there cannot be cavity between the bonded substrate 114 and the surface of the second insulating layer 111.
As an example, the back side of the bonded substrate 114 is formed with N electrode (not shown).
As an example, forming first metal bonding layer in the front of the bonded substrate 114 using evaporation process
116, the material of first metal bonding layer 116 can be but be not limited only to AuSn；It is exhausted described second using evaporation process
111 surface of edge layer forms second metal bonding layer 117, and the material of second metal bonding layer 117 can be but not only
It is limited to the combination of one or more of Cr, Al, Ti, Pt, Au, Ni；The thickness of second metal bonding layer 117 can be but
It is not limited only to 5000 angstroms~50000 angstroms.
As an example, the bonded substrate 114 can be but be not limited only to silicon wafer.
As an example, the growth is served as a contrast using laser lift-off when the growth substrates 100 are Sapphire Substrate
It removes at bottom 100.
In step 9), the S9 step and Figure 14 to Figure 16 in Fig. 1 are please referred to, successively removal corresponds to the aisle 106
And the n-type GaN layer 101 and first insulating layer 107 of 105 region of the second deep hole, it is described anti-to expose
Penetrate layer protective layer 110.
As an example, corresponding to the aisle 106 and described second using the removal of inductively coupled plasma etching technique
The n-type GaN layer 101 of 105 region of deep hole, as shown in figure 14.
As an example, removal corresponds to the n-type GaN layer of the aisle 106 and 105 region of the second deep hole
After 101, further include the steps that carrying out roughening treatment to 101 surface of the n-type GaN layer of reservation.Preferably, the present embodiment
In, using the KOH solution for being heated to certain temperature or the developer solution for being heated to certain temperature to 101 surface of n-type GaN layer into
Row roughening treatment, to form pyramidal structure 118 on 101 surface of n-type GaN layer, as shown in figure 15.To the n-type GaN layer
101 surface carries out roughening treatment and is conducive to the ease of light so that 101 surface of the n-type GaN layer forms the pyramidal structure 118
Out, the outer quantum effect of the flip LED chips can be promoted.
As an example, corresponding to the aisle 106 and 105 region of the second deep hole using the removal of BOE solution skill
First insulating layer 107, as shown in figure 16.
In step 10), S10 step and Figure 17 in Fig. 1 are please referred to, is corresponding to 105 location of the second deep hole
110 surface of reflecting layer protective layer in domain forms P electrode 115.
As an example, being protected using evaporation process in the reflecting layer for corresponding to 105 region of the second deep hole
110 surface of layer form the P electrode 115；The material of the P electrode 115 can be but be not limited only to Cr, Al, Pt, Ti, Au, Ni
One or more of combination；The thickness of the P electrode 115 can be but be not limited only to 5000 angstroms~50000 angstroms.
By above processing step, pass through the P electrode 115 and the reflecting layer the reflecting layer protective layer 110- Europe 109-
Nurse contact and current extending 108-p type GaN layer 103, which are connected, is used as electric current injection end, is bonded by the bonded substrate 114-
Metal layer-N mesoporous metal 113 is used as current output terminal, constitutes current path, the vertical flip-chip as prepared.
Flip LED chips of the invention are output and input by porous electric current, and current distribution is excellent, and the distribution that shines is equal
It is even；By bonded substrate heat dissipation metal, unfailing performance is excellent；Light-emitting surface is the very thin epitaxial layer of thickness, axial intensity；Make
It obtains the flip LED chips and is suitable for the higher extraordinary application field of reliability.Forming the first deep hole, the second deep hole and aisle
Later, extraordinary first insulating layer of film quality is formed in the bottom in the second deep hole and aisle and side wall, for coating etching
The luminescent layer multiple quantum wells exposed has evaded the caused residual graphical sapphire substrate print in subsequent n-type GaN layer etching
The exception of note and metal backwash, is effectively promoted the reliability of flip LED chips in use.
In conclusion the present invention provides a kind of preparation method of the vertical flip LED chips of high reliability, the high reliability
The preparation methods of vertical flip LED chips is successively given birth on the growth substrates surface the following steps are included: 1) provide growth substrates
Long n-type GaN layer, luminescent layer multiple quantum wells and p-type GaN layer；2) it is formed in the structure that step 1) obtains through the p-type GaN
The first deep hole, the second deep hole and the aisle of layer and the luminescent layer multiple quantum wells, first deep hole, second deep hole and institute
The bottom for stating aisle is respectively positioned in the n-type GaN layer；First deep hole is located at the inside for the structure that the step 1) obtains,
The aisle is located at the edge for the structure that the step 1) obtains, and the structure obtained along the step 1) circumferentially around one
Week, the edge for the structure that second deep hole is obtained close to the step 1), and it is located at the inside in the aisle；3) described
The first insulating layer is formed in two deep holes and the aisle, first insulating layer covers the bottom in second deep hole and the aisle
Portion and side wall；4) Ohmic contact and current extending and reflecting layer are sequentially formed from the bottom to top on the p-type GaN layer surface；5)
The exposed p-type GaN layer surface between the surface in the reflecting layer and side wall, first deep hole and second deep hole
And first surface of insulating layer forms reflecting layer protective layer；6) second insulating layer is formed in the body structure surface that step 5) obtains,
And opening is formed in the second insulating layer for corresponding to first deep hole region, the opening is exposed positioned at institute
State the n-type GaN layer of the first deep hole bottom；7) in the opening fill N mesoporous metal, the upper surface of the N mesoporous metal with
The upper surface flush of the second insulating layer；8) bonded substrate is provided, positive and described second in the bonded substrate is exhausted
The surface of edge layer is respectively formed the first metal bonding layer and the second metal bonding layer, and the bonded substrate passes through first metal
Bonded layer and second metal bonding layer are bonded to the surface of the second insulating layer；The growth substrates are removed later；9)
Successively removal corresponds to the n-type GaN layer and first insulating layer of the aisle and second deep hole region, with
Expose the reflecting layer protective layer；10) in the reflecting layer protective layer for corresponding to second deep hole region
Form P electrode.After forming the first deep hole, the second deep hole and aisle, formed in the bottom in the second deep hole and aisle and side wall
Extraordinary first insulating layer of film quality, the luminescent layer multiple quantum wells exposed for coating etching, has evaded in subsequent N-shaped
The exception of GaN layer caused residual graphical sapphire substrate marking and metal backwash when etching, is effectively promoted flip LED
The reliability of chip in use.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (13)
1. a kind of preparation method of the vertical flip LED chips of high reliability, which is characterized in that the preparation method includes:
1) growth substrates are provided, in the growth substrates surface successively growing n-type GaN layer, luminescent layer multiple quantum wells and p-type GaN
Layer；
2) formed in the structure obtained in step 1) through the first deep hole of the p-type GaN layer and the luminescent layer multiple quantum wells,
The bottom in the second deep hole and aisle, first deep hole, second deep hole and the aisle is respectively positioned in the n-type GaN layer；
3) the first insulating layer is formed in second deep hole and the aisle, first insulating layer covers second deep hole
And bottom and the side wall in the aisle, first insulating layer with a thickness of 3000 angstroms~30000 angstroms；
4) Ohmic contact and current extending and reflecting layer are sequentially formed from the bottom to top on the p-type GaN layer surface；
5) the p-type GaN exposed between the surface in the reflecting layer and side wall, first deep hole and second deep hole
Layer surface and first surface of insulating layer form reflecting layer protective layer；
6) second insulating layer is formed in the body structure surface that step 5) obtains, and in the institute for corresponding to first deep hole region
It states and forms opening in second insulating layer, the opening exposes the n-type GaN layer positioned at first deep hole bottom；
7) N mesoporous metal is filled in the opening, and the upper surface of the N mesoporous metal is equal with the upper surface of the second insulating layer
Together；
8) bonded substrate is provided, is respectively formed the first metal on the surface of the positive and described second insulating layer of the bonded substrate
Bonded layer and the second metal bonding layer, the bonded substrate pass through first metal bonding layer and second metal bonding layer
It is bonded to the surface of the second insulating layer；The growth substrates are removed later；
9) successively removal corresponds to the n-type GaN layer and described first in the aisle and second deep hole region absolutely
Edge layer, to expose the reflecting layer protective layer；
10) P electrode is formed in the reflecting layer protective layer for corresponding to second deep hole region.
2. the preparation method of the vertical flip LED chips of high reliability according to claim 1, it is characterised in that: the life
Long substrate is Sapphire Substrate, GaN substrate, silicon substrate or silicon carbide substrates.
3. the preparation method of the vertical flip LED chips of high reliability according to claim 1, it is characterised in that: utilize
Pecvd process forms first insulating layer in second deep hole and the aisle, and the material of first insulating layer is
Silica, silicon nitride or silicon oxynitride.
4. the preparation method of the vertical flip LED chips of high reliability according to claim 1, it is characterised in that: utilize magnetic
Sputtering or reaction and plasma depositing operation are controlled in p-type GaN layer surface deposition ito thin film as the Ohmic contact and electric current
Extension layer, the ito thin film with a thickness of 50 angstroms~3000 angstroms, the area of the Ohmic contact and current extending is less than described
The area of p-type GaN layer.
5. the preparation method of the vertical flip LED chips of high reliability according to claim 1, it is characterised in that: utilize magnetic
Sputtering or MOCVD technique are controlled in p-type GaN layer surface deposition ZnO film as the Ohmic contact and current extending, institute
State ZnO film with a thickness of 50 angstroms~3000 angstroms, the area of the Ohmic contact and current extending is less than the p-type GaN layer
Area.
6. the preparation method of the vertical flip LED chips of high reliability according to claim 1, it is characterised in that: utilize magnetic
Control sputters at the Ohmic contact and current expansion layer surface forms the reflecting layer, the material in the reflecting layer be Ag-TiW or
Ag-TiW-Pt。
7. the preparation method of the vertical flip LED chips of high reliability according to claim 1, it is characterised in that: use magnetic
Sputtering technology or electron-beam vapor evaporation technology are controlled in the surface in the reflecting layer and side wall, first deep hole and described second
The exposed p-type GaN layer surface and first surface of insulating layer form reflecting layer protective layer between deep hole, and the reflection is protected
The material of sheath is the combination of one or more of Cr, Al, TiW, Pt, Ti, Au, Ni, the thickness of the reflecting layer protective layer
It is 20 angstroms~20000 angstroms.
8. the preparation method of the vertical flip LED chips of high reliability according to claim 1, it is characterised in that: utilize
Pecvd process forms the second insulating layer in the body structure surface that the step 5) obtains, and the material of the second insulating layer is
Silica, silicon nitride or silicon oxynitride；The second insulating layer with a thickness of 3000 angstroms~30000 angstroms.
9. the preparation method of the vertical flip LED chips of high reliability according to claim 1, it is characterised in that: described
The N mesoporous metal filled in opening is the combination of one or more of Cr, Al, Pt, Ti, Au, Ni, the N mesoporous metal
With a thickness of 2000 angstroms~50000 angstroms.
10. the preparation method of the vertical flip LED chips of high reliability according to claim 1, it is characterised in that: the key
The back side for closing substrate is formed with N electrode.
11. the preparation method of the vertical flip LED chips of high reliability according to claim 1, it is characterised in that: utilize electricity
Feel the n type GaN that the removal of coupled plasma etch technique corresponds to the aisle and second deep hole region
Layer；Correspond to first insulating layer of the aisle and second deep hole region using the removal of BOE solution.
12. the preparation method of the vertical flip LED chips of high reliability according to claim 1, it is characterised in that: removal pair
After the n-type GaN layer of aisle described in Ying Yu and second deep hole region, removal corresponds to the aisle and described
It further include the step that roughening treatment is carried out to the n-type GaN layer surface before first insulating layer of second deep hole region
Suddenly.
13. the preparation method of the vertical flip LED chips of high reliability according to claim 12, it is characterised in that: utilize
The step of KOH solution or developer solution carry out roughening treatment to the n-type GaN layer surface.
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| CN111725372B (en) * | 2020-06-16 | 2022-02-18 | 南京亮芯信息科技有限公司 | Submicron vertical deep ultraviolet LED based on surface plasmon enhancement and preparation method thereof |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102315352A (en) * | 2010-07-08 | 2012-01-11 | 三星Led株式会社 | Light emitting semiconductor device and manufacturing approach thereof |
| CN102412355A (en) * | 2010-09-17 | 2012-04-11 | Lg伊诺特有限公司 | Light emitting device |
| CN103098235A (en) * | 2010-09-10 | 2013-05-08 | 欧司朗光电半导体有限公司 | Light-emitting diode chip and method for producing the same |
| CN103765616A (en) * | 2011-08-31 | 2014-04-30 | 奥斯兰姆奥普托半导体有限责任公司 | Light-emitting diode chip |
| CN104051582A (en) * | 2013-03-14 | 2014-09-17 | 株式会社东芝 | Semiconductor Light Emitting Element, Light Emitting Device, And Method For Manufacturing Semiconductor Light Emitting Element |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100573940C (en) * | 2005-09-06 | 2009-12-23 | 昭和电工株式会社 | Gallium-nitride-based compound semiconductor light emitting element and manufacture method thereof |
| JP5983125B2 (en) * | 2012-07-18 | 2016-08-31 | 日亜化学工業株式会社 | Manufacturing method of semiconductor light emitting device |
| CN103579447B (en) * | 2012-08-03 | 2016-12-21 | 同方光电科技有限公司 | A kind of inverted structure light emitting diode and preparation method thereof |
-
2015
- 2015-12-03 CN CN201510881813.0A patent/CN106848027B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102315352A (en) * | 2010-07-08 | 2012-01-11 | 三星Led株式会社 | Light emitting semiconductor device and manufacturing approach thereof |
| CN103098235A (en) * | 2010-09-10 | 2013-05-08 | 欧司朗光电半导体有限公司 | Light-emitting diode chip and method for producing the same |
| CN102412355A (en) * | 2010-09-17 | 2012-04-11 | Lg伊诺特有限公司 | Light emitting device |
| CN103765616A (en) * | 2011-08-31 | 2014-04-30 | 奥斯兰姆奥普托半导体有限责任公司 | Light-emitting diode chip |
| CN104051582A (en) * | 2013-03-14 | 2014-09-17 | 株式会社东芝 | Semiconductor Light Emitting Element, Light Emitting Device, And Method For Manufacturing Semiconductor Light Emitting Element |
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