CN103682021B - Metal electrode has light emitting diode and the manufacture method thereof of array type micro structure - Google Patents

Metal electrode has light emitting diode and the manufacture method thereof of array type micro structure Download PDF

Info

Publication number
CN103682021B
CN103682021B CN201210349636.8A CN201210349636A CN103682021B CN 103682021 B CN103682021 B CN 103682021B CN 201210349636 A CN201210349636 A CN 201210349636A CN 103682021 B CN103682021 B CN 103682021B
Authority
CN
China
Prior art keywords
light emitting
emitting diode
layer
metal electrode
micropore
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201210349636.8A
Other languages
Chinese (zh)
Other versions
CN103682021A (en
Inventor
周圣军
王书方
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guangdong Ltd By Share Ltd Group
Original Assignee
GUANGDONG QUANTUM WAFER PHOTOELECTRIC TECHNOLOGY Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GUANGDONG QUANTUM WAFER PHOTOELECTRIC TECHNOLOGY Co Ltd filed Critical GUANGDONG QUANTUM WAFER PHOTOELECTRIC TECHNOLOGY Co Ltd
Priority to CN201210349636.8A priority Critical patent/CN103682021B/en
Publication of CN103682021A publication Critical patent/CN103682021A/en
Application granted granted Critical
Publication of CN103682021B publication Critical patent/CN103682021B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds

Abstract

This application provides a kind of metal electrode and there is the light emitting diode of array type micro structure, the multiple structure on epitaxial wafer substrate including epitaxial wafer substrate and preparation, described multiple structure is followed successively by cushion, the first type semiconductor layer, MQW active layer, electronic barrier layer, Second-Type semiconductor layer and transparent current extending from the bottom to top, first type metal electrode and Second-Type metal electrode are prepared on transparent current extending, and are separated by insulating barrier between the first type metal electrode and transparent current extending and Second-Type semiconductor layer.Present invention also provides corresponding LED production method.The present invention can be obviously improved the situation that light-emitting diode chip for backlight unit active region area in the fabrication process significantly reduces, and can effectively improve the luminous power of light emitting diode.

Description

Metal electrode has light emitting diode and the manufacture method thereof of array type micro structure
Technical field
The present invention relates to LED technology field, specifically, the present invention relates to a kind of luminescence two with array type micro structure Pole pipe and preparation method thereof.
Background technology
Electro-optical efficiency is high, energy-conservation, ring owing to having for light emitting diode (Light Emitting Diodes, LEDs) The advantage such as guarantor, life-span length, volume are little so that LED-based semiconductor lighting is considered as to most likely enter 21st century One of a kind of novel solid cold light source in general lighting field and high-technology field most with prospects.
Semiconductor lighting is wide variety of it is crucial that to improve its electro-optical efficiency.Wherein, nitride LED chip is improved Internal quantum efficiency and light extraction efficiency be one of the effective way of overall electro-optical efficiency improving LED.The interior amount of LED chip Sub-efficiency depends primarily on quality and the epitaxial structure of epitaxial material, and light extraction efficiency is the most relevant with chip structure.Therefore, need To go in terms of material, epitaxial structure, chip surface, side and back side form etc. improve LED chip internal quantum efficiency with Light extraction efficiency.
For the most epitaxially grown horizontal structure power type light-emitting diode chip, its p-n electrode position In the same side, owing to the flowing of electric current can observe the path of minimal path, therefore under big current operating conditions, it is easily caused electricity Stream blocking.The long-pending effect of heat can be formed further, reduce the internal quantum efficiency of power type light-emitting diode chip, cause active area to be sent out Light is uneven.It is thus desirable to the electrode pattern of power type light-emitting diode chip is optimized design, injection current is made to send out Luminous diode chip active area is uniformly distributed, it is to avoid current blockage phenomenon.
In horizontal structure power type light-emitting diode chip manufacturing proces, the formation of the first type Ohm contact electrode needs By micro fabrication, emitting diode epitaxial layer is performed etching, expose the GaN layer of the first type doping.
Fig. 1 shows the structure of a kind of typical GaN base power type light-emitting diode in prior art, lower section in Fig. 1 Being the top view on GaN base power type light-emitting diode surface, top is GaN base power type light-emitting diode cuing open along A-A face Face schematic diagram, the structure of this GaN base power type light-emitting diode is followed successively by epitaxial layer substrate 100, low temperature buffer layer from the bottom to top 101, the first type semiconductor layer 102, MQW active layer 103, electronic barrier layer 104, Second-Type semiconductor layer 105, transparent Current extending 106.
Second-Type Ohm contact electrode is produced on transparent current extending 106, specifically, according to the electricity being pre-designed Electrode structure makes transparent current extending 106 on current barrier layer 107, makes on transparent current extending 106 the most again Make Second-Type plain conductor 108, thus form Second-Type Ohm contact electrode.And for the first type Ohm contact electrode, at it In manufacturing process, then need by micro fabrication, emitting diode epitaxial layer to be performed etching, expose the first type quasiconductor The subregion of layer 102, then makes in the region that the first type semiconductor layer 102 exposes according to the electrode structure being pre-designed First type plain conductor 109, thus form the first type Ohm contact electrode.
It can easily be seen that in prior art when making the first type Ohm contact electrode, owing to needs pass through micro fabrication Etching exposes the subregion of the first type semiconductor layer 102, the most inevitably causes light-emitting diode chip for backlight unit to have The significantly reduction of source region area, causes the utilization rate of light-emitting diode chip for backlight unit active region area to decline, and then causes power-type to be sent out The decline of the luminous power of luminous diode chip.
In sum, currently in the urgent need to a kind of it can be avoided that light-emitting diode chip for backlight unit active region area significantly reduces and energy Enough improve light emitting diode and the manufacture method thereof of luminous power.
Summary of the invention
For overcoming existing defect, the present invention proposes one it can be avoided that light-emitting diode chip for backlight unit active region area significantly subtracts Little and light emitting diode and the manufacture method thereof of luminous power can be improved.
According to an aspect of the present invention, it is proposed that a kind of metal electrode has the light emitting diode of array type micro structure, The multiple structure on epitaxial wafer substrate including epitaxial wafer substrate and preparation, described multiple structure is followed successively by buffering from the bottom to top Layer, the first type semiconductor layer, MQW active layer, electronic barrier layer, Second-Type semiconductor layer and transparent current extending, the One type metal electrode and Second-Type metal electrode are prepared on transparent current extending, and the first type metal electrode and transparent electrical Separated by insulating barrier between stream extension layer and Second-Type semiconductor layer, with transparent electric current immediately below the pad of Second-Type metal electrode Separated by current barrier layer between extension layer, the described first type metal electrode micropore and described first by multiple filler metal Type semiconductor layer realize electrical connection, metal in described micropore and micropore through each layer of light emitting diode there is sidewall Insulating barrier, the superiors' deposition of described light emitting diode has passivation protection layer.
Wherein, described micropore has certain gradient, forms inverted trapezoidal structure.
Wherein, the inclination angle of the gradient of described micropore is 30 ° ~ 70 °.
Wherein, there is at described micropore electric connection micro structure, be electrically connected with the overall dimensions of micro structure at 20um ~ 50um Between.
Wherein, described electric connection micro structure is distributed on the wire of described first type electrode with a determining deviation.
Wherein, the ratio of the overall dimensions of the spacing of described electric connection micro structure and described electric connection micro structure 1 ~ Between 4.
Wherein, the hole size of the side wall insulating layer in described micropore is at least below described pore size 5um.
Wherein, described micropore is circular or regular polygon, or carries wavy circle or regular polygon, or with The circle of sawtooth or regular polygon.
Wherein, described transparent current extending can use tin indium oxide (Indium Tin Oxides writes a Chinese character in simplified form ITO), RuOx、IrOx, the material such as ZnO of Ga/Al etc. the 3rd major element doping makes.
Wherein, the thickness of described transparent current extending isWherein λ is lambda1-wavelength, and n is described transparent electrical The refractive index of stream extension layer material, m is integer.
Wherein, described current blocking layer material is SiO2、SiNxThin film, or A2O3Thin film.
Wherein, described passivation protection layer material is SiO2、SiNxThin film, or A2O3Thin film.
Wherein, the dielectric material of described side wall insulating layer is SiO2、Si3N4、TiO2、Al2O3, spin-coating glass, polyimides Or benzocyclobutene.
Wherein, described lumination of light emitting diode layer surface coarsening.
According to another aspect of the invention, it is proposed that a kind of metal electrode has the light emitting diode of array type micro structure Preparation method, comprises the following steps:
1) on epitaxial wafer substrate, it is sequentially prepared cushion, the first type semiconductor layer, MQW active layer, electronic blocking Layer, Second-Type semiconductor layer；
2) multiple micropore is gone out to expose the first type semiconductor layer in epitaxial wafer surface etch；
3) in epitaxial wafer surface deposition of insulative material, in making the plurality of micropore, attachment insulant forms lateral wall insulation Layer；And prepare current barrier layer in Second-Type wire position directly below；
4) transparent current extending is prepared；
5) make the first type metal electrode and Second-Type metal electrode, and in the plurality of micropore, be full of metal, make institute State the first type metal electrode to realize electrically connecting with described first type semiconductor layer by the metal in the plurality of micropore；
6) make passivation protection layer, and make metal pad exposed outside in case being electrically connected with.Wherein, described step 2) in, The inclination angle using 30 ° ~ 70 ° etches micropore, and making micropore is inverted trapezoidal structure.
Wherein, in described step 3), lift-off or wet corrosion technique can be used to prepare described side wall insulating layer.
Wherein, in described step 6), use plasma reinforced chemical vapour deposition method (PECVD), sputtering method (sputter), atomic layer deposition method (ALD) deposition of insulative material.
Compared with prior art, the present invention has a following technique effect:
1, the present invention can effectively improve the problem that light-emitting diode chip for backlight unit active region area significantly reduces.
2, the present invention can improve the luminous power of light emitting diode.
3, present invention process condition is simple, cost of manufacture is low, processing procedure is easily controlled.
Accompanying drawing explanation
Fig. 1 shows the structure of a kind of typical GaN base power type light-emitting diode in prior art, and wherein lower section is The top view on GaN base power type light-emitting diode surface, top is the GaN base power type light-emitting diode section along A-A face Schematic diagram；
Fig. 2 (a) shows the structure of the GaN base power type light-emitting diode in one embodiment of the invention, wherein lower section Be the top view of LED surface；Top is this light emitting diode generalized section along A-A face；Its first wire Being electrically connected with for noncontinuity, its micro structure is circular；
Fig. 2 (b) is the micro structure local of the first type electrode cable of the GaN base power type light-emitting diode shown in Fig. 2 (a) Enlarged drawing；
Fig. 3 (a) is the top view on the surface of the GaN base power type light-emitting diode in another embodiment of the present invention；
Fig. 3 (b) is the micro structure partial enlargement of the first type wire of the GaN base power type light-emitting diode shown in Fig. 3 (a) Figure；
Fig. 4 (a) is the top view on the surface of the GaN base power type light-emitting diode in another embodiment of the present invention；
Fig. 4 (b) is the micro structure partial enlargement of the first type wire of the GaN base power type light-emitting diode shown in Fig. 4 (a) Figure；
Fig. 5 is the profile of the electric connection micro structure in one embodiment of the invention；In figure, A represents that Second-Type metal saves Point, B represents side wall insulating layer；C represents transparent current extending；D is each layer of epitaxial wafer that micropore is passed；
Fig. 6 (a) is that the schematic diagram of the adoptable another kind of electrode pattern of the present invention (is electrically connected with micro-knot not shown in figure Structure)；
Fig. 6 (b) is that the schematic diagram of the present invention another electrode pattern adoptable (is electrically connected with micro-knot not shown in figure Structure).
Detailed description of the invention
Describe the present invention with specific embodiment below in conjunction with the accompanying drawings.
Embodiment one
According to one embodiment of present invention, it is provided that a kind of metal electrode has the light-emitting diodes of array type micro structure Pipe, the method comprises the following steps:
(1) method initially with metallochemistry vapour deposition (MOCVD) be sequentially depositing on a sapphire substrate cushion, First type semiconductor layer n-GaN, SQW, InGaN electronic barrier layer, Second-Type semiconductor layer p-GaN epitaxial layer, formed complete LED P N junction structure；
(2) use alloying furnace to make annealing treatment growing complete epitaxial wafer, excite the Mg doping acceptor of p-GaN；
(3) method using chemical reagent to clean carries out step etching after processing epitaxial wafer surface, exposes the first type half Conductor layer n-GaN, this operation is MESA etching technics；It is different from prior art, this step not whole to epitaxial wafer surface Panel region performs etching, but goes out a series of micropore in epitaxial wafer surface etch, exposes first from the micropore etched Type semiconductor layer n-GaN, these micropores composition microwell array, for leading in the first type semiconductor layer n-GaN and the first type metal Form noncontinuity between line to be electrically connected with；When MESA etches, the micropore etched has certain gradient, forms ladder Shape structure, 30 °-70 ° of its inclination angle, so it is beneficial to insulating barrier attachment and increases sidewall lighting area, thus shape in micropore Become side wall insulating layer；
(4) method using plasma reinforced chemical vapour deposition (PECVD) deposits one layer of SiO at crystal column surface2, pass through The design of reticle so that this insulating barrier part hinders as the electric current between Second-Type plain conductor and Second-Type semiconductor layer Barrier (insulating barrier), another part forms the side wall insulating layer in micropore, is used for the first type plain conductor in micropore with micro- The each layer of epitaxial wafer that hole is passed separates；
(5) using thin film evaporation equipment to be deposited with one layer of transparent conductive film on epitaxial wafer surface, its thickness is according to incidence Optical wavelength and ITO refractive index and change, can be determined by equation below:
t = mλ 2 n
In formula, λ is lambda1-wavelength, and n is the refractive index of ito thin film, and m is integer, and t is the thickness of ito thin film.
(6) ito thin film photoetching, prepares, the current extending of size little 5um consistent with MESA shape；
(7) at 450 DEG C of high temperature and N2Under atmosphere annealing ITO, annealing time is 30 minutes.
(8) prepared by metal electrode, utilizes negative photoresist to prepare metal electrode pattern at crystal column surface, and steams at electron beam Electrode evaporation is completed on the equipment of sending out；Wherein, when being deposited with the first type electrode, except desirable pattern is produced on surface on the insulating layer Outward, also need to fill full metal in micropore so that the first type semiconductor layer n-GaN by the metal in micropore be produced on insulation The metal electrode of layer upper surface realizes being electrically connected with；
(9) at 400 DEG C of high temperature and N2Under atmosphere, metal electrode being carried out alloying, annealing time is 30 minutes；
(10) use PECVD device deposition passivation protection layer and remove metal pad (PAD) table by photoetching, etching process The passivation layer in face.
Fig. 2 shows the light emitting diode using the metal electrode prepared by said method to have array type micro structure.As Shown in Fig. 2, this light emitting diode includes the most successively: epitaxial layer substrate 100, low temperature buffer layer the 101, first type quasiconductor Layer 102, MQW active layer 103, electronic barrier layer 104, Second-Type semiconductor layer 105, transparent current extending 106 and electricity Flow barrier 107.Having Second-Type plain conductor 108 on the most transparent current extending 106, Second-Type metal pad is with saturating Separating with current barrier layer 107 between bright current extending 106, insulating barrier 110 is prepared on transparent current extending 106, the One type plain conductor 109 is produced on insulating barrier 110, between such first type plain conductor 109 and transparent current extending 106 Separated by insulating barrier 110.Top view such as Fig. 2 of first type plain conductor 109 and the constituted figure of Second-Type plain conductor 108 Shown in (a).First type semiconductor layer 102 (be can be described as metal by the metal in a series of micropores and is electrically connected with node, hereinafter Do not repeating) realize being electrically connected with the first type plain conductor 109 being positioned at epitaxial wafer surface.It addition, the luminescence of the present embodiment Diode also have the first type metal pad corresponding with the first type plain conductor 109, Second-Type plain conductor 108, second Type metal pad, the superiors of light emitting diode have also deposited passivation protection layer, and these are the most not shown in FIG. 2.The present embodiment In, realize noncontinuity by the micro structure in micropore between the first type semiconductor layer n-GaN and the first type plain conductor electrical Connecting, shown in this micro structure such as Fig. 2 (b), the shape of this micro structure is circular.Wherein c1 is: straight at the minimum of insulating barrier aperture Footpath (refers to Fig. 5 understand), and c2 is: the electric connection node diameter of plain conductor, and c3 is: the opening diameter of MESA etching, c4 For: transparent current extending opening diameter, c5 is: diameter of a circle outside insulating barrier.The size of the micro structure of the present embodiment and Away from selecting the most flexibly.The overall dimensions of micro structure between 20um-50um, the spacing of micro structure and micro structure chi Very little ratio is between 1-4.It addition, at the minimum of insulating barrier aperture size both can be more than having might be less that metal was electrically connected with Node size.Insulating barrier endoporus is generally less than more than MESA etching size 5um.
Embodiment two
According to one embodiment of present invention, it is provided that another kind of metal electrode has the light-emitting diodes of array type micro structure Pipe, the method comprises the following steps:
(1) method initially with metallochemistry vapour deposition (MOCVD) be sequentially depositing on a sapphire substrate cushion, N-GaN, SQW, p-InGaN electronic barrier layer, p-GaN epitaxial layer, form complete LED P N junction structure；
(2) use alloying furnace to make annealing treatment growing complete epitaxial wafer, excite the Mg doping acceptor of p-GaN；
(3) method using chemical reagent to clean carries out step etching after processing epitaxial wafer surface, exposes n-GaN；No Being same as prior art, the entire area on epitaxial wafer surface is not performed etching by this step, but goes out in epitaxial wafer surface etch A series of micropore, exposes the first type semiconductor layer n-GaN from the micropore etched, these micropores composition microwell array, It is electrically connected with for forming noncontinuity between the first type semiconductor layer n-GaN and the first type plain conductor；Etch at MESA Time, the micropore etched has certain gradient, forms inverted trapezoidal structure, 30 °-70 ° of its inclination angle, the most beneficially insulating barrier Attachment, thus in micropore, form side wall insulating layer；
(4) (in finished product, this current barrier layer is positioned at Second-Type metal to use lift-off technique to prepare current barrier layer Immediately below pad, for Second-Type metal pad and transparent current extending are separated) and by the first type plain conductor micro structure The side wall insulating layer that layer each with the epitaxial wafer that micropore is passed separates；Its step is as follows:
First, positive photoresist is used to prepare required insulating layer pattern at crystal column surface；
Secondly, insulate at crystal column surface spin coating spin-coating glass (SOG) with photoetching agent pattern by the method for spin coating The film forming of layer；
Again, the hot plate of 120 ° of C toasts wafer 10min, makes spin-coating glass insulating barrier primary solidification；Then, by crystalline substance Circle is immersed in positive photoresist cleaning solution, sonic oscillation 20min, removes the photoresist below spin-coating glass；
Finally, the wafer cleaned up is solidified 30min in 500 ° of C high temperature furnace pipes；
(5) using thin film evaporation equipment to be deposited with one layer of transparent conductive film on epitaxial wafer surface, its thickness is according to incidence Optical wavelength and ITO refractive index and change, can be determined by equation below:
t = mλ 2 n
In formula, λ is lambda1-wavelength, and n is the refractive index of ito thin film, and m is integer, and t is the thickness of ito thin film.
(6) ito thin film photoetching, prepares, the current extending of size little 5-10um consistent with MESA shape；
(7) at 450 DEG C of high temperature and N2Under atmosphere annealing ITO, annealing time is 30 minutes.
(8) prepared by metal electrode, utilizes negative photoresist to prepare metal electrode pattern at crystal column surface, and steams at electron beam Electrode evaporation is completed on the equipment of sending out；
(9) at 400 DEG C of high temperature and N2Under atmosphere, metal electrode being carried out alloying, annealing time is 30 minutes；
(10) use PECVD device deposit passivation layer and removed the passivation layer on PAD surface by photoetching, etching process.
The overall structure of the light emitting diode of the present embodiment is consistent with embodiment one, repeats no more.The difference of the present embodiment Part is between the first type semiconductor layer n-GaN and the first type plain conductor to realize in the micropore that noncontinuity is electrically connected with The shape that micro structure is used.As shown in Figure 3 (b), the shape of the micro structure of the present embodiment is the circle of band wave concaveconvex structure, The circle of this band wave concaveconvex structure has the effect increasing sidewall lighting area further.Wherein c1 ' is: insulating barrier aperture Diameter (referring to Fig. 5 understand) at little, r0 is: the radius of waveform semicircle, r1 on the electric connection node of plain conductor For: the radius of waveform semicircle on MESA aperture, r2 is: the radius of waveform semicircle on transparent current extending aperture, and r3 is: The radius of waveform semicircle on insulating barrier outer ledge, a1 is: plain conductor be electrically connected with between node and MESA aperture away from From, a2 is: the distance between transparent current extending aperture and MESA aperture, and a3 is: transparent current extending aperture and insulating barrier Distance between outer ledge.The size of the micro structure of the present embodiment and spacing can select the most flexibly.Micro structure whole Body size is between 20um-50um, and the spacing of micro structure and the ratio of microstructure size are between 1-4.It addition, insulating barrier aperture At minimum size both can more than might be less that metal be electrically connected with node size.Insulating barrier endoporus is generally less than MESA and carves More than erosion size 5um.
Embodiment three
According to one embodiment of present invention, it is provided that another metal electrode has the light-emitting diodes of array type micro structure Pipe, the method comprises the following steps:
(1) method initially with metallochemistry vapour deposition (MOCVD) be sequentially depositing on a sapphire substrate cushion, N-GaN, SQW, P-InGaN electronic barrier layer, P-GaN epitaxial layer, form complete LED P N junction structure；
(2) use alloying furnace to make annealing treatment growing complete epitaxial wafer, excite the Mg doping acceptor of p-GaN；
(3) method using chemical reagent to clean carries out step etching after processing epitaxial wafer surface, exposes n-GaN；No Being same as prior art, the entire area on epitaxial wafer surface is not performed etching by this step, but goes out in epitaxial wafer surface etch A series of micropore, exposes the first type semiconductor layer n-GaN from the micropore etched, these micropores composition microwell array, It is electrically connected with for forming noncontinuity between the first type semiconductor layer n-GaN and the first type plain conductor；Etch at MESA Time, the micropore etched has certain gradient, forms inverted trapezoidal structure, 30 °-70 ° of its inclination angle, the most beneficially insulating barrier Attachment, thus in micropore, form side wall insulating layer；
(4) crystal column surface one layer of SiO of deposition of the method for PECVD deposition is used2, by photoetching and the method for wet etching Preparing current barrier layer, in final finished product, this current barrier layer is positioned at immediately below Second-Type metal pad, for by second Type metal pad separates with transparent current extending；
(5) each layer of epitaxial wafer that the first type plain conductor micro structure and micropore are passed by the preparation of lift-off technique is used The side wall insulating layer separated；Its step is as follows:
First, positive photoresist is used to prepare required insulating layer pattern at crystal column surface；
Secondly, insulate at crystal column surface spin coating spin-coating glass (SOG) with photoetching agent pattern by the method for spin coating The film forming of layer；
Again, the hot plate of 120 ° of C toasts wafer 10min, makes spin-coating glass insulating barrier primary solidification；
Then, wafer is immersed in positive photoresist cleaning solution, sonic oscillation 20min, removes below spin-coating glass Photoresist；
Finally, the wafer cleaned up is solidified 30min in 500 ° of C high temperature furnace pipes；
(6) using thin film evaporation equipment to be deposited with one layer of transparent conductive film on epitaxial wafer surface, its thickness is according to incidence Optical wavelength and ITO refractive index and change, can be determined by equation below:
t = mλ 2 n
In formula, λ is lambda1-wavelength, and n is the refractive index of ito thin film, and m is integer, and t is the thickness of ito thin film.
(7) ito thin film photoetching, prepares, the current extending of size little 5um consistent with MESA shape；
(8) at 450 DEG C of high temperature and N2Under atmosphere annealing ITO, annealing time is 30 minutes.
(9) prepared by metal electrode, utilizes negative photoresist to prepare metal electrode pattern at crystal column surface, and steams at electron beam Electrode evaporation is completed on the equipment of sending out；
(10) at 400 DEG C of high temperature and N2Under atmosphere, metal electrode being carried out alloying, annealing time is 30 minutes；
(11) use PECVD device deposit passivation layer and removed the passivation layer on PAD surface by photoetching, etching process.
The overall structure of the light emitting diode of the present embodiment is consistent with embodiment one, repeats no more.The difference of the present embodiment Part is between the first type semiconductor layer n-GaN and the first type plain conductor to realize in the micropore that noncontinuity is electrically connected with The shape that micro structure is used.As shown in Figure 4 (b), the shape of the micro structure of the present embodiment is regular hexagon, and this shape has Reduce the effect of the total reflection probability of light.
In figure, c1 is: the length of side (referring to Fig. 5 understand) at the minimum of insulating barrier aperture, b1 is: electrically connecting of plain conductor Connecing the node length of side, b2 is: the length of side in MESA hole, and b3 is: the length of side in transparent current extending hole, and b4 is: insulating barrier lateral profile The length of side.The size of the micro structure of the present embodiment and spacing can select the most flexibly.The overall dimensions of micro structure exists Between 20um-50um, the spacing of micro structure and the ratio of microstructure size are between 1-4.It addition, at the minimum of insulating barrier aperture Size both can be more than might be less that metal is electrically connected with node size.Insulating barrier endoporus is generally less than MESA etching size 5um。
In above-described embodiment, the first wire beyond micro structure does not contact with the first type semiconductor layer, but by absolutely Edge layer is attached to the second semiconductor surface, thus traditional first type metal electrode place etch areas is prepared as noncontinuity Electric interconnection structure, thus reduce etching area, improve the area utilization of light emitting diode active area, promote chip goes out light efficiency Rate.
It addition, the present invention is while utilizing metal micro structure to realize noncontinuity electrical interconnection, it is also possible at light-emitting diodes Die luminescent layer surface makes micro structure so that luminescent layer surface coarsening, thus improves chip light-emitting efficiency further.
Need explanation time, the electrode pattern of the present invention is not limited to the pattern shown in Fig. 1, Fig. 2, such as Fig. 6 (a) and (b) 2 kinds of shown patterns can also be adopted by the present invention.Certainly, being electrically connected with micro structure not shown in Fig. 6, the present invention is using Time need on the basis of Fig. 6 (a) and (b) pattern increase be electrically connected with micro structure, this is that those skilled in the art should be readily appreciated that 's.
Finally it should be noted that above example is only in order to describe technical scheme rather than to this technical method Limiting, the present invention can extend to other amendment in application, change, applies and embodiment, and it is taken as that institute Have such amendment, change, apply, embodiment is all in the range of the spirit or teaching of the present invention.

Claims (18)

1. metal electrode has a light emitting diode for array type micro structure, serves as a contrast at epitaxial wafer including epitaxial wafer substrate and preparation Multiple structure at the end, described multiple structure is followed successively by cushion, the first type semiconductor layer, MQW activity from the bottom to top Layer, electronic barrier layer, Second-Type semiconductor layer and transparent current extending, the first type metal electrode and Second-Type metal electrode system Standby on transparent current extending, metal electrode protection pad and wire two parts, and two parts Nature Link, the first type gold Belong to and being separated by insulating barrier between electrode and transparent current extending and Second-Type semiconductor layer, the pad of Second-Type metal electrode and Separated by current barrier layer between transparent current extending, described first type metal electrode by the micropore of multiple filler metal with Described first type semiconductor layer realize electrical connection, metal in described micropore and micropore through each layer of light emitting diode Having side wall insulating layer, the superiors' deposition of described light emitting diode has passivation protection layer.
Light emitting diode the most according to claim 1, it is characterised in that described micropore has the gradient, forms inverted trapezoidal knot Structure.
Light emitting diode the most according to claim 2, it is characterised in that the inclination angle of the gradient of described micropore be 30 °～ 70°。
Light emitting diode the most according to claim 1, it is characterised in that described first type metal electrode is at described micropore There is electric connection micro structure, be electrically connected with the overall dimensions of micro structure between 20um～50um.
Light emitting diode the most according to claim 4, it is characterised in that described electric connection micro structure is divided with a determining deviation Cloth is on the wire of described first type metal electrode.
Light emitting diode the most according to claim 5, it is characterised in that the spacing of described electric connection micro structure is with described It is electrically connected with the ratio of overall dimensions of micro structure between 1～4.
Light emitting diode the most according to claim 6, it is characterised in that the endoporus chi of the side wall insulating layer in described micropore Very little at least below described pore size 5um.
Light emitting diode the most according to any one of claim 1 to 7, it is characterised in that described micropore be circular or Regular polygon, or carry wavy circle or regular polygon, or carry serrate circle or regular polygon.
Light emitting diode the most according to any one of claim 1 to 7, it is characterised in that described transparent current extending Use ITO, RuOx、IrOxOr the ZnO of the 3rd major element doping makes.
Light emitting diode the most according to any one of claim 1 to 7, it is characterised in that described transparent current extending Thickness beWherein λ is lambda1-wavelength, and n is the refractive index of described transparent current extending material, and m is integer.
11. light emitting diodes according to any one of claim 1 to 7, it is characterised in that described current blocking layer material It is SiO2Thin film, SiNxThin film or Al2O3Deielectric-coating.
12. light emitting diodes according to any one of claim 1 to 7, it is characterised in that Jie of described passivation protection layer Material is SiO2、Si3N4Or Al2O3。
13. light emitting diodes according to any one of claim 1 to 7, it is characterised in that Jie of described side wall insulating layer Material is SiO2、Si3N4、TiO2、Al2O3, spin-coating glass, polyimides or benzocyclobutene.
14. light emitting diodes according to any one of claim 1 to 7, it is characterised in that described lumination of light emitting diode Layer surface coarsening.
15. 1 kinds of metal electrodes have the preparation method of the light emitting diode of array type micro structure, comprise the following steps:
1) be sequentially prepared on epitaxial wafer substrate cushion, the first type semiconductor layer, MQW active layer, electronic barrier layer and Second-Type semiconductor layer；
2) multiple micropore is gone out to expose the first type semiconductor layer in epitaxial wafer surface etch；
3) in epitaxial wafer surface deposition of insulative material, in making the plurality of micropore, attachment insulant forms side wall insulating layer；And Position directly below at Second-Type metal electrode pad prepares current barrier layer；
4) transparent current extending is prepared；
5) make the first metal electrode and Second-Type metal electrode, and in the plurality of micropore, be full of metal, make described first Type metal electrode realizes electrically connecting with described first type semiconductor layer by the metal in the plurality of micropore；
6) make passivation protection layer, and make metal pad exposed outside in case being electrically connected with.
The preparation method of 16. light emitting diodes according to claim 15, it is characterised in that described step 2) in, use The inclination angle of 30 °～70 ° etches micropore, and making micropore is inverted trapezoidal structure.
The preparation method of 17. light emitting diodes according to claim 15, it is characterised in that described step 4) in, use Lift-off or wet corrosion technique prepare described side wall insulating layer.
The preparation method of 18. light emitting diodes according to claim 15, it is characterised in that described step 6) in, use Plasma reinforced chemical vapour deposition method, sputtering method, atomic layer deposition method deposition of insulative material.
CN201210349636.8A 2012-09-18 2012-09-18 Metal electrode has light emitting diode and the manufacture method thereof of array type micro structure Active CN103682021B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201210349636.8A CN103682021B (en) 2012-09-18 2012-09-18 Metal electrode has light emitting diode and the manufacture method thereof of array type micro structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201210349636.8A CN103682021B (en) 2012-09-18 2012-09-18 Metal electrode has light emitting diode and the manufacture method thereof of array type micro structure

Publications (2)

Publication Number Publication Date
CN103682021A CN103682021A (en) 2014-03-26
CN103682021B true CN103682021B (en) 2016-12-07

Family

ID=50318918

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210349636.8A Active CN103682021B (en) 2012-09-18 2012-09-18 Metal electrode has light emitting diode and the manufacture method thereof of array type micro structure

Country Status (1)

Country Link
CN (1) CN103682021B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105762252B (en) * 2014-12-16 2024-02-06 晶宇光电（厦门）有限公司 LED chip structure and a method of manufacturing the same
CN109004068A (en) * 2017-06-21 2018-12-14 佛山市国星半导体技术有限公司 A kind of LED chip and preparation method thereof of anti-metal migration
CN109904241A (en) * 2019-03-07 2019-06-18 地太科特电子制造(北京)有限公司 A kind of photodiode and its manufacturing method
CN111653653B (en) * 2020-06-17 2021-10-22 京东方科技集团股份有限公司 Light-emitting device, manufacturing method thereof and display panel

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1655371A (en) * 2005-02-18 2005-08-17 乐清市亿昊科技发展有限公司 Substrate structure for light-emitting diode tube core and method for making same
CN101197415A (en) * 2007-12-26 2008-06-11 江苏奥雷光电有限公司 Production method of LED chip for illumination
CN101447546A (en) * 2008-12-09 2009-06-03 武汉华灿光电有限公司 LED chip-containing photonic crystal side direction light extractor
CN102130220A (en) * 2010-01-13 2011-07-20 晶元光电股份有限公司 Photoelectric semiconductor device and manufacturing method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8367462B2 (en) * 2010-04-21 2013-02-05 Georgia Tech Research Corporation Large-scale fabrication of vertically aligned ZnO nanowire arrays

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1655371A (en) * 2005-02-18 2005-08-17 乐清市亿昊科技发展有限公司 Substrate structure for light-emitting diode tube core and method for making same
CN101197415A (en) * 2007-12-26 2008-06-11 江苏奥雷光电有限公司 Production method of LED chip for illumination
CN101447546A (en) * 2008-12-09 2009-06-03 武汉华灿光电有限公司 LED chip-containing photonic crystal side direction light extractor
CN102130220A (en) * 2010-01-13 2011-07-20 晶元光电股份有限公司 Photoelectric semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
CN103682021A (en) 2014-03-26

Similar Documents

Publication Publication Date Title
CN102097559B (en) LED and manufacture method thereof
CN102017193B (en) Semiconductor light-emitting device with double-sided passivation
CN102916028B (en) LED (light emitting diode) array and manufacturing method thereof
CN104037277A (en) LED flip chip manufacturing method and LED flip chip
TWI782286B (en) Flip chip led and manufacturing method thereof
CN105720140A (en) GaN-based LED (Light-Emitting Diode) vertical chip structure and preparation method
CN103682021B (en) Metal electrode has light emitting diode and the manufacture method thereof of array type micro structure
CN104638069A (en) Vertical LED (Light-Emitting Diode) chip structure and manufacturing method thereof
CN108258089A (en) Light emitting diode construction production method and light emitting diode construction
CN109872945A (en) A kind of compound substrate, semiconductor devices and its manufacturing method
EP2495773A1 (en) Light-emitting diode and method for manufacturing same
CN102185043A (en) Light-emitting diode and preparation method thereof, and solar cell and preparation method thereof
CN111063778A (en) Light-emitting diode structure
CN105720155B (en) A kind of Light-emitting diode LED and preparation method thereof
CN107731975B (en) Nanotube LED and manufacturing method thereof
CN105742445A (en) Vertical light emitting diode (LED) chip structure and fabrication method thereof
CN103094442A (en) Nitride light emitting diode (LED) and preparation method thereof
CN102651438B (en) Substrate, preparation method thereof and chip with substrate
CN207651512U (en) A kind of compound substrate and semiconductor device structure
CN102208506B (en) Buried high-brightness light emitting diode structure
CN106848006A (en) Flip LED chips and preparation method thereof
CN103137800B (en) A kind of LED production method
CN110571315B (en) LED chip and manufacturing method thereof
CN209747453U (en) Semiconductor device with a plurality of transistors
CN106848027B (en) The preparation method of the vertical flip LED chips of high reliability

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20221102

Address after: Floor 11, Mingzhu Building, Zhaoxin Square, Fujing Garden, No. 11, Pingzhou Nangang Road, Guicheng Street, Nanhai District, Foshan, Guangdong 528251

Patentee after: Guangdong Limited by Share Ltd Group

Address before: Jingu Optoelectronics Community, No. 1, Yong'an North Road, Pingzhou, Nanhai District, Foshan, Guangdong 528251

Patentee before: QUANTUM WAFER Inc.