CN112951954A - Light-emitting diode chip and manufacturing process thereof - Google Patents

Light-emitting diode chip and manufacturing process thereof Download PDF

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CN112951954A
CN112951954A CN202110116768.5A CN202110116768A CN112951954A CN 112951954 A CN112951954 A CN 112951954A CN 202110116768 A CN202110116768 A CN 202110116768A CN 112951954 A CN112951954 A CN 112951954A
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diffusion metal
electrode
metal layer
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CN112951954B (en
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何鹏
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Xiangneng Hualei Optoelectrical Co Ltd
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Xiangneng Hualei Optoelectrical Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure

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Abstract

The invention provides a light-emitting diode chip and a manufacturing process thereof, wherein the light-emitting diode chip comprises a current diffusion metal layer growing on a Bragg reflection layer, the current diffusion metal layer comprises a first diffusion metal layer and a second diffusion metal layer which are arranged alternately at intervals, the first diffusion metal layer is connected with a P electrode growing below the Bragg reflection layer through a first through hole penetrating through the Bragg reflection layer, the second diffusion metal layer is connected with an N electrode growing below the Bragg reflection layer through a second through hole penetrating through the Bragg reflection layer, so that the number of limited points of an electrode of one line is changed, and the problem of brightness reduction caused by too many insertion fingers in the design of an insertion finger structure is effectively reduced. The manufacturing process has simple steps and easily controlled parameters, and ensures that the light-emitting diode chip has practicability and wide application prospect.

Description

Light-emitting diode chip and manufacturing process thereof
Technical Field
The invention relates to the technical field of LED manufacturing, in particular to a light-emitting diode chip and a manufacturing process thereof.
Background
Compared with a normally-installed LED chip, the flip chip has the advantages of low thermal resistance, high current, no routing, close arrangement and the like. In recent years, flip-chip LED chips are more and more emphasized, the market scale and specific gravity of the flip-chip LED chips are increased year by year, and the market for medium-sized backlight and high light efficiency also starts to try flip-chip schemes, which has great market potential. Because the middle-size and large-size chips have higher requirements on the current diffusion capacity compared with the small-size chips, the current diffusion capacity can be improved by adopting the design of the insert finger structure, however, the number of the insert finger structures needs to be increased to improve the current diffusion capacity of the insert finger structure, the insert finger structure is made of a metal material, the light is not transmitted, and the more the insert fingers are, the more the light is blocked by the LED chip, so that the luminous efficiency of the LED chip is reduced. The number of the insertion finger structures is small, the current diffusion capability is poor, so that the resistance is increased, the voltage is increased, and the luminous efficiency is also reduced.
In summary, there is a need for a light emitting diode chip and a manufacturing process thereof to solve the problem of low light emitting efficiency of medium-sized and large-sized chips in the prior art.
Disclosure of Invention
The first objective of the present invention is to provide a light emitting diode chip, which has the following specific technical scheme:
the utility model provides a light-emitting diode chip, is including growing the electric current diffusion metal level on the Bragg reflector layer, the electric current diffusion metal level includes first diffusion metal level and the second diffusion metal level of interval and alternative arrangement, first diffusion metal level with grow the P electrode of Bragg reflector layer below through the through-hole connection of punch-through Bragg reflector layer, the second diffusion metal level with grow the N electrode of Bragg reflector layer below through the through-hole connection of punch-through Bragg reflector layer No. two.
Preferably, the light emitting diode chip further comprises a P welding layer and an N welding layer, the P welding layer and the N welding layer are arranged on the current diffusion metal layer at intervals, insulating layers are arranged between the current diffusion metal layer and the P welding layer and between the current diffusion metal layer and the N welding layer, and a plurality of third through holes are formed in the insulating layers at intervals respectively and are used for achieving communication between the P welding layer and the first diffusion metal layer and communication between the N welding layer and the second diffusion metal layer.
Preferably, each of the first and second diffusion metal layers includes a Cr layer, an Al layer, a Ni layer, a Pt layer, an Au layer, a Pt layer, and a Cr layer sequentially grown on the bragg reflection layer.
Preferably, the first diffusion metal layer and the second diffusion metal layer each include a Cr layer, an Al layer, a Ni layer, a Ti layer, an Au layer, a Ti layer, and a Cr layer sequentially grown on the bragg reflection layer.
Preferably, the light emitting diode chip further comprises a substrate, and a buffer layer, an N-type semiconductor layer, a light emitting layer, a P-type semiconductor layer, a current blocking layer and a transparent conductive layer which are sequentially grown on the substrate, wherein a step structure is arranged at one end of the N-type semiconductor layer, the N electrode is arranged on the step surface of the N-type semiconductor layer, the length of the light emitting layer and the length of the P-type semiconductor layer are equal to the length of the upper surface of the N-type semiconductor layer, the current blocking layer is grown on the partial surface of the P-type semiconductor layer, the transparent conductive layer is grown on the current blocking layer and the P-type semiconductor layer, the P electrode is arranged on the transparent conductive layer and is positioned right above the current blocking layer, and one end of the transparent conductive layer, which is close.
The second objective of the present invention is to provide a manufacturing process of a light emitting diode chip, which has the following specific technical scheme:
the manufacturing process of the light-emitting diode chip comprises the following steps:
step 1, growing a buffer layer, an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, a current blocking layer and a transparent conducting layer on a substrate in sequence, and forming a first step structure and a second step structure by adopting an ICP (inductively coupled plasma) etching method;
step 2, etching the first step structure formed in the step 1 and one end of the transparent conducting layer far away from the second step structure vertically downwards to a substrate position by adopting an ICP (inductively coupled plasma) etching method to form a single wafer;
step 3, growing a P electrode and an N electrode, specifically, after the transparent conducting layer is pretreated, a P electrode and an N electrode are respectively plated on the transparent conducting layer and the N-type semiconductor layer by adopting an evaporation table or a sputtering coating method, and the P electrode and the N electrode are obtained after post-treatment;
step 4, growing a Bragg reflection layer, specifically, plating a Bragg reflection layer on the whole structure in the step 3 by using an optical evaporation plating machine, after pretreatment, etching the positions, corresponding to the P electrode and the N electrode, on the Bragg reflection layer by using ICP (inductively coupled plasma) to form a first through hole and a second through hole;
step 5, growing a first diffusion metal layer and a second diffusion metal layer, specifically, after preprocessing the Bragg reflection layer, arranging a negative glue mask with patterns on the Bragg reflection layer by adopting an evaporation station or a sputtering coating method, coating a current diffusion metal layer on the whole surface of the negative glue mask, and performing post-processing to obtain the first diffusion metal layer and the second diffusion metal layer;
step 6, growing an insulating layer, specifically, growing and depositing the insulating layer on the first diffusion metal layer and the second diffusion metal layer by adopting a PECVD method, and etching the insulating layer at intervals by adopting an ICP etching method to obtain a plurality of third through holes;
and 7, growing a P welding layer and an N welding layer, specifically, after the insulating layer is pretreated, respectively plating the P welding layer and the N welding layer on the insulating layer by adopting an evaporation table or a sputtering coating method, and obtaining the P welding layer and the N welding layer through post-treatment.
Preferably, the post-treatment in the steps 3, 5 and 7 is to remove unnecessary metal on a corresponding growth layer of the product by a metal stripping method, then put the product into the degumming solution to be soaked for 12-18min, wash off the photoresist on the surface of the product, and dry by water.
Preferably, the etching process parameters in the step 1 are as follows: ICP power is 400-600W, RF power is 64-96W, cavity pressure is 4-6mtorr, BCl3Flow rate of 8-12sccm, Cl2The flow rate is 40-60sccm, and the etching time is 10-15 min.
Preferably, the etching process parameters in the step 2 are as follows: ICP power is 300-400W, and RF power is 120-180W, and the cavity pressure is 3-6mtorr, BCl3Flow rate of 8-12sccm, Cl2The flow rate is 40-60sccm, and the etching time is 30-45 min.
Preferably, the transparent conductive layer is an indium tin oxide thin film layer.
Preferably, the insulating layer in step 6 is SiO2Layer, the technological parameters of PECVD are as follows: the power is 40-60W, the pressure of the cavity is 680-1020mtorr, N2The flow rate of O is 800-4The flow rate is 320-2The flow rate is 320-480sccm, and the deposition time is 25-45 min.
The technical scheme of the invention has the following beneficial effects:
according to the invention, the first diffusion metal layer and the second diffusion metal layer are grown on the Bragg reflection layer and are connected with the N electrode and the P motor below the Bragg reflection layer through the first through hole and the second through hole, the N electrode and the P motor only occupy a small area, and the first diffusion metal layer and the second diffusion metal layer are arranged at intervals, so that the electrodes of one line are changed into a plurality of limited points, and the problem of brightness reduction caused by too many fingers in the finger insertion structure design is effectively reduced. Meanwhile, the first diffusion metal layer and the second diffusion metal layer effectively solve the problem that the current diffusion capacity of the transparent conducting layer is insufficient, the transparent conducting layer can be thinner, the cost is saved, light absorption can be reduced, the luminous efficiency is improved, the resistance of the first diffusion metal layer and the resistance of the second diffusion metal layer are far smaller than that of the transparent conducting layer, the diffusion capacity of current is far larger than that of the transparent conducting layer, the voltage of an LED chip is obviously reduced, and the luminous efficiency is obviously improved.
The manufacturing process has simple steps and easily controlled parameters, and ensures that the light-emitting diode chip has practicability and wide application prospect.
In addition to the objects, features and advantages described above, other objects, features and advantages of the present invention are also provided. The present invention will be described in further detail below with reference to the drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a cross-sectional view of a light emitting diode chip of embodiment 1 of the present invention, cut vertically along a P bonding plane;
fig. 2 is a cross-sectional view of a light emitting diode chip of embodiment 1 of the present invention, which is vertically cut along an N bonding plane;
fig. 3 is a top view of a light emitting diode chip of embodiment 1 (where a is a P bonding face vertical cut line of fig. 1, and B is an N bonding face vertical cut line of fig. 2);
fig. 4 is a cross-sectional view of the light emitting diode chip of comparative example 2 cut vertically along the P-bond plane;
fig. 5 is a cross-sectional view of the light emitting diode chip of comparative example 2 cut vertically along the N bonding plane;
FIG. 6 is a top view of comparative example 2 (where C is the P weld face vertical cut line of FIG. 4 and D is the N weld face vertical cut line of FIG. 5);
the LED comprises a substrate 1, a substrate 2, a buffer layer 3, an N-type semiconductor layer 4, a light emitting layer 5, a P-type semiconductor layer 6, a current blocking layer 7, a transparent conducting layer 8, a P electrode 9, an N electrode 10, a Bragg reflecting layer 11, a first diffusion metal layer 12, a second diffusion metal layer 13, an insulating layer 14, a P welding layer 15 and an N welding layer.
Detailed Description
Embodiments of the invention will be described in detail below with reference to the drawings, but the invention can be implemented in many different ways, which are defined and covered by the claims.
Example 1:
referring to fig. 1 to 3, a light emitting diode chip includes a current diffusion metal layer grown on a bragg reflector 10, the current diffusion metal layer including a first diffusion metal layer 11 and a second diffusion metal layer 12 which are alternately disposed at intervals, the first diffusion metal layer 11 being connected to a P electrode 8 grown under the bragg reflector 10 through a first through hole penetrating the bragg reflector 10, and the second diffusion metal layer 12 being connected to an N electrode 9 grown under the bragg reflector 10 through a second through hole penetrating the bragg reflector 10. Considering that the resistance of the N-type semiconductor layer 3 is much smaller than that of the P-type semiconductor layer 5, in order to achieve that the current diffusion capability of the first diffusion metal layer 11 to the P-type semiconductor layer 5 is equivalent to that of the second diffusion metal layer 12 to the N-type semiconductor layer 3, the spacing position between the first diffusion metal layer 11 and the second diffusion metal layer 12 should be arranged close to the N electrode 9, so that the area of the first diffusion metal layer 11 is larger than that of the second diffusion metal layer 12, the current diffusion capability of the first diffusion metal layer 11 to the P-type semiconductor layer 5 is enhanced by increasing the area of the first diffusion metal layer 11, and the purpose of being equivalent to that of the second diffusion metal layer 12 to the N-type semiconductor layer 3 is achieved.
The light emitting diode chip further comprises a P welding layer 14 and an N welding layer 15, the P welding layer 14 and the N welding layer 15 are arranged on the current diffusion metal layer at intervals, specifically, channels are arranged between the P welding layer 14 and the N welding layer 15, insulating layers 13 are arranged between the current diffusion metal layer and the P welding layer 14 and between the current diffusion metal layer and the N welding layer 15, and a plurality of third through holes are respectively arranged on the insulating layers 13 at intervals and used for achieving communication between the P welding layer 14 and the first diffusion metal layer 11 and communication between the N welding layer 15 and the second diffusion metal layer 12.
The first diffusion metal layer 11 and the second diffusion metal layer 12 each include a Cr layer, an Al layer, a Ni layer, a Pt layer, an Au layer, a Pt layer, and a Cr layer, which are sequentially grown on the bragg reflection layer 10. The Cr layer is used for adhering to the front film layer and the rear film layer, the Al layer plays a role in reflection, the Ni layer enhances the current tolerance, the Au layer is used for diffusing current, and the Pt layer is an inert metal layer and mainly plays an isolation role.
The light emitting diode chip also comprises a substrate 1, and a buffer layer 2, an N-type semiconductor layer 3, a light emitting layer 4, a P-type semiconductor layer 5, a current blocking layer 6 and a transparent conducting layer 7 which are sequentially grown on the substrate 1, one end of the N-type semiconductor layer 3 is provided with a first step structure, the N electrode 9 is arranged on the step surface of the N-type semiconductor layer 3, the lengths of the light emitting layer 4 and the P-type semiconductor layer 5 are equal to the length of the upper surface of the N-type semiconductor layer 3, the current blocking layer 6 grows on part of the surface of the P-type semiconductor layer 5, the transparent conducting layer 7 grows on the current blocking layer 6 and the P-type semiconductor layer 5 in equal thickness, the P electrode 8 is arranged on the transparent conducting layer and is positioned right above the current blocking layer 6, and one end of the transparent conducting layer, which is close to the N electrode 9, and the P-type semiconductor layer 5 form a second step structure.
The manufacturing process of the light-emitting diode chip comprises the following steps:
step 1, growing a buffer layer 2, an N-type semiconductor layer 3, a light-emitting layer 4, a P-type semiconductor layer 5, a current blocking layer 6 and a transparent conducting layer 7 on a substrate 1 in sequence (the growing process is the prior art), and forming a first step structure and a second step structure by adopting an ICP (inductively coupled plasma) etching method;
step 2, vertically etching the first step structure formed in the step 1 and one end of the transparent conducting layer far away from the second step structure downwards to the position of the substrate 1 by adopting an ICP (inductively coupled plasma) etching method to form a single wafer;
step 3, growing a P electrode 8 and an N electrode 9, specifically, after the transparent conducting layer is pretreated, the P electrode 8 and the N electrode 9 are respectively plated on the transparent conducting layer and the N-type semiconductor layer 3 by adopting an evaporation table or a sputtering coating method, and the P electrode 8 and the N electrode 9 are obtained after post-treatment;
step 4, growing a Bragg reflection layer 10, specifically, plating a Bragg reflection layer 10 on the whole structure in the step 3 by using an optical evaporation machine, after pretreatment, etching the positions, corresponding to the P electrode 8 and the N electrode 9, of the Bragg reflection layer 10 to the P electrode 8 and the N electrode 9 by using ICP (inductively coupled plasma) to form a first through hole and a second through hole;
step 5, growing a first diffusion metal layer 11 and a second diffusion metal layer 12, specifically, after preprocessing the Bragg reflection layer 10, arranging a negative glue mask with patterns on the Bragg reflection layer 10 by adopting an evaporation station or a sputtering coating method, plating a current diffusion metal layer on the whole surface of the negative glue mask, and performing post-processing to obtain the first diffusion metal layer 11 and the second diffusion metal layer 12;
step 6, growing an insulating layer 13, specifically, growing and depositing the insulating layer 13 on the first diffusion metal layer 11 and the second diffusion metal layer 12 by adopting a PECVD (plasma enhanced chemical vapor deposition) method, and etching the insulating layer 13 at intervals by adopting an ICP (inductively coupled plasma) etching method to obtain a plurality of third through holes;
and 7, growing a P welding layer 14 and an N welding layer 15, specifically, after the insulating layer 13 is pretreated, respectively plating the P welding layer 14 and the N welding layer 15 on the positions, corresponding to the P electrode 8 and the N electrode 9, of the insulating layer 13 by adopting an evaporation table or a sputtering film coating method, and obtaining the P welding layer 14 and the N welding layer 15 through aftertreatment.
The post-treatment in the steps 3, 5 and 7 is to remove unnecessary metal on the corresponding growth layer of the product by a metal stripping method, put the product into the degumming solution to be soaked for 15min, wash off the photoresist on the surface of the product, and wash and spin-dry the product by water.
The etching process parameters in the step 1 are as follows: ICP power was 500W, RF power was 80W, and chamber pressure was 5mtorr, BCl3Flow rate of 10sccm, Cl2The flow rate is 50sccm, and the etching time is 12 min.
The etching process parameters in the step 2 are as follows: ICP power of 350W, RF power of 150W, and chamber pressure of 4.5mtorr, BCl3Flow rate of 10sccm, Cl2The flow rate is 50sccm, and the etching time is 40 min.
The transparent conducting layer is an indium tin oxide thin film layer.
The insulating layer 13 in step 6 is SiO2Layer, the technological parameters of PECVD are as follows: power 50W, chamber pressure 850mtorr, N2O flow rate 1000sccm, SiH4The flow rate is 400sccm, N2The flow rate was 400sccm and the deposition time was 35 min.
The pretreatment of the invention comprises glue homogenizing, soft baking, exposure, development and film hardening, and then the pattern on the photoetching plate is copied to the surface of the product, which is a conventional technology.
Example 2:
unlike embodiment 1, the Pt layers of the first diffusion metal layer 11 and the second diffusion metal layer 12 are Ti layers.
Comparative example 1:
unlike embodiment 1, the first diffusion metal layer 11 and the second diffusion metal layer 12 are not provided.
Comparative example 2:
referring to fig. 4 to 6, unlike embodiment 1, the first diffusion metal layer 11, the second diffusion metal layer 12, and the insulating layer 13 are not provided.
The light emitting diode chips prepared in the embodiments 1-2 and the comparative examples 1-2 are respectively packaged into lamp beads by adopting DX-20C insulating glue, Hongda 00902 fluorescent powder, a Chiming 2835 bracket, Dow Corning silica gel 6636 and 0.8mil gold wires, and the light effect performance data in the table 1 are obtained by testing under the same integrating sphere. In table 1, luminous efficiency is luminous flux ÷ power, and power is test current × voltage.
TABLE 1 comparison of the luminous efficacy of the LED chips prepared in examples 1-2 and comparative examples 1-2
Serial number Test Current/(mA) voltage/(V) Luminous flux/(lm) Luminous efficiency/(lm/W)
Example 1 60 2.72 24.58 150.61
Example 2 60 2.71 24.18 148.71
Comparative example 1 60 2.83 22.59 133.04
Comparative example 2 60 2.85 22.50 131.58
As is clear from the data of table 1, the light emitting diode chips prepared in examples 1 to 2 were significantly lower in voltage than comparative examples 1 to 2 and significantly higher in luminous flux than comparative examples 1 to 2 under the condition of a certain test current, so that the luminous efficiencies were significantly higher than comparative examples 1 to 2.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. The light emitting diode chip is characterized by comprising a current diffusion metal layer grown on a Bragg reflection layer (10), wherein the current diffusion metal layer comprises a first diffusion metal layer (11) and a second diffusion metal layer (12) which are arranged at intervals and alternately, the first diffusion metal layer (11) is connected with a P electrode (8) grown below the Bragg reflection layer (10) through a first through hole penetrating through the Bragg reflection layer (10), and the second diffusion metal layer (12) is connected with an N electrode (9) grown below the Bragg reflection layer (10) through a second through hole penetrating through the Bragg reflection layer (10).
2. The light-emitting diode chip as claimed in claim 1, further comprising a P bonding layer (14) and an N bonding layer (15), wherein the P bonding layer (14) and the N bonding layer (15) are disposed on the current diffusion metal layer at intervals, an insulating layer is disposed between the current diffusion metal layer and the P bonding layer (14) and between the current diffusion metal layer and the N bonding layer (15), and a plurality of through holes of three numbers are disposed on the insulating layer (13) at intervals respectively for achieving communication between the P bonding layer (14) and the first diffusion metal layer (11) and communication between the N bonding layer (15) and the second diffusion metal layer (12).
3. The light-emitting diode chip as claimed in claim 2, characterized in that the first and second diffused metal layers (11, 12) each comprise a Cr layer, an Al layer, a Ni layer, a Pt layer, an Au layer, a Pt layer and a Cr layer grown in this order on the bragg reflector layer (10).
4. The light-emitting diode chip as claimed in claim 2, characterized in that the first diffusion metal layer (11) and the second diffusion metal layer (12) each comprise a Cr layer, an Al layer, a Ni layer, a Ti layer, an Au layer, a Ti layer and a Cr layer grown in this order on the bragg reflector layer (10).
5. The light-emitting diode chip according to claim 3 or 4, further comprising a substrate (1), and a buffer layer (2), an N-type semiconductor layer (3), a light-emitting layer (4), a P-type semiconductor layer (5), a current blocking layer (6) and a transparent conductive layer (7) which are sequentially grown on the substrate (1), wherein a first step structure is provided at one end of the N-type semiconductor layer (3), the N electrode (9) is disposed on a step surface of the N-type semiconductor layer (3), the length of the light-emitting layer (4) and the length of the P-type semiconductor layer (5) are equal to the length of an upper surface of the N-type semiconductor layer (3), the current blocking layer (6) is grown on a part of the surface of the P-type semiconductor layer (5), the transparent conductive layer (7) is grown on the current blocking layer (6) and the P-type semiconductor layer (5), the P electrode (8) is disposed on the transparent conductive layer (7) and is located right above the current blocking layer (6), one end of the transparent conducting layer (7) close to the N electrode (9) and the P-type semiconductor layer (5) form a second step structure.
6. The process for manufacturing the light-emitting diode chip as claimed in claim 5, comprising the steps of:
step 1, growing a buffer layer (2), an N-type semiconductor layer (3), a light-emitting layer (4), a P-type semiconductor layer (5), a current blocking layer (6) and a transparent conductive layer (7) on a substrate in sequence, and forming a first step structure and a second step structure by adopting an ICP (inductively coupled plasma) etching method;
step 2, vertically etching the first step structure formed in the step 1 and one end, far away from the second step structure, of the transparent conducting layer (7) downwards to the position of the substrate (1) by adopting an ICP (inductively coupled plasma) etching method to form a single wafer;
step 3, growing a P electrode (8) and an N electrode (9), specifically, after the transparent conducting layer (7) is pretreated, the P electrode (8) and the N electrode (9) are respectively plated on the transparent conducting layer (7) and the N-type semiconductor layer (3) by adopting an evaporation table or a sputtering coating method, and the P electrode (8) and the N electrode (9) are obtained through post-treatment;
step 4, growing a Bragg reflection layer (10), specifically, plating a Bragg reflection layer (10) on the whole structure in the step 3 by using an optical evaporation plating machine, after pretreatment, etching the positions, corresponding to the P electrode (8) and the N electrode (9), of the Bragg reflection layer (10) by adopting ICP (inductively coupled plasma) to the P electrode (8) and the N electrode (9) to form a first through hole and a second through hole;
step 5, growing a first diffusion metal layer (11) and a second diffusion metal layer (12), specifically, after preprocessing the Bragg reflection layer (10), arranging a negative glue mask with patterns on the Bragg reflection layer (10) by adopting an evaporation station or a sputtering coating method, plating a current diffusion metal layer on the whole surface of the negative glue mask, and performing post-processing to obtain the first diffusion metal layer (11) and the second diffusion metal layer (12);
step 6, growing an insulating layer (13), specifically, growing and depositing the insulating layer (13) on the first diffusion metal layer (11) and the second diffusion metal layer (12) by adopting a PECVD method, and etching the insulating layer (13) at intervals by adopting an ICP (inductively coupled plasma) etching method to obtain a plurality of third through holes;
and 7, growing a P welding layer (14) and an N welding layer (15), specifically, after the insulating layer (13) is pretreated, respectively plating the P welding layer (14) and the N welding layer (15) on the insulating layer (13) by adopting an evaporation table or a sputtering film coating method, and obtaining the P welding layer (14) and the N welding layer (15) through post-treatment.
7. The manufacturing process of claim 6, wherein the post-treatment in the steps 3, 5 and 7 is to remove unnecessary metal on the corresponding growth layer of the product by a metal stripping method, then to put the product into the degumming solution to be soaked for 12-18min, to wash away the photoresist on the surface of the product, and to dry by water.
8. The manufacturing process according to claim 7, wherein the etching parameters in the step 1 are as follows: ICP power is 400-600W, RF power is 64-96W, cavity pressure is 4-6mtorr, BCl3Flow rate of 8-12sccm, Cl2The flow rate is 40-60sccm, and the etching time is 10-15 min.
9. The manufacturing process according to claim 8, wherein the etching parameters in the step 2 are as follows: ICP power is 300-400W, RF power is 120-180W, and cavity pressure is 3-6mtorr, BCl3Flow rate of 8-12sccm, Cl2The flow rate is 40-60sccm, and the etching time is 30-45 min.
10. Production process according to claim 9, characterized in that the insulating layer (13) in step 6 is SiO2Layer, the technological parameters of PECVD are as follows: the power is 40-60W, the pressure of the cavity is 680-1020mtorr, N2The flow rate of O is 800-4The flow rate is 320-2The flow rate is 320-480sccm, and the deposition time is 25-45 min.
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