WO2014187235A1

WO2014187235A1 - Method for manufacturing directly attached semiconductor light-emitting eutectic wafer

Info

Publication number: WO2014187235A1
Application number: PCT/CN2014/076841
Authority: WO
Inventors: 严敏; 程君; 周鸣波
Original assignee: Yan Min; Cheng Jun; Zhou Mingbo
Priority date: 2013-05-21
Filing date: 2014-05-06
Publication date: 2014-11-27
Also published as: CN103311385B; CN103311385A

Abstract

A method for manufacturing a directly attached semiconductor light-emitting eutectic wafer comprises: performing graphical processing on the front side and the back side of a transparent body substrate; performing epitaxial growth on the transparent body substrate after the graphical processing, to obtain an epitaxial wafer; performing a forepart process on the epitaxial wafer, wherein metal photoetching is performed on the epitaxial wafer, an electrode pattern is formed on the epitaxial wafer by using photoresist, and metal evaporation is further performed, to obtain an epitaxial wafer with an electrode; performing reverse molding processing on the epitaxial wafer; performing laser cutting on the epitaxial wafer after the reverse molding processing, to obtain a semiconductor light-emitting eutectic wafer. The manufacturing method omits multiple traditional processes, and improves product reliability.

Description

Method for manufacturing direct-welding semiconductor light-emitting eutectic wafers This application claims to be submitted to the Chinese Patent Office on May 21, 201, the application number is

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The present invention relates to the field of semiconductors, and more particularly to a method for fabricating a direct-attach (DA) semiconductor light-emitting eutectic wafer. Background technique

The traditional semiconductor light-emitting chip fabrication process, that is, to form an epitaxial wafer by MOCVD, and then the post-process #electrode, can be handed over to the downstream application by cutting and grading, and then "package" (PACKAGE) before downstream application. It is then fixed on the circuit carrier (PCB) of the application to implement the relevant electrical connections and functions.

In the electrode fabrication in the post-wafer process, it is mainly to produce an electrode which can be used for ultrasonic welding of a gold wire or an aluminum wire for downstream use.

Before the downstream application, the "package" should be done first, mainly on a reasonable bracket (FRAME) with a conductive silver glue (process name: solid crystal) to install one of the electrodes and make an electrical connection, and then The other electrode of the wafer is soldered by gold wire or aluminum wire and connected to another independent electrical pin of the bracket by an ultrasonic wire bonding machine, and finally the wafer, a part of the bracket and the gold wire connecting them are connected with a transparent epoxy resin. Or the aluminum wire is sealed together with a mold (also called a casting mold) which has been previously designed with an optical lens. The pins of some electrical brackets are exposed. They are used as electrical carriers (PCBs) for SMT connections or DIP (plug-in) installations when used with other electronic devices. Used above.

In the process of "packaging", because the wire must be soldered, it is necessary to leave an opaque gold or aluminum wire solder joint on the light-emitting surface to cover part of the light-emitting direction, and a spot light in a separate point source. There is a hollow "black" heart point, rather than an ideal spot with a uniform point source.

In the market environment where semiconductor light-emitting applications are becoming more cost-effective, there is a huge price reduction requirement for the supply cost of semiconductor light.

In addition, the traditional process has come to an end in the case of small pitch and high density, and it cannot be directly applied at a pitch (PITCH) of 1.0 mm or less. Summary of the invention

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of fabricating a semiconductor light emitting DA (Direct Attach) eutectic wafer capable of overcoming the above drawbacks.

The invention provides a semiconductor light emitting DA (Direct Attach Direct Bonding) eutectic wafer manufacturing method, comprising: patterning both the front side and the back side of the substrate; performing epitaxial growth on the imaged substrate ( EPI: Epitaxy) obtains an epitaxial wafer; performs a pre-stage process on the obtained epitaxial wafer, performs metal photolithography on the epitaxial wafer in the preceding step, forms an electrode pattern on the epitaxial wafer with a photoresist, and performs metal evaporation on the epitaxial wafer Depositing Cr, Ni, Au, Ti, Sn, the outermost layer of the deposited layer after metal evaporation is an AuSn alloy layer, to obtain an epitaxial wafer having electrodes; and performing epitaxial processing on the epitaxial wafer after the previous step processing; The film-treated epitaxial wafer was subjected to laser cutting to obtain a semiconductor light-emitting DA (Direct Attach Direct Bonding) eutectic wafer.

Preferably, the epitaxial growth is performed by metallurgical chemical vapor deposition MOCVD. Preferably, the substrate is sapphire (ΑΙ_2〇3) or silicon carbide (SiC), and the patterning process uses an imaged sapphire (ΑΙ_2〇3) or silicon carbide (SiC) substrate PSS process.

Preferably, the preceding step further comprises: performing photolithography on the surface of the epitaxial wafer by using a photoresist and a mask having a predetermined pattern; etching the epitaxial wafer after photolithography; Epitaxial wafer for current blocking layer CBL deposition; epitaxy after deposition of current blocking layer The film is subjected to CBL lithography; the CBL etched epitaxial wafer is subjected to CBL etching; the CBL etched epitaxial wafer is deposited by current diffusion layer using nano-indium tin oxide ITO; and the ITO is deposited on the epitaxial wafer after current diffusion layer deposition Photolithography; performing ITO etching on the epitaxial wafer after ITO photolithography; pre-annealing the epitaxial wafer after ITO etching;

Preferably, the preceding step further comprises: after the metal lithography and before the metal evaporation, ashing the epitaxial wafer after metal lithography.

Preferably, the preceding step further comprises: stripping the epitaxial wafer to peel off the metal other than the electrode after the metal evaporation; and performing passivation layer deposition on the epitaxial wafer after stripping by plasma enhanced chemical vapor deposition The epitaxial wafer after the deposition of the passivation layer is subjected to rapid annealing treatment.

Preferably, the preceding step further comprises: performing a solderability simulation test WST on the epitaxial wafer after the rapid annealing treatment.

Preferably, the surface of the epitaxial wafer is ground and thinned after the preceding process and before the mold reduction process

Preferably, the epitaxial wafer obtained by the epitaxial growth is gallium nitride GaN (two elements) or InGaN (three elements) or InGaAIP (four elements), and the P type layer is P-GaN (two elements) or InGaN (three Element) or InGaAIP (four elements), N-type layer is N-GaN (two elements) or InGaN (three elements) or InGaAIP (four elements).

Preferably, the current blocking layer is deposited with silicon dioxide SiO 2 as an isolation dielectric layer.

In the manufacturing process of the present invention, an epitaxial wafer suitable for use in the post-process of the present invention is first produced in the MOCVD interval, which is the first point of the present invention, "transparent substrate" and "double-sided patterning". "Production, this is the basis for achieving "flip-flop" after the completion of the post-process. Moreover, there will be no impurities accompanying the phenomenon of uneven light or the phenomenon of blackouts that produce a "black" heart. The invention saves many traditional processing steps, and improves the stability, reliability, reliability and the like of the product and the traditional MTBF measurement index by more than 10 times, and is a household lighting and high-quality large-scale production of semiconductor light-emitting applications. The most basic foundation guarantee. DRAWINGS

1 is a flow chart showing a method of fabricating a semiconductor light emitting DA (Direct Attach Direct Bond) eutectic wafer according to an embodiment of the present invention;

2 is a schematic diagram of a semiconductor light emitting DA (Direct Attach) eutectic wafer fabricated in accordance with an embodiment of the present invention;

3 is a graph showing changes in physical characteristics of a semiconductor light emitting DA (Direct Attach) eutectic wafer according to an embodiment of the present invention;

4 is a schematic diagram of light intensity and illumination angle of a semiconductor light emitting DA (Direct Attach direct solder eutectic wafer) fabricated in accordance with an embodiment of the present invention.

The technical solution of the present invention will be further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a flow chart showing a method of fabricating a semiconductor light emitting DA (Direct Attach direct bonding eutectic wafer) according to an embodiment of the present invention.

1. Epitaxial growth (EPI: Epitaxy) was carried out on a substrate material of a transparent body to obtain an epitaxial wafer, as described below.

In general, sapphire or silicon carbide SiC can be used as the substrate, and the main component of sapphire is aluminum oxide AI203. Currently, sapphire or silicon carbide SiC is the most commonly used substrate material for GaN (two-element) or InGaN (three-element) or InGaAIP (quad-element) heteroepitaxial.

First, use a patterned sapphire (AL2O3) or silicon carbide (SiC) substrate.

The (pattern Sapphire Substrate, PSS) process graphically processes the substrate. Preferably, the patterning process performs a patterning process on both the front side and the back side of the substrate. After PSS processing, the patterned front and back sides of the substrate are aligned for the laser cutting tool after the completion of the post-process, without damaging the wafer body.

Next, epitaxial growth is performed on the patterned substrate. Preferably, the growth of the epitaxial layer can be performed in accordance with an Inductive Coupled Plasma (ICP) process. Specifically, through That is, a plurality of thin single crystals or compounds are deposited on a substrate material of a single crystal or a compound, and the layer formed by the deposition is referred to as an epitaxial layer, and the substrate on which the epitaxial layer is deposited is referred to as an epitaxial wafer. Epitaxial growth can be carried out by means of Metal-Organic Chemical Vapor Deposition (MOCVD). Specifically, MOCVD is a raw material for crystal growth using an organic compound of a group III or a group II element and a hydride of a group V or VI element, and is subjected to vapor phase epitaxy on a substrate by thermal decomposition reaction to grow various mv groups. Thin-layer single crystal materials of Π-VI compound semiconductors and their multiple solid solutions. For example, by MOCVD, a PN junction can be formed on the front side of the patterned substrate, i.e., adjacent P-type layers and N-type layers are formed. Depending on the raw materials used, the epitaxial layer can be formed as two elements of gallium nitride (GaN) or InGaN (three elements) or InGaAIP (four elements), and the P-type layer is P-GaN (two elements) or InGaN ( Three elements) or InGaAIP (four elements), N-type layers are N-GaN two elements) or InGaN (three elements) or InGaAIP (four elements).

Finally, the epitaxial wafer is cleaned by various methods to remove particulate matter and metal ions from the surface of the epitaxial wafer.

2. The epitaxial wafer obtained by epitaxial growth is subjected to the previous step, and is specifically described below.

First, the surface of the epitaxial layer is photolithographically patterned using an optical resist (PR) and a mask having a predetermined pattern so that the photoresist on the surface of the epitaxial layer forms the predetermined pattern. The pattern appears as an array of a plurality of wafer patterns, each of which is a N-electrode position in the hollow, and a P-type/light-emitting area in the non-hollowed area, with a scribe line between each pattern.

Next, the lithographic epitaxial wafer is etched, and the photoresist-free region is etched to the N-type layer to expose the epitaxial layer at the N-electrode position.

Next, a Current Blocking Layer (CBL) deposition is performed, and the CBL is generally made of silicon dioxide SiO 2 as an isolation dielectric layer. In this way, it is possible to prevent the light from being blocked/light-blocking (PN junction) from being illuminated, thereby improving the effective current injection.

Next, CBL lithography is performed on the epitaxial wafer after CBL deposition.

Next, a CBL etch is performed to etch away SiO 2 where there is no photoresist protection. Next, current diffusion layer deposition is performed on the epitaxial wafer after CBL etching, and the current diffusion layer is The deposition is generally carried out using Indium Tin Oxides (ITO).

Next, iridium lithography is performed to protect the area requiring ruthenium with photoresist, and to pattern the next ΙΤ0 etch.

Next, a ruthenium etch is performed to etch the ruthenium and SiO 2 where the photoresist is not protected.

Next, pre-annealing is performed. In other words, high-temperature heat treatment is performed, as a result of which the forward voltage of the wafer can be lowered, the formation of the surface contact of the current diffusion layer is facilitated, and the surface current uniformity is improved.

Next, metal lithography is performed on the epitaxial wafer, that is, an electrode pattern is formed using a photoresist.

Next, the epitaxial wafer is subjected to an ashing process. Ashing can be done by plasma degumming. Specifically, the wafer is cleaned with oxygen and nitrogen to make the photoresist surface of the wafer more flat. The ashing treatment also removes the negative glue at the electrodes, thereby improving electrode adhesion.

Next, the epitaxial wafer was subjected to metal evaporation to deposit Cr, Ni, Au, Ti, Sn. The outermost layer of the deposited layer after evaporation is an AuSn alloy layer.

Next, the epitaxial wafer is lifted-off to peel off the metal other than the electrode.

Next, a passivation layer is deposited on the epitaxial wafer. Specifically, the plasma enriched chemical vapor deposition (PECVD) can be used for the deposition of the passivation layer, and the SiO2 film can be used as a passivation layer to prevent short circuit and avoid the adsorption of impurity atoms on the surface of the chip. IT0 film, improve luminous efficiency.

Next, the epitaxial wafer is subjected to rapid annealing treatment. The wafer can be screened once in a customer's environment by rapid annealing and high temperature heat treatment.

Finally, a Weldability Simulation Test (WST) was performed to test the adhesion of the electrodes in the solder.

3. The post-process of the epitaxial wafer obtained in the previous step is carried out as follows.

First, the surface of the chip is ground and thinned, followed by mold-cutting, and finally laser cutting, and the LED wafer is cut and formed. Finally, after automatic visual inspection, classification, packaging, Shipped.

2 is a schematic diagram of a semiconductor light emitting DA (Direct Attach direct solder eutectic wafer) fabricated in accordance with an embodiment of the present invention.

The specific parameters of the eutectic wafer can be obtained by combining the following table. structure size:

A direct-welding (DA) wafer according to an embodiment of the present invention uses a high-luminance efficiency gallium nitride (GaN) two-element or InGaN (three-element) or aluminum-indium-phosphorus-phosphorus four-element (AllnGaP) material and a silicon carbide substrate ( Made of SiC or sapphire substrate (AI203), it is a high-brightness top-emitting flip-chip structure with low driving voltage and high luminous efficiency. Pads that are directly mounted or soldered to the carrier board circuit. The material used for the pads can be eutectic soldering of AuSn alloy or LEP mounting of common copper-tin alloys.

Fig. 3 is a graph showing changes in physical properties of a semiconductor light-emitting eutectic wafer according to an embodiment of the present invention.

Combined with the table below, the main object characteristics can be known. Main physical characteristics

Wavelength (nm) 450-640

Power (mw) 80≤ Electrical characteristics Ta=25 ° C parameters

Wavelength (nm) 450-470

Power (mw) 80≤

Forward voltage (V) 1.85-3.6

Forward current (mA) 1-20

Peak forward current (mA) 10-30

Reverse voltage (V) 5

Reverse current (μΑ) 2

Half-wave width (nm) 20

Working temperature (° C ) -40-+100

Storage temperature (° C ) -40-+100

Static Load Threshold (HBM) (V) 1000

Electrostatic load level (MIL-STD-883E) 2

Brightness level (MCD)

4 is a schematic illustration of light intensity and illuminating angle of a eutectic wafer fabricated in accordance with an embodiment of the present invention. The present invention includes, but is not limited to, the most common method of fabricating a red light, green light, blue light semiconductor light emitting DA (Direct Attach Direct Bond) eutectic wafer.

In this manufacturing process, an epitaxial wafer suitable for use in the post-process of the present invention is first produced in the MOCVD interval, and is the first point of the present invention, "transparent substrate" and "double-sided patterning". This is the basis for achieving "flip-chip" after the completion of the post-process. Moreover, there will be no impurities accompanying the phenomenon of uneven light or the phenomenon of light-sinking "black" heart spots.

The electrode fabricated in the post-process of the present invention is a eutectic electrode, which is a five-element electrode, which can be directly eutectic soldering process or LEP mounting on the electrical carrier (PCB) of the application product to complete with other electronic components. Electrical connection of the device and related. Eliminate the traditional "packaging" processing process (in addition to the cost of gold wire, bracket, rubber and other materials used in this process, the processing of equipment, such as solid crystal, wire bonding, automatic wire casting, etc.) Cost and labor cost And the process of processing this process must be added 25-30% of the cost of profits and taxes. Can save the semiconductor lighting supply to double the original cost). Improve the light output efficiency by 10%.

In the present invention, since the SMT process of the conventional application product is omitted (the flux is consumed here, the power consumption of the reflow machine, the tin furnace, etc.), the eutectic gold tin is produced in the post-process electrode production. The conductive layer is then directly soldered (DA: Direct Attach) using a eutectic soldering device to the LEP-mounted wafer on the electrical carrier (PCB) of the application product. Therefore, the application processing program is greatly simplified.

The present invention breaks the application limitations of semiconductor light-emitting wafers at a small pitch (PITCH) of 1.0 mm, since it is no longer limited by the additional volume limitations of semiconductor light emitters due to post-processing (packaging). It is possible to fabricate eutectic devices of any size. A wider application of semiconductor luminescence can be achieved.

In the present invention, since many processing steps of conventional application products are omitted, the stability, reliability, reliability, and the like of the product and the traditional MTBF (Mean Time Between Failure) measurement index will be Increase by more than 10 times. It is the most basic guarantee for the household lighting and high-quality large-scale production of semiconductor lighting applications.

The invention will also bring about a material revolution in the application of other related semiconductor products, and we can use a material with a stable mechanical strength (such as a glass substrate) (or a laminated substrate, or a silicon plate) to make a circuit. Carrier.

A person skilled in the art should further appreciate that the elements and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both, in order to clearly illustrate hardware and software. Interchangeability, the composition and steps of the various examples have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods for implementing the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present invention.

The steps of a method or algorithm described in connection with the embodiments disclosed herein can be implemented in hardware, a software module executed by a processor, or a combination of both. Software modules can be placed in random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

The above described embodiments of the present invention are further described in detail, and the embodiments of the present invention are intended to be illustrative only. The scope of the protection, any modifications, equivalents, improvements, etc., made within the spirit and scope of the invention are intended to be included within the scope of the invention.

Claims

claims

1. A method for manufacturing a semiconductor light-emitting eutectic wafer that directly welds DA, including: patterning both the front and back of a transparent substrate;

Epitaxial growth of EPI is performed on the imaged transparent substrate to obtain an epitaxial wafer; the obtained epitaxial wafer is subjected to a pre-process, in which the epitaxial wafer is subjected to metal photolithography, and a photoresist is used to form the epitaxial wafer. Electrode pattern, and perform metal evaporation on the epitaxial wafer to deposit Cr, Ni, Au, Ti, Sn. The outermost layer deposited after metal evaporation is an AuSn alloy layer to obtain an epitaxial wafer with electrodes;

The epitaxial wafer processed in the previous process is flip-chip processed;

The epitaxial wafer after reverse film processing was laser cut to obtain a semiconductor luminescence system directly welded to DA.

Say, say, ΐ.

2. The method according to claim 1, wherein the epitaxial growth adopts metal organic chemical vapor deposition (MOCVD).

3. The method according to claim 1, wherein the substrate is sapphire AL203 or silicon carbide SiC, and the patterning process adopts a patterned sapphire substrate PSS process.

4. The method according to claim 1, wherein the front-end process before the metal photolithography further includes:

Use photoresist and a mask with a predetermined pattern to photoetch the surface of the epitaxial wafer;

Etch the epitaxial wafer after photolithography;

Deposit the current blocking layer CBL on the etched epitaxial wafer;

Perform CBL photolithography on the epitaxial wafer after the current blocking layer is deposited;

Perform CBL etching on the epitaxial wafer after CBL photolithography;

Use nano-indium tin oxide ITO for current diffusion layer deposition on the epitaxial wafer after CBL etching; perform ITO photolithography on the epitaxial wafer after current diffusion layer deposition;

Perform ITO etching on the epitaxial wafer after ITO photolithography;

Pre-anneal the epitaxial wafer after ITO etching.

5. The method according to claim 1, wherein the front-end process after the metal photolithography and before the metal evaporation further includes:

The epitaxial wafer after metal photolithography is ashed.

6. The method according to claim 1, wherein the front-end process after the metal evaporation further includes:

Peel off the epitaxial wafer and peel off the metal other than the electrodes;

Plasma-enhanced chemical vapor deposition is used to deposit a passivation layer on the stripped epitaxial wafer; and a rapid annealing treatment is performed on the epitaxial wafer after the passivation layer is deposited.

7. The method according to claim 1, the preceding steps further include:

Weldability simulation test WST was performed on epitaxial wafers after rapid annealing treatment.

8. The method of claim 1, further comprising:

After the previous process and before the molding process, the surface of the epitaxial wafer is ground and thinned.

9. The method according to claim 1, wherein the epitaxial wafer obtained by the epitaxial growth is gallium nitride GaN or InGaN, and its P-type layer is P-GaN or InGaN or InGaAIP, and its N-type layer is correspondingly Ground is N-GaN or InGaN or lnGaAIP.

10. The method according to claim 4, wherein the current blocking layer is deposited using silicon dioxide SiO2 as an isolation dielectric layer.