CN109638131B - Manufacturing method of DBR flip chip - Google Patents
Manufacturing method of DBR flip chip Download PDFInfo
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- CN109638131B CN109638131B CN201811451640.9A CN201811451640A CN109638131B CN 109638131 B CN109638131 B CN 109638131B CN 201811451640 A CN201811451640 A CN 201811451640A CN 109638131 B CN109638131 B CN 109638131B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/387—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0025—Processes relating to coatings
Abstract
The invention relates to a manufacturing method of a DBR flip chip, which comprises the following steps: step one, manufacturing an epitaxial layer; etching an N-type step on the epitaxial layer structure; growing a reflecting layer and a metal binding layer on the surface of the epitaxial layer respectively; growing a DBR Bragg reflector layer on the DBR flip chip, and respectively etching a P electrode conductive hole and an N electrode conductive hole; and step five, according to the arrangement of the conductive holes, evaporating a current expansion metal layer on the DBR Bragg reflector layer and enabling the P electrode conductive hole and the N electrode conductive hole to be connected respectively. The manufacturing method of the DBR flip chip provided by the invention can ensure the uniform expansion of current under the use condition of large current and high power so as to meet the condition that the DBR flip chip is applied to high power.
Description
Technical Field
The invention relates to the field of LED flip chips, in particular to a manufacturing method of a DBR flip chip.
Background
Traditional DBR flip chip technology is on the basis of just adorning chip technology, in just adorning the front evaporation plating DBR passivation layer of chip, as the reflector layer, again in the etching of DBR layer goes out corresponding P electrode electrically conductive hole and N electrode electrically conductive hole, at last in the evaporation plating P, N electrode layer of DBR surface. The electrode layers respectively cover the P electrode conductive hole and the N electrode conductive hole in the DBR layer, and the P, N electrode holes are used for conducting the chip downwards, so that the flip chip effect is obtained. Because the traditional flip chip adopts the DBR reflector as the reflecting layer, the area of the current expansion metal layer between the luminous layer and the reflecting layer cannot be too large, so that the reflecting area is reduced. The region of the non-current expansion metal layer adopts a transparent metal conductive film to play a role in current expansion, the transparent metal conductive film cannot be too thick, and the transparent metal conductive film can absorb light more strongly if being too thick, so that the transparent metal conductive film is not beneficial to light transmission. Under the condition of large-current and high-power use, the thin transparent metal conductive film is not enough for uniform current expansion, so that the traditional DBR flip chip is not suitable for large-current and high-power use.
Disclosure of Invention
The invention provides a manufacturing method of a DBR flip chip, which can ensure the uniform expansion of current under the use condition of large current and high power so as to meet the condition that the DBR flip chip is applied to high power.
In order to achieve the purpose, the invention provides a manufacturing method of a DBR flip chip, which comprises the following steps: step one, manufacturing an epitaxial layer; etching an N-type step on the epitaxial layer structure; growing a reflecting layer and a metal binding layer on the surface of the epitaxial layer respectively; growing a DBR Bragg reflector layer on the DBR flip chip, and respectively etching a P electrode conductive hole and an N electrode conductive hole; and step five, according to the arrangement of the conductive holes, evaporating a current expansion metal layer on the DBR Bragg reflector layer and enabling the P electrode conductive hole and the N electrode conductive hole to be connected respectively.
Preferably, the first step comprises: a buffer layer, an N-GaN layer, a light-emitting quantum well and a P-GaN layer are sequentially grown on a sapphire substrate through MOCVD equipment.
Preferably, the second step comprises: and etching an N-type step on the epitaxial layer structure and enabling the N-GaN layer to be in a naked state.
Preferably, the third step comprises: sequentially growing a TCL transparent metal conductive film, a metal reflecting layer and a metal protective layer on the surface of the P-GaN layer; and growing a metal binding layer on the surface of the N-GaN layer.
Preferably, the fourth step comprises: and after the third step is finished, evaporating a DBR Bragg reflector layer on the surface of the DBR flip chip, and etching a P electrode conductive hole and an N electrode conductive hole respectively corresponding to the metal binding layers on the surfaces of the P-GaN layer and the N-GaN layer.
Preferably, the fifth step further comprises: and after the fourth step is completed, growing a current expansion metal layer on the surface of the DBR Bragg reflector layer according to the arrangement of the P electrode conductive holes and the N electrode conductive holes so that the P electrode conductive holes are connected and the N electrode conductive holes are connected.
And preferably, after the fifth step is completed, a sixth step of depositing a SiO2 passivation layer on the surface of the chip, and etching conductive channels of the passivation layer on two sides of the chip according to the appearance of the current spreading metal layer.
Preferably, the method further comprises a seventh step of evaporating P, N an electrode layer on the surface of the chip after the sixth step.
According to the manufacturing method of the DBR flip chip, the plurality of P electrode conductive holes and the plurality of N electrode conductive holes are evenly etched on the surface of the DBR chip and are distributed in a combined manner, the current expansion metal layer is evaporated on the surface of the DBR layer, so that the P electrode conductive holes are respectively connected with the N electrode conductive holes, and the current injected into the P, N electrode is guaranteed to be evenly conducted to the metal reflecting layer and the metal binding layer on the surface of the N-GaN layer through countless small conductive holes after being expanded through the current expansion metal layer, and the problem of uneven current expansion under the high-current condition is solved.
Drawings
FIG. 1 is a schematic structural view of the present invention;
fig. 2 is a top view of fig. 1.
Wherein: 1. a sapphire substrate; 2. a buffer layer; 3. an N-GaN layer; 4. a light emitting quantum well; 5. a P-GaN layer; 6. a TCL transparent metal conductive film; 7. a metal reflective layer; 8. a metal binding layer; 9. a DBR Bragg reflector layer; 10. a current spreading metal layer; 11. a SiO2 passivation layer; 12. p, N electrode layers.
Detailed Description
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
Referring to fig. 1-2, a manufacturing method of a DBR flip chip provided by the present invention includes the following steps: step one, manufacturing an epitaxial layer; specifically, the first step includes: the buffer layer 2, the N-GaN layer 3, the light-emitting quantum well 4 and the P-GaN layer 5 are sequentially grown on the sapphire substrate 1 through MOCVD equipment, and the manufacture of the GaN-based LED epitaxial layer is completed. Etching an N-type step on the epitaxial layer structure to enable the N-GaN to be in an exposed state; step three, respectively growing a reflecting layer and a metal binding layer 8 on the surface of the epitaxial layer; growing a DBR Bragg reflector layer 9 on the DBR flip chip, and respectively etching a P electrode conductive hole and an N electrode conductive hole; and step five, according to the arrangement of the conductive holes, evaporating a current expansion metal layer 10 on the DBR Bragg reflector layer 9 and enabling the P electrode conductive holes and the N electrode conductive holes to be connected respectively. In the embodiment, a plurality of P-electrode conductive holes and N-electrode conductive holes are uniformly etched on the surface of the DBR bragg reflector layer 9, and the conductive holes are arranged in combination, so that the current spreading metal layer 10 is evaporated on the surface of the DBR layer, and the P-electrode conductive holes and the N-electrode conductive holes are respectively connected, thereby ensuring that current injected from the P, N electrode is uniformly conducted to the metal reflecting layer 7 and the metal binding layer 8 on the surface of the N-GaN layer 3 through countless small conductive holes after being spread by the current spreading metal layer 10, and solving the problem of nonuniform current spreading under a high-current condition.
Further, the third step includes: sequentially growing a TCL transparent metal conductive film 6, a metal reflecting layer 7 and a metal protective layer on the surface of the P-GaN layer 5; and (3) growing a metal binding layer 8 on the surface of the N-GaN layer 3, and evaporating a DBR Bragg reflector layer 9 on the surface of the chip after the step three is completed. The DBR flip chip provided by this embodiment uses a metal layer with high reflectivity as the metal reflective layer 7 on the surface of the P-GaN layer 5, and the reflectivity is equivalent to the DBR bragg reflector and combined with the DBR layer, thereby increasing the reflective area to the maximum extent.
In this embodiment, the fourth step includes: and after the third step is finished, evaporating a DBR Bragg reflector layer 9 on the surface of the DBR flip chip, and etching a P electrode conductive hole and an N electrode conductive hole respectively corresponding to the metal binding layers 8 on the surfaces of the P-GaN layer 5 and the N-GaN layer 3, specifically, reasonably processing the P electrode conductive hole and the N electrode conductive hole according to the size of the chip and the current using condition during processing.
Further, the fifth step includes: and after the fourth step is completed, growing a current expansion metal layer 10 on the surface of the DBR Bragg reflector layer 9 according to the arrangement of the P electrode conductive holes and the N electrode conductive holes so that the P electrode conductive holes are connected with each other and the N electrode conductive holes are connected with each other. Step six is also included after the step five is completed, a SiO2 passivation layer 11 is deposited on the surface of the chip, and therefore the chip is protected; and etching a passivation layer conductive channel on two sides of the chip according to the appearance of the current expansion metal layer 10, and evaporating P, N electrode layers 12 on the surface of the chip after the sixth step.
The DBR flip chip manufactured through the steps can guarantee the uniform expansion of current under the high-power service condition of large current, so that the DBR flip chip can be applied to the high-power condition. Meanwhile, a metal layer with high reflectivity is used as the metal reflecting layer 7 on the surface of the P-GaN layer 5, the reflectivity is equivalent to that of a DBR Bragg reflector and is combined with the DBR layer, and therefore the reflecting area is increased to the maximum extent.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and substitutions can be made without departing from the technical principle of the present invention, and these modifications and substitutions should also be regarded as the protection scope of the present invention.
Claims (7)
1. A manufacturing method of a DBR flip chip is characterized by comprising the following steps: step one, manufacturing an epitaxial layer; etching an N-type step on the epitaxial layer structure; respectively growing a reflecting layer and a metal binding layer on the surface of the epitaxial layer, and sequentially growing a TCL transparent metal conductive film, a metal reflecting layer and a metal protective layer on the surface of the P-GaN layer; growing a metal binding layer on the surface of the N-GaN layer; growing a DBR Bragg reflector layer on the DBR flip chip, and respectively etching a P electrode conductive hole and an N electrode conductive hole; and step five, according to the arrangement of the conductive holes, evaporating a current expansion metal layer on the DBR Bragg reflector layer and enabling the P electrode conductive hole and the N electrode conductive hole to be connected respectively.
2. The method for manufacturing the DBR flip chip according to claim 1, wherein the first step comprises: a buffer layer, an N-GaN layer, a light-emitting quantum well and a P-GaN layer are sequentially grown on a sapphire substrate through MOCVD equipment.
3. The method for manufacturing the DBR flip chip of claim 2, wherein the second step comprises: and etching an N-type step on the epitaxial layer and enabling the N-GaN layer to be in an exposed state.
4. The DBR flip chip fabrication method of claim 1, wherein the fourth step comprises: and after the third step is finished, evaporating a DBR Bragg reflector layer on the surface of the DBR flip chip, and etching a P electrode conductive hole and an N electrode conductive hole respectively corresponding to the metal binding layers on the surfaces of the P-GaN layer and the N-GaN layer.
5. The method for manufacturing the DBR flip chip of claim 4, wherein the fifth step comprises: and after the fourth step is completed, growing a current expansion metal layer on the surface of the DBR Bragg reflector layer according to the arrangement of the P electrode conductive holes and the N electrode conductive holes so that the P electrode conductive holes are connected and the N electrode conductive holes are connected.
6. The DBR flip chip manufacturing method of claim 5, further comprising a sixth step of depositing a SiO2 passivation layer on the chip surface after the fifth step, and etching a passivation layer conductive channel on both sides of the chip according to the shape of the current spreading metal layer.
7. The method for manufacturing the DBR flip chip of claim 6, further comprising a seventh step of evaporating P, N an electrode layer on the surface of the chip after the sixth step.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811451640.9A CN109638131B (en) | 2018-11-30 | 2018-11-30 | Manufacturing method of DBR flip chip |
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| CN201811451640.9A CN109638131B (en) | 2018-11-30 | 2018-11-30 | Manufacturing method of DBR flip chip |
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| CN109638131B true CN109638131B (en) | 2020-05-19 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111129256A (en) * | 2019-12-30 | 2020-05-08 | 广东德力光电有限公司 | Silver mirror-based flip high-voltage chip and manufacturing method thereof |
| CN111129244B (en) * | 2019-12-30 | 2022-03-25 | 广东德力光电有限公司 | Silver mirror high-power flip chip and preparation method thereof |
| CN112530802A (en) * | 2020-11-30 | 2021-03-19 | 北京北方华创微电子装备有限公司 | Etching control method |
| CN112951954B (en) * | 2021-01-28 | 2023-03-24 | 湘能华磊光电股份有限公司 | Light-emitting diode chip and manufacturing process thereof |
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| CN102709421B (en) * | 2012-06-21 | 2014-11-05 | 安徽三安光电有限公司 | GaN-based LED with dual reflecting layers |
| CN102868091A (en) * | 2012-09-13 | 2013-01-09 | 北京工业大学 | High-power surface-emitting laser using graphene surface current extension layer |
| US20160329461A1 (en) * | 2015-02-17 | 2016-11-10 | Genesis Photonics Inc. | Light emitting diode |
| CN106025010A (en) * | 2016-07-19 | 2016-10-12 | 厦门乾照光电股份有限公司 | Flip LED chip based on conductive DBR structure and manufacturing method thereof |
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