CN114583025A - Multi-surface type side wall LED chip and preparation method thereof - Google Patents

Multi-surface type side wall LED chip and preparation method thereof Download PDF

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Publication number
CN114583025A
CN114583025A CN202210199465.9A CN202210199465A CN114583025A CN 114583025 A CN114583025 A CN 114583025A CN 202210199465 A CN202210199465 A CN 202210199465A CN 114583025 A CN114583025 A CN 114583025A
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Prior art keywords
mask
led
side wall
etching
substrate
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Pending
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CN202210199465.9A
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Chinese (zh)
Inventor
张亚
张星星
张雪
简弘安
胡加辉
金从龙
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Jiangxi Zhao Chi Semiconductor Co Ltd
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Jiangxi Zhao Chi Semiconductor Co Ltd
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Priority to CN202210199465.9A priority Critical patent/CN114583025A/en
Publication of CN114583025A publication Critical patent/CN114583025A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers

Abstract

The invention provides a multi-surface type side wall LED chip and a preparation method thereof, wherein the preparation method comprises the following steps: providing a substrate, forming an LED epitaxy on the substrate, and depositing materials with different compactness on the LED epitaxy to be used as a mask; forming a photoresist layer with an ISO pattern by ISO photoetching, and etching the mask by taking the photoresist layer as a shield; and removing the photoresist layer, and carrying out ICP (inductively coupled plasma) etching on the LED epitaxy by taking the mask as a shield until the LED epitaxy is etched to the substrate to form an isolation groove with a plurality of inclined planes on the side wall. According to the multi-surface type side wall LED chip and the preparation method thereof, the appearance of the side wall of the isolation groove is changed, so that the light emitting area of the side wall is increased, the incident angle from the light inside the chip to the side wall is changed, more light can be taken out, and the brightness of the chip is improved.

Description

Multi-surface type side wall LED chip and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a multi-surface type side wall LED chip and a preparation method thereof.
Background
Light Emitting Diodes (LEDs) are widely used as a new generation of green Light source in the fields of illumination, backlight, display, indication, etc. The high-voltage LED chip comprises at least two sub-chips which are connected in series, each sub-chip comprises an N-type layer, an active layer and a P-type layer, the high-voltage LED chip has the advantages of high antistatic capacity, high luminous efficiency, packaging factory routing cost saving and the like, and the status in the field of chips is gradually shown.
In order to avoid the occurrence of electric leakage of the side wall of the LED chip, the manufacturing process of an isolation groove mode is adopted for both a normally-installed chip and a flip chip, particularly for a high-voltage chip, the isolation groove is required to be cut to form a partition, and after the isolation groove is etched, the insulating layer is deposited, so that the occurrence of failure caused by the exposure of the side wall light emitting layer is avoided. The shape state of the side wall is important to influence photoelectric performance and reliability.
In the prior art, as shown in fig. 4 and 5, the angle of the sidewall formed by the isolation trench is generally about 30 ° to 80 °, when the angle of the sidewall is too small, the area ratio of the isolation trench is large, the light emitting surface loss is serious, the light emitting efficiency is poor, and when the angle of the sidewall is too large, the coverage is poor, and the insulation effect of the sidewall is affected.
Disclosure of Invention
Accordingly, the present invention is directed to a multi-sided LED chip and a method for fabricating the same, which solves at least one of the problems of poor light emitting efficiency and poor coverage caused by the angle of the sidewall of the isolation trench in the prior art.
The invention provides a multi-face type side wall LED chip, comprising:
providing a substrate, forming an LED epitaxy on the substrate, and depositing materials with different compactness on the LED epitaxy to be used as a mask;
forming a photoresist layer with an ISO pattern by ISO photoetching, and etching the mask by taking the photoresist layer as a shield;
and removing the photoresist layer, and carrying out ICP (inductively coupled plasma) etching on the LED epitaxy by taking the mask as a shield until the LED epitaxy is etched to the substrate to form an isolation groove with a plurality of inclined planes on the side wall.
According to the preparation method of the multi-surface type side wall LED chip, the side wall with a plurality of inclined surfaces is etched by depositing masks made of different compact materials on the LED epitaxy, and the side walls with the inclined surfaces increase the light emitting area, so that the light emitting efficiency is improved; furthermore, the radian change of the side wall formed by the inclined planes can slow down the over-steep angle of the side wall, so that the problem of chip failure caused by poor coating due to over-large angle of a subsequent coating is avoided; simultaneously, a plurality of inclined planes of lateral wall can change the incident angle of the inside light of chip to the lateral wall for more light can be taken out, wholly promote chip luminance, thereby the isolation slot lateral wall angle leads to the poor problem of luminous efficiency and drapability among the background art has been solved. Further, the material of different compactness comprises SiO2、SiNX、TiOXAnd Al2O3One or more of the above materials.
Further, the step of depositing materials with different densities on the LED epitaxy as a mask comprises:
the compactness of the mask is changed by adjusting the manufacturing parameters of the mask material, wherein the manufacturing parameters comprise machine power, cavity pressure, gas flow, temperature and target source.
Furthermore, the compactness of the materials with different compactabilities increases or decreases from bottom to top.
Furthermore, the thickness of the mask is 0.5um-4 um.
Furthermore, in the process of etching the mask by taking the photoresist layer as a shield, the etching method comprises any one of dry etching or wet etching.
The invention also provides a multi-surface type side wall LED chip which sequentially comprises a substrate and an LED extension from bottom to top.
Drawings
FIG. 1 is a schematic cross-sectional view of a multi-sided sidewall LED chip according to an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view of a two-sided sidewall isolation trench in accordance with an embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view of a multi-sided sidewall isolation trench in accordance with an embodiment of the present invention;
FIG. 4 is a comparison of a multi-sided sidewall LED chip of the present invention with a prior art 80 degree sidewall;
FIG. 5 is a comparison of a multi-sided sidewall LED chip of the present invention with a prior art 30 degree sidewall;
fig. 6 is a schematic structural diagram of a multi-sided sidewall LED front chip in an embodiment of the invention.
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Description of the main element symbols:
substrate 1 Multi-sided side wall 11
LED epitaxy 2 CBL current blocking layer 5
First semiconductor mesa 3 TCL Current spreading layer 6
Electrode layer 7 Reflective layer 8
Bonding pad layer 9 Two-sided side wall 10
Passivation layer 12
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Several embodiments of the invention are presented in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Example one
In this embodiment, a method for manufacturing a multi-sided LED chip is provided, as shown in fig. 1, the method for manufacturing an LED chip according to the present embodiment includes:
and S1, providing a substrate 1, and growing a first semiconductor layer, a light-emitting layer and a second semiconductor layer on the substrate 1 in sequence to form the LED epitaxy 2. The Mesa graph is manufactured on the LED epitaxy 2 by using photoresist, and a first semiconductor layer of the LED epitaxy 2 is etched to form a first semiconductor Mesa 3.
And S2, depositing masks made of materials with different densities on the LED epitaxy.
The first semiconductor layer and the second semiconductor layer on the LED epitaxy 2 are deposited with materials with different compactness as masks through PECVD (plasma enhanced chemical vapor deposition), and the thickness of the masks is 0.5-4 um. Wherein, the mask composed of materials with different compactedness is formed by adjusting the manufacturing parameters or combining the materials with different compactedness. The manufacturing parameters comprise machine power, cavity pressure, gas flow, temperature and target source, and the manufacturing material comprises SiO2、SiNX、TiOXAnd Al2O3One or more of the above materials. The mask is different in etching rate due to different compactness of the upper component and the lower component, when the material is higher in compactness, the etching is more difficult to etch, the etching speed is lower, the compact material is smaller, the etching speed is high, the angle of the formed side wall is smaller, and therefore the side wall of the isolation groove can gradually form a plurality of inclined planes and angles. When the compactness of the mask changes more, more slopes of the ISO isolation trench sidewalls occur until curved sidewalls occur.
The preparation process of the deposition mask comprises the following steps:
deposition of SiO with different densification on LED epitaxy 22The mask may be a PECVD process that places the epitaxy to be deposited into the process chamber. In the deposition step, the chamber pressure is 120Pa, the deposition power of the machine is 90W, and the reaction gas is N2O、SiH4The carrier gas is N2The gas flow during deposition is N2O1180sccm、SiH4110sccm (content: 5%) and the machine temperature is 230 ℃. The densification can be improved by raising the corresponding deposition temperature to 260 ℃, 290 ℃, or raising the deposition power to 110W and 130W.
The above manufacturing parameters can be changed singly or simultaneously. As shown in fig. 2, two masks of different compactness materials are obtained by adjusting the manufacturing parameters or materials of the masks, and then an isolation trench with a two-sided sidewall 10 is obtained by etching, wherein the sidewall is composed of two inclined planes; as shown in fig. 3, by adjusting the manufacturing parameters or materials of the mask, masks of more than two kinds of dense materials are obtained, and then the side wall with the multi-surface type side wall 11 is obtained after etching, and the side wall is composed of a plurality of sections of inclined surfaces.
As the difference in mask material densification increases, the sidewalls of the ISO isolation trench will be sloped at more angles. As more bevels are present, the side wall will assume an arc shape. As shown in fig. 5, when the angle of the side wall inclined plane is 30 degrees in the prior art, the light emitting area is smaller, and by adding a plurality of inclined planes and a plurality of angles in the embodiment, the larger the area of the side wall is, the more the light is emitted from the side surface, and the gradient of the plurality of inclined planes on the side wall will not affect the subsequent coating process. As shown in fig. 4, when the angle of the sidewall slope in the prior art is 80 degrees, the sidewall slope is steeper, and thus the drapability is not good, and in this embodiment, by adding a plurality of slopes, the sidewall is finally formed into a radian, so that the too steep angle of the sidewall can be reduced, thereby avoiding the failure of the chip caused by the bad coverage due to the too large angle during the subsequent plating. The more the inclined plane, the more the angle of the internal light incident on the plane changes, the total reflection can be reduced, more light can be taken out, the light extraction rate can be increased, and the light emitting brightness of the LED is improved.
The compactness of the mask materials is different from bottom to top, the mask materials with different compactness form different inclined planes after etching, and the effects of increasing the light-emitting area of the side wall, slowing down the steep form of the inclined plane of the side wall and improving the subsequent coating are achieved. Preferably, the compactness of the mask material can be sequentially increased from top to bottom or sequentially decreased, when the compactness of the mask material is sequentially increased, the isolation trench etched on the side wall is in an outer eight-shaped angle, and when the compactness is sequentially decreased, the isolation trench etched on the side wall is in an inverted eight-shaped angle.
S3, coating glue on the mask, exposing, developing to make ISO pattern, etching (wet etching) SiO by BOE2When masking, a plurality of inclined planes are formed on the side surface, and the photoresist layer with the ISO pattern is obtained. And taking the photoresist layer with the ISO graph as a shield, etching the mask, and removing part of the mask until the substrate 1 is exposed by etching. And the etching mode is dry etching or wet etching, and the mask pattern is equally transferred to the side wall of the ISO isolation groove after etching, so that the isolation groove with the side wall provided with a plurality of inclined planes is finally obtained.
S4, depositing SiO on LED epitaxy2And making a CBL current blocking layer 5 pattern to form the CBL current blocking layer 5. The material used for the CBL current blocking layer 5 in the embodiments provided by the present invention may be SiO2、Al2O3、TiOXAnd the like, and one or more non-conductive substances.
And S5, depositing a TCL transparent conductive layer on the LED epitaxy, and making a TCL pattern to form the TCL conductive layer. The TCL transparent conductive layer in the embodiment of the invention may be ITO, IZO, or other transparent conductive materials.
S6, performing Metal layer photoetching, and performing first electrode and second electrode deposition; and removing the photoresist after Metal photoetching. The metal material used for the electrode bottom layer in the embodiment provided by the invention can be a laminated layer consisting of one or more of metals such as Cr, Au, Pt, Ni, Ti, Al, Ag, Mg and the like or alloys thereof.
S7, depositing the DBR layer of the Bragg reflection layer 8, making a DBR pattern, and etching to expose the Metal layer. The material used for the DBR layer in the embodiment provided by the present invention may be the bragg reflective layer 8 composed of two of SiO2, TiOx, and Al2O3 alternately.
The DBR layer covers all regions except the contact holes of the P electrode and the N electrode, and plays a role in insulation reflection. The isolation groove with the ISO multi-angle manufactured by S3 is covered, so that the leakage of the side wall during die bonding is effectively avoided, and the insulation protection effect is achieved in the isolation groove.
S8, performing binding layer photoetching by using the photoresist, and depositing binding; and removing the photoresist after the Bonding photoetching to form a Bonding layer. In the embodiment provided by the invention, the metal material used for the Bonding bottom layer can be a laminated layer composed of one or more of metals such as Cr, Au, Pt, Ni, Ti, Al, Ag, Mg, and the like.
In summary, in the method for manufacturing the multi-surface type side wall LED chip in the above embodiment of the invention, the masks made of different dense materials are deposited on the LED epitaxy, so as to etch the side wall with the plurality of slopes, and the side walls with the plurality of slopes increase the light emitting area, thereby improving the light emitting efficiency; furthermore, the side wall formed by the inclined planes presents radian change, so that the over-steep angle of the side wall can be relieved, and the problem that the chip fails due to poor coating caused by over-large angle of a subsequent coating is solved; simultaneously, a plurality of inclined planes of lateral wall can change the incident angle of the inside light of chip to the lateral wall for more light can be taken out, and whole promotion chip luminance, thereby at least one problem in the isolation slot lateral wall angle leads to luminous efficiency poor and drapability poor among the background art has been solved.
Example two
The embodiment provides a method for manufacturing a multi-sided side-wall LED chip, which is different from the first embodiment in that a manufacturing process of depositing a mask is provided in the embodiment, and the compactness of the mask is changed by changing a material for manufacturing the mask.
The preparation process comprises the following steps: and placing the epitaxy to be deposited into the operation cavity by adopting a PECVD method. In the deposition step, the mask material comprises SiNXThe pressure of the chamber can be 120Pa, the deposition power of the machine is 90W, and the reaction gas is NH3、SiH4The carrier gas is N2The gas flow during deposition is respectively NH3 13sccm、SiH4270sccm (content: 5%) and a machine temperature of 230 ℃. If the mask compactness needs to be improved, the corresponding NH can be added3The gas flow is respectively promoted to 17sccm,21 sccm; the deposition power can also be raised to 110W, 130W.
In summary, in the method for manufacturing the multi-surface type side wall LED chip in the above embodiment of the invention, the masks made of different dense materials are deposited on the LED epitaxy, so as to etch the side wall with the plurality of slopes, and the side walls with the plurality of slopes increase the light emitting area, thereby improving the light emitting efficiency; furthermore, the side wall formed by the inclined planes presents radian change, so that the over-steep angle of the side wall can be relieved, and the problem that the chip fails due to poor coating caused by over-large angle of a subsequent coating is solved; simultaneously, a plurality of inclined planes of lateral wall can change the incident angle of the inside light of chip to the lateral wall for more light can be taken out, and whole promotion chip luminance, thereby at least one problem in the isolation slot lateral wall angle leads to luminous efficiency poor and drapability poor among the background art has been solved.
EXAMPLE III
The embodiment provides a method for preparing a multi-sided side wall LED chip, which is different from the first embodiment in that another mask deposition preparation process is provided in the embodiment, the mask is prepared by depositing multiple materials, and the mask material in the embodiment comprises SiO2And SiNXThe preparation process comprises the following steps: and placing the epitaxy to be deposited into the operation cavity by adopting a PECVD method. In the deposition step, the chamber pressure may be 120Pa, the deposition power of the machine is 90W, and the reaction gas is N2O、NH3、SiH4The carrier gas is N2The gas flow during deposition is N2O 1180sccm、SiH4110sccm (content: 5%), NH3 13sccm、SiH4270sccm, the tool temperature is 230 ℃.
In summary, in the method for manufacturing the multi-surface type side wall LED chip in the above embodiment of the invention, the masks made of different dense materials are deposited on the LED epitaxy, so as to etch the side wall with the plurality of slopes, and the side walls with the plurality of slopes increase the light emitting area, thereby improving the light emitting efficiency; furthermore, the side wall formed by the inclined planes presents radian change, so that the over-steep angle of the side wall can be relieved, and the problem that the chip fails due to poor coating caused by over-large angle of a subsequent coating is solved; simultaneously, a plurality of inclined planes of lateral wall can change the incident angle of the inside light of chip to the lateral wall for more light can be taken out, and whole promotion chip luminance, thereby at least one problem in the isolation slot lateral wall angle leads to luminous efficiency poor and drapability poor among the background art has been solved.
Example four
In this embodiment, a multi-surface type side wall LED chip is provided, as shown in fig. 1, the multi-surface type side wall LED chip sequentially includes a substrate 1 and an LED extension 2 from bottom to top, the LED extension 2 sequentially includes a first semiconductor layer, a light emitting layer, and a second semiconductor layer from bottom to top, an upward opening of the LED extension 2 is provided with an isolation trench, and the bottom of the isolation trench exposes out of the substrate 1. The sidewall of the isolation trench has a plurality of slopes, and the more slopes on the sidewall, the closer the sidewall will be to an arc shape.
In this embodiment, the first semiconductor layer includes a first semiconductor mesa 3, the CBL current blocking layer 5 is disposed on the first semiconductor mesa 3, and the TCL current spreading layer 6, the electrode layer 7, the reflective layer 8, and the Bonding pad layer 9 are sequentially disposed on the second semiconductor layer.
As shown in fig. 5, when the angle of the side wall inclined plane is 30 degrees in the prior art, the light emitting area is smaller, and by adding a plurality of inclined planes and a plurality of angles in the embodiment, the larger the area of the side wall is, the more the light is emitted from the side surface, and the gradient of the plurality of inclined planes on the side wall will not affect the subsequent coating process. As shown in fig. 4, when the angle of the sidewall slope in the prior art is 80 degrees, the sidewall slope is steeper, and thus the drapability is not good, and in this embodiment, by adding a plurality of slopes, the sidewall is finally formed into a radian, so that the too steep angle of the sidewall can be reduced, thereby avoiding the failure of the chip caused by the bad coverage due to the too large angle during the subsequent plating. The more the inclined plane, the more the angle of the internal light incident on the plane changes, the total reflection can be reduced, more light can be taken out, the light extraction rate can be increased, and the light emitting brightness of the LED is improved.
The structure is a flip-chip LED chip structure, in some other optional embodiments, the multi-sided sidewall LED chip may also be a front-mounted LED chip, as shown in fig. 6, the multi-sided sidewall LED chip includes, from bottom to top, an LED extension 2 on a substrate 1, and a CBL current blocking layer 5, a TCL current spreading layer 6, an electrode layer 7 and a passivation layer 12 on the LED extension 2, wherein a sidewall of an isolation trench on the chip extension layer is composed of a plurality of slopes. When the inclined surfaces on the side walls are more, the side walls are closer to an arc shape, and the effect is the same as that of the flip LED chip.
In summary, in the multi-surface-type sidewall LED chip in the above embodiments of the invention, the sidewall having the plurality of slopes is disposed on the LED extension, and the sidewalls of the plurality of slopes increase the light emitting area, thereby improving the light emitting efficiency; furthermore, the side wall formed by the inclined planes presents radian change, so that the over-steep angle of the side wall can be relieved, and the problem that the chip fails due to poor coating caused by over-large angle of a subsequent coating is solved; simultaneously, a plurality of inclined planes of lateral wall can change the incident angle of the inside light of chip to the lateral wall for more light can be taken out, and whole promotion chip luminance, thereby at least one problem in the isolation slot lateral wall angle leads to luminous efficiency poor and drapability poor among the background art has been solved.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (7)

1. A method for preparing a multi-sided side-wall LED chip is characterized by comprising the following steps:
providing a substrate, forming an LED epitaxy on the substrate, and depositing materials with different compactness on the LED epitaxy to be used as a mask;
forming a photoresist layer with an ISO pattern by ISO photoetching, and etching the mask by taking the photoresist layer as a shield;
and removing the photoresist layer, and carrying out ICP (inductively coupled plasma) etching on the LED epitaxy by taking the mask as a shield until the LED epitaxy is etched to the substrate to form an isolation groove with a plurality of inclined planes on the side wall.
2. The method of claim 1, wherein the material of different densification comprises SiO2、SiNX、TiOXAnd Al2O3One or more of the above materials.
3. The method of claim 1, wherein the step of depositing materials of different densities as masks on the LED epitaxy comprises:
and changing the compactness of the mask by adjusting the manufacturing parameters of the mask material, wherein the manufacturing parameters comprise machine power, cavity pressure, gas flow, temperature and target source.
4. The method of claim 1, wherein the densification of the materials with different densification degrees gradually increases or decreases from bottom to top.
5. The method of claim 1, wherein the mask has a thickness of 0.5um to 4 um.
6. The method for preparing the multi-sided LED chip, according to claim 1, wherein in the step of etching the mask by using the photoresist layer as a mask, the etching method comprises any one of dry etching or wet etching.
7. The utility model provides a multiaspect formula lateral wall LED chip, is extended by lower supreme substrate and LED that includes in proper order, its characterized in that, the LED is extended to open the top and is equipped with isolation trench, isolation trench's bottom is revealed the substrate, just isolation trench's lateral wall has a plurality of inclined planes.
CN202210199465.9A 2022-03-01 2022-03-01 Multi-surface type side wall LED chip and preparation method thereof Pending CN114583025A (en)

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Application Number Priority Date Filing Date Title
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CN114583025A true CN114583025A (en) 2022-06-03

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