TWI599017B - Light emitting diode array on wafer level and method of forming the same - Google Patents

Description

Wafer grade light emitting diode array and manufacturing method thereof

The present invention relates to an array of light-emitting diodes, and more particularly to a light-emitting diode array having a plurality of light-emitting diodes connected via wires and formed into a flip chip type, and a method of forming the same.

The light-emitting diode is an element that performs a light-emitting operation when a turn-on voltage or a higher voltage is applied to the anode terminal and the cathode terminal. Generally, the value of the turn-on voltage used to illuminate the light-emitting diode is much lower than the voltage of a general power source. Therefore, the disadvantage of the light-emitting diode is that it cannot be used directly under a general AC power source of 110V or 220V. The operation of a light-emitting diode using a general AC power source requires a voltage converter for reducing the supplied AC voltage. Therefore, it is necessary to provide a driving circuit for a light-emitting diode which becomes a factor that causes an increase in manufacturing cost of a lighting device including a light-emitting diode. Since a separate drive circuit should be provided, the volume of the illumination device is increased and unnecessary heat is generated. In addition, there is a problem such as an improvement in the power factor of the supplied power source.

In order to use a general AC power source in a state in which a separate voltage conversion tool is excluded, there has been a method of forming an array by connecting a plurality of light-emitting diode wafers in series with each other. In order to realize the use of the light-emitting diodes as an array, the light-emitting diode wafers should be formed into individual packages. Therefore, a substrate separation process, a package process for a separate light-emitting diode wafer, and the like are required, and additionally, a load process of arranging a package on the array substrate and wiring processing for forming a wire between the electrodes of the package are required. . Therefore, there is a problem that the processing time constituting the array increases and the manufacturing cost of the array increases.

Further, wire bonding is performed using wire bonding to form an array, and a molding layer for protecting the bonding wires is additionally formed on the entire surface of the array. Therefore, there is a problem of a molding process which additionally requires the formation of a mold layer, thus increasing the complexity of the process. In particular, in the case of applying a wafer type having a lateral structure, the light-emitting efficiency of the light-emitting diode wafer is lowered due to the generation of heat, and the quality of the light-emitting diode is deteriorated.

In order to solve the above-mentioned problems, proposals have been made to manufacture a light-emitting diode wafer array including a plurality of light-emitting diode wafers in an array as a single package.

In the Korean Patent Laid-Open Publication No. 2007-0035745, a plurality of lateral-type light-emitting diode wafers are electrically connected to each other via a metal wire formed using an air bridge process on a single substrate. According to this patent publication, there is an advantage that separate packaging processing is not required for each of the individual wafers, and the array is formed at the wafer level. However, the empty bridge connection structure causes weak durability, and the lateral type causes a problem of deterioration in luminous efficiency or heat dissipation efficiency.

In U.S. Patent No. 6,573,537, a plurality of flip-chip light-emitting diodes are formed on a single substrate. However, the n-type and p-type electrodes of each of the light-emitting diodes are exposed in a state in which the n-type and p-type electrodes are separated from each other. Therefore, in order to use a single power source, wiring processing in which a plurality of electrodes are connected to each other should be added. To this end, a submount substrate is used in the U.S. patent. That is, in order to wire between the electrodes, the flip-chip type light emitting diode should be mounted on the separated sub-mount substrate. At least two electrodes for electrically connecting to another substrate should be formed on the back surface of the sub-substrate. In this U.S. patent, there is an advantage of improving the luminous efficacy and heat dissipation efficiency due to the use of a flip-chip type light emitting diode. Conversely, the use of a sub-substrate causes an increase in both the thickness of the final product and the manufacturing cost. Further, there is a disadvantage in that it requires additional wiring processing for the sub-substrate and additional processing for loading the sub-substrate on a new substrate.

Korean Patent Laid-Open Publication No. 2008-0002161 discloses an arrangement in which flip-chip type light-emitting diodes are connected in series to each other. According to this patent publication, the encapsulation process on the wafer substrate is not required, and the use of the flip-chip type light-emitting diode exhibits an effect of improving luminous efficacy and heat dissipation efficiency. However, in addition to the wiring between the n-type and p-type semiconductor layers, a separate reflective layer is used, and an interconnection wiring is used on the n-type electrode. Therefore, a plurality of patterned metal layers should be formed. For this reason, many types of masks should be used, which is a problem. Further, detachment or cracking occurs due to a difference in thermal diffusion coefficient between the n-type electrode and the interconnection electrode or the like, and thus there is a problem that the electrical connection between them is open.

It is an object of the present invention to provide a flip-chip type light emitting diode array having an improved structure and a method of forming the same.

Another object of the present invention is to provide an array of light-emitting diodes and a method of forming the same, which can be used without any sub-substrate.

Still another object of the present invention is to provide a flip-chip type light-emitting diode array and a method of forming the same, which can be used in addition to wires for connecting a plurality of light-emitting diodes, A separate reflective metal layer may not be used to prevent light loss.

It is still another object of the present invention to provide an array of light-emitting diodes and a method of forming the same, which can improve light extraction efficiency by reducing optical loss.

Other features and advantages of the invention will be apparent from the

A light emitting diode array according to an aspect of the present invention includes: a growth substrate; a plurality of light emitting diodes disposed on the substrate, wherein each of the plurality of light emitting diodes has a first semiconductor layer, an active layer, and a second semiconductor layer; and a plurality of upper electrodes disposed on the plurality of light emitting diodes and formed of the same material, wherein each of the plurality of upper electrodes is electrically connected to a corresponding one of the light emitting diodes The first semiconductor layer. At least one of the upper electrodes is electrically connected to the second semiconductor layer adjacent to one of the light emitting diodes, and the other of the upper electrodes is adjacent to the one of the light emitting diodes Two semiconductor layers are insulated.

Therefore, it is possible to provide a flip-chip type light-emitting diode array which can be driven at a high voltage without using any sub-substrate and to simplify the formation process thereof.

The upper electrode may include an ohmic contact layer in ohmic contact with the first semiconductor layer. Since the upper electrode includes an ohmic contact layer, it is not necessary to form the ohmic contact layer and the upper electrode by using individual masks, and thus the formation process can be more simplified.

The ohmic contact layer may include a metal material of Cr, Ni, Ti, Rh, or Al, or ITO.

The upper electrode may include a reflective conductor layer. The reflective conductor layer can be on the ohmic contact layer. The reflective conductor layer may include Al, Ag, Rh, or Pt. Further, the upper electrode may further include a barrier layer for protecting the reflective conductor layer. The barrier layer may be formed in a single layer or a multilayer structure and has a thickness of 300 nm to 5000 nm.

The light emitting diode array may further include a first interlayer insulating layer disposed between the light emitting diode and the upper electrode. The upper electrode may be insulated from the side surface of the light emitting diode by the first interlayer insulating layer. The first interlayer insulating layer may cover a side surface of the light emitting diode and a region between the light emitting diodes. The upper electrode may be located on the first interlayer insulating layer and may cover a large portion of the area between the light emitting diodes. In the conventional case of using a linear wire, the wire hardly covers the area between the light-emitting diodes. Conversely, the upper electrode may cover at least 30%, at least 50%, or even at least 90% of the area between the light emitting diodes. However, since the upper electrodes are separated from each other, the upper electrode covers a region between the light emitting diodes of less than 100%.

In order to reduce the impedance caused by the upper electrode, the upper electrode may be formed to have Relatively large area. Therefore, it is possible to promote current distribution and reduce the forward voltage of the light emitting diode array.

Further, the upper electrode may constitute an omni-directional reflector together with the first interlayer insulating layer. Alternatively, the first interlayer insulating layer may include a distributed Bragg reflector. Therefore, an omnidirectional reflector or a distributed Bragg reflector can further enhance the reflectance of light.

The light emitting diode array may further include a lower electrode respectively disposed on the second semiconductor layer of the light emitting diode. The first interlayer insulating layer may expose a portion of the lower electrode on each of the light emitting diodes. The upper electrode electrically connected to the second semiconductor layer adjacent to the light emitting diode may be connected to the exposed portion of the lower electrode via the first interlayer insulating layer. Each of the lower electrodes may include a reflective layer.

The light emitting diode array may further include a second interlayer insulating layer covering the upper electrode. The second interlayer insulating layer may expose one of the lower electrodes and the upper semiconductor layer adjacent to the light emitting diodes.

Furthermore, the light emitting diodes can be connected in series by the upper electrodes. Meanwhile, the second interlayer insulating layer may expose the lower electrode and the upper electrode corresponding to the light emitting diode at both ends of the LEDs connected in series.

The LED array may further include a first pad and a second pad on the second interlayer insulating layer. The first pad may be connected to the lower electrode exposed through the second interlayer insulating layer, and the second pad may be connected to the upper electrode exposed via the second interlayer insulating layer. Therefore, it is possible to provide a flip-chip type light-emitting diode array that can be mounted on a printed circuit board or the like using the first pad and the second pad.

In some embodiments, each of the light emitting diodes can have a via hole that exposes the first semiconductor layer through the second semiconductor layer and the active layer. Each of the upper electrodes may be connected to a first semiconductor layer of a corresponding one of the light emitting diodes via a via.

At the same time, the upper electrode can occupy at least 30% and less than 100% of the overall area of the array of light emitting diodes.

Each of the upper electrodes may be in the form of a plate or sheet having a breadth to width in the range of 1:3 to 3:1. Unlike conventional linear wires, since the upper electrode is in the form of a plate or a sheet, it is possible to promote current distribution and reduce the forward voltage of the light emitting diode array.

The breadth or width of at least one of the upper electrodes may be greater than the breadth or width of a corresponding one of the light emitting diodes. Therefore, the upper electrode can cover a region between the light emitting diodes, and can reflect light generated in the active layer toward the substrate.

A method of forming a light emitting diode array according to another aspect of the present invention includes forming a plurality of light emitting diodes, wherein each of the plurality of light emitting diodes has a first semiconductor layer on a growth substrate, and an active a layer and a second semiconductor layer. Each of the plurality of light emitting diodes has a first semiconductor layer exposed by removing the second semiconductor layer and the active layer. Thereafter, a first interlayer insulating layer for covering the light emitting diode is formed. The first interlayer insulating layer exposes the exposed first semiconductor layer and has openings on the second semiconductor layer of each of the light emitting diodes. Further, a plurality of upper electrodes are formed of the same material on the first interlayer insulating layer. Each of the upper electrodes is connected to a first semiconductor layer of a corresponding one of the light emitting diodes. Furthermore, in the upper electrode At least one of the first interlayer insulating layer is electrically connected to the second semiconductor layer adjacent to one of the light emitting diodes, and the other of the upper electrodes and the adjacent one of the light emitting diodes The second semiconductor insulation.

Therefore, it is possible to form a flip-chip type light-emitting diode array which can electrically connect the light-emitting diodes using the upper electrode. Therefore, it is not necessary to use a sub-substrate. The upper electrode may include an ohmic contact layer, and thus it is not necessary to form a separate ohmic contact layer on the first semiconductor layer of each of the light emitting diodes.

Further, each of the upper electrodes may include a reflective conductor layer. Since the upper electrode includes a reflective conductor layer, it is possible to reduce the light loss of the light emitting diode array.

The above method may further include forming a second interlayer insulating layer on the upper electrode. The second interlayer insulating layer may expose one of the lower electrodes and other upper electrodes insulated from the second semiconductor layer of the adjacent light emitting diode.

The above method may further include forming a first pad and a second pad on the second interlayer insulating layer. The first pad can be connected to the lower electrode and the second pad can be connected to the upper electrode.

Meanwhile, the above method may further include cutting the growth substrate into individual units. The upper electrode occupies at least 30% and less than 100% of the area of the array of light emitting diodes of each of the individual cells that are cut.

In some embodiments, the first interlayer insulating layer can be formed as a distributed Bragg reflector. In other embodiments, the first interlayer insulating layer may form an omnidirectional reflector together with the upper electrode.

According to an embodiment of the present invention, it is possible to provide a flip-chip type light emitting diode array having an improved structure. In particular, it is possible to provide wafer level LED arrays that can be driven at high voltages. In addition, the array of light emitting diodes may not require a submount substrate. Since the upper electrode may include an ohmic contact layer, it does not need to form a separate ohmic contact layer.

Further, the upper electrode includes a reflective conductor layer. In addition, since the upper electrode covers most of the area between the side of the light-emitting diode and the light-emitting diode, the upper electrode can be used to reflect light. Therefore, it is possible to reduce the loss of light generated in the region between the light emitting diodes. Further, apart from the upper electrode (wire), it is not necessary to additionally form a separate reflective metal layer for reflecting light.

Furthermore, the upper electrode is fabricated in the form of a plate or sheet having a wide area, thereby improving current distribution efficiency and reducing forward voltage at the same current when the same number of light-emitting diodes are used.

Moreover, since the first pads and the second pads occupy a relatively large area, it is possible to simply and stably mount the array of light emitting diodes on a printed circuit board or the like.

100‧‧‧Substrate

110, 111, 112, 113, 114‧‧‧ first semiconductor layer

120, 121, 122, 123, 124‧‧‧ active layers

130, 131, 132, 133, 134‧‧‧ second semiconductor layer

140‧‧‧layer window

151, 152, 153, 154‧‧‧ lower electrode

161, 162, 163, 164, 301~310, 401~408‧‧‧ unit area

170‧‧‧First interlayer insulation

180a‧‧‧ohm contact layer

180b‧‧‧reflective conductor layer

180c‧‧‧Barrier layer

181, 182, 183, 184, 185, 186, 187, 188, 189, 189' ‧ ‧ upper electrode

190‧‧‧Second interlayer insulation

210, 320, 410, 220, 330, 420‧‧‧ pads

A1-A2, B1-B2, C1-C1, D1-D2, E1-E2‧‧‧ lines

D1~D10‧‧‧Light Emitting Diode

L‧‧‧Light

V+‧‧‧ positive voltage

V-‧‧‧negative voltage

1 and 2 are a plan view and a cross-sectional view showing the formation of a plurality of via holes in a laminated structure according to an embodiment of the present invention.

3 and 4 are diagrams showing the formation of a lower electrode on the second semiconductor layer of FIG. Surface and cross-section.

Fig. 5 is a plan view showing a state in which the unit regions are separated from the structure of Fig. 3.

Figure 6 is a cross-sectional view taken along line A1-A2 in the plan view of Figure 5.

Figure 7 is a perspective view of the structure in the plan view of Figure 5.

8 is a plan view showing formation of a first interlayer insulating layer on the entire surface of the structure of FIGS. 5 to 7, and exposing portions of the first semiconductor layer and the lower electrode in each of the unit regions.

9 to 12 are cross-sectional views taken along a specific line in the plan view of Fig. 8.

Figure 13 is a plan view showing the formation of an upper electrode on the structure shown in Figures 8 to 12 .

14 to 17 are cross-sectional views taken along a specific line in the plan view of Fig. 13.

Figure 18 is a perspective view of the structure in the plan view of Figure 13.

Figure 19 is an equivalent circuit diagram obtained by modeling the structures of Figures 13 through 18 in accordance with an embodiment of the present invention.

20 is a plan view showing application of a second interlayer insulating layer on the entire surface of the structure of FIG. 13, a portion of the first electrode in the first cell region is exposed, and a fourth lower electrode in the fourth cell region Part of it is exposed.

21 to 24 are cross-sectional views taken along a specific line in the plan view of Fig. 20.

Figure 25 is a plan view showing the formation of a first pad and a second pad in the structure of Figure 20;

26 to 29 are cross-sectional views taken along a specific line in the plan view of Fig. 25.

Figure 30 is a perspective view taken along line C2-C3 in the plan view of Figure 25.

Figure 31 is a circuit diagram obtained by modeling a connection of ten light-emitting diodes connected in series according to an embodiment of the present invention.

32 is a circuit diagram obtained by modeling an array of light-emitting diodes connected in series/parallel according to an embodiment of the present invention.

Hereinafter, in order to more fully describe the present invention, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments, but may be implemented in other forms.

In these embodiments, it will be understood that the terms "first," "second," "third," or similar terms do not impose any limitation on the component, but are merely used to distinguish components.

1 and 2 are a plan view and a cross-sectional view showing the formation of a plurality of via holes in a laminated structure according to an embodiment of the present invention.

In particular, Figure 2 is a cross-sectional view taken along line A1-A2 of the plan view of Figure 1.

Referring to FIGS. 1 and 2 , a first semiconductor layer 110 , an active layer 120 , and a second semiconductor layer 130 are formed on the substrate 100 , and the vias 140 are formed such that the surface of the semiconductor layer 110 passes through the vias 140 . And exposed.

The substrate 100 includes a material such as sapphire, tantalum carbide or GaN. Any material may be used for the substrate 100 as long as it promotes the growth of a film to be formed on the substrate 100. The first semiconductor layer 110 may have n-type conductivity. Active layer 120 There may be a plurality of quantum well structures, and a second semiconductor layer 130 is formed on the active layer 120. When the first semiconductor layer 110 has n-type conductivity, the second semiconductor layer 130 has p-type conductivity. A buffer layer (not shown) may be further formed between the substrate 100 and the first semiconductor layer 110 to promote single crystal growth of the first semiconductor layer 110.

Next, the structure formed up to the second semiconductor layer 130 is selectively etched, and a plurality of via holes 140 are formed. The lower portion of the first semiconductor layer 110 is exposed through the via hole 140. The vias 140 can be formed by conventional etching processes. For example, the photoresist is coated and then a portion of the photoresist on the region where the via is to be formed is removed via a conventional patterning process to form a photoresist pattern. Thereafter, an etching process is performed by using a photoresist pattern as an etching mask. An etching process is performed until a portion of the first semiconductor layer 110 is exposed. After the etching process, the remaining photoresist pattern is removed.

The shape and number of the vias 140 can be varied variously.

3 and 4 are a plan view and a cross-sectional view showing the formation of a lower electrode on the second semiconductor layer of Fig. 1. In particular, Figure 4 is a cross-sectional view of the plan view of Figure 3 taken along line A1-A2.

Referring to FIG. 3 and FIG. 4, the lower electrodes 151, 152, 153 and 154 are formed in the region except the via hole 140, and a plurality of cell regions 161 can be defined by forming the lower electrodes 151, 152, 153 and 154, 162, 163 and 164. The lower electrodes 151, 152, 153, and 154 can be formed by using a lift-off process used after forming the metal electrodes. For example, a photoresist is formed in a separate region other than the dummy cell regions 161, 162, 163, and 164 and in a region formed by the via hole 140, and then A known thermal deposition or similar treatment forms a metal layer. Next, the photoresist is removed to form the lower electrodes 151, 152, 153, and 154 on the second semiconductor layer 130. Any material may be employed for the lower electrodes 151, 152, 153, and 154 as long as it is a metal material capable of ohmic contact with the second semiconductor layer 130. The lower electrodes 151, 152, 153, and 154 may include a reflective layer of a material such as Al, Ag, Rh, or Pt. For example, the lower electrodes 151, 152, 153, and 154 may include Ni, Cr, or Ti, and may be composed of a composite metal layer of Ti/Al/Ni/Au.

In FIGS. 3 and 4, the regions in which the four lower electrodes 151, 152, 153, and 154 are formed define four unit regions 161, 162, 163, and 164, respectively. The second semiconductor layer 130 is exposed in a gap between the cell regions 161, 162, 163, and 164. The number of cell regions may correspond to the number of light emitting diodes to be formed included in the array. Therefore, the number of unit areas can be varied variously.

Although FIG. 4 shows that the lower electrodes 151, 152, 153 or 154 are separated in the same unit region 161, 162, 163 or 164, this is a phenomenon occurring in the line A1-A2 across the via hole 140. As can be seen in Figure 3, the regions of the lower electrodes 151, 152, 153 or 154 formed in the same cell region 161, 162, 163 or 164 are substantially continuous. Therefore, even if the via hole 140 is formed therein, the lower electrode 151, 152, 153 or 154 formed in the same cell region is still in an electrically short-circuited state.

Figure 5 is a plan view showing a state in which the unit regions are separated with respect to the structure of Figure 3, Figure 6 is a cross-sectional view taken along line A1-A2 in the plan view of Figure 5, and Figure 7 is in the plan view of Figure 5 Perspective view of the structure.

Referring to FIGS. 5, 6, and 7, a mesa etching region is formed via mesa etching for a gap between the four unit regions 161, 162, 163, and 164. Substrate 100 is exposed to a mesa etched region formed via mesa etching. Therefore, the four unit regions 161, 162, 163, and 164 are completely electrically separated from each other. If a buffer layer is interposed between the substrate 100 of FIGS. 1 to 4 and the first semiconductor layer 110, the buffer layer can be retained even in the separation process of the cell regions 161, 162, 163, and 164. However, in order to completely separate the cell regions 161, 162, 163, and 164 from each other, the buffer layer between adjacent ones of the cell regions 161, 162, 163, and 164 may be removed via mesa etching.

With the separation process between adjacent ones of the cell regions 161, 162, 163, and 164, the first semiconductor layers 111, 112, 113, and 114, the active layers 121, 122, 123, and 124, and the second semiconductor layers 131, 132 The 133 and 134 and the lower electrodes 151, 152, 153, and 154 are independently formed in the cell regions 161, 162, 163, and 164, respectively. Therefore, the first lower electrode 151 is exposed in the first unit region 161, and the first semiconductor layer 111 is exposed through the via hole 140. The second lower electrode 152 is exposed in the second cell region 162, and the first semiconductor layer 112 is exposed through the via hole 140. Similarly, the third lower electrode 153 and the first semiconductor layer 113 are exposed in the third cell region 163, and the fourth lower electrode 154 and the first semiconductor layer 114 are exposed in the fourth cell region 164.

In the present invention, the light emitting diode means that the first semiconductor layer 111, 112, 113 or 114, the active layer 121, 122, 123 or 124 and the second semiconductor layer 131, 132, 133 or 134 are laminated, respectively. structure. Therefore, one light emitting diode is formed in one unit region. When the light emitting diode is shaped such that the first semiconductor layer 111, When 112, 113 or 114 has n-type conductivity and the second semiconductor layer 131, 132, 133 or 134 has p-type conductivity, the lower electrodes 151, 152 formed on the second semiconductor layer 131, 132, 133 or 134, 153 or 154 can be used as the anode electrode of the light-emitting diode.

8 is a plan view showing formation of a first interlayer insulating layer on the entire surface of the structure of FIGS. 5 to 7, and exposing portions of the first semiconductor layer and the lower electrode in each of the unit regions.

9 to 12 are cross-sectional views taken along a specific line in the plan view of Fig. 8. In particular, FIG. 9 is a cross-sectional view taken along line B1-B2 in the plan view of FIG. 8, FIG. 10 is a cross-sectional view taken along line C1-C2 in the plan view of FIG. 8, and FIG. 11 is a plan view of FIG. A cross-sectional view taken along line D1-D2 in the middle, and FIG. 12 is a cross-sectional view taken along line E1-E2 in the plan view of FIG.

First, a first interlayer insulating layer 170 is formed for the structures of FIGS. 5 to 7. Further, portions of the lower electrodes 151, 152, 153, and 154 and portions of the first semiconductor layers 111, 112, 113, and 114 under the via holes are exposed by a patterning method.

For example, in the first cell region 161, two pre-formed via holes are opened, thereby exposing portions of the first semiconductor layer 111, and exposing a portion formed on the pre-formed second semiconductor layer 131 The portion of the electrode 151 is lowered. In the second cell region 162, a portion of the first semiconductor layer 112 is exposed via a pre-formed via hole, and a portion of the second lower electrode 152 is exposed by etching a portion of the first interlayer insulating layer 170 . In the third cell region 163, a portion of the first semiconductor layer 113 is exposed through the via hole, and by etching the first interlayer insulating layer 170 Part of the method exposes a portion of the third lower electrode 153. In the fourth cell region 164, a portion of the first semiconductor layer 114 is exposed through the via hole, and a portion of the fourth lower electrode 154 is exposed by etching a portion of the first interlayer insulating layer 170.

Therefore, in FIGS. 8 to 12, the first interlayer insulating layer 170 is formed on the entire surface of the substrate, and is exposed in each of the cell regions 161, 162, 163, and 164 by selective etching. Portions of the first semiconductor layers 111, 112, 113, and 114 under the via holes and portions of the lower electrodes 151, 152, 153, and 154 on the second semiconductor layers 131, 132, 133, and 134. That is, in each of the unit regions 161, 162, 163, and 164, the portions of the first semiconductor layers 111, 112, 113, and 114 are exposed through the via holes formed in advance in the previous process, and the lower electrodes 151 are also exposed. Sections 152, 153 and 154. The remaining area is shielded by the first interlayer insulating layer 170. The first interlayer insulating layer 170 may be formed of an insulating material having light transparency. For example, the first interlayer insulating layer may include SiO ₂ . Alternatively, the first interlayer insulating layer 170 may be formed as a distributed Bragg reflector in which the material layers have different reflection coefficients and are laminated. For example, the first interlayer insulating layer 170 may be formed by repeatedly stacking SiO ₂ /TiO ₂ to reflect light generated by the active layer.

13 is a plan view showing the upper electrode formed on the structure shown in FIGS. 8 to 12, and FIGS. 14 to 17 are cross-sectional views taken along a specific line in the plan view of FIG. In particular, FIG. 14 is a cross-sectional view taken along line B1-B2 in the plan view of FIG. 13, FIG. 15 is a cross-sectional view taken along line C1-C2 in the plan view of FIG. 13, and FIG. 16 is a plan view of FIG. A cross-sectional view taken along the line D1-D2, and FIG. 17 is a cross-sectional view taken along line E1-E2 in the plan view of FIG.

Referring to FIG. 13, upper electrodes 181, 182, 183, and 184 are formed. The upper electrodes 181, 182, 183, and 184 are formed as four separate regions. For example, a first upper electrode 181 is formed over the first cell region 161 and a portion of the second cell region 162. A second upper electrode 182 is formed over a portion of the second cell region 162 and a portion of the third cell region 163. A third upper electrode 183 is formed over a portion of the third cell region 163 and a portion of the fourth cell region 164. A fourth upper electrode 184 is formed in a portion of the fourth unit region 164. Thus, each of the upper electrodes 181, 182, 183, and 184 is formed while shielding the gap between adjacent ones in the cell region. The upper electrodes 181, 182, 183, and 184 may cover a gap between adjacent ones of the unit regions of not less than 30% (or not less than 50%, or not less than 90%). However, since the upper electrodes 181, 182, 183, and 184 are separated from each other, the upper electrodes 181, 182, 183, and 184 cover a region between adjacent ones of the light-emitting diodes of less than 100%.

The entire upper electrodes 181, 182, 183, and 184 may occupy an overall area of the light emitting diode array of not less than 30% (not less than 50%, not less than 70%, not less than 80%, or not less than 90%). However, since the upper electrodes 181, 182, 183, and 184 are separated from each other, they occupy less than 100% of the entire area of the array of light emitting diodes. Each of the upper electrodes 181, 182, 183, and 184 is in the shape of a plate or sheet having a wide aspect ratio in the range of 1:3 to 3:1. Further, the breadth or width of at least one of the upper electrodes 181, 182, 183, and 184 is greater than the breadth or width of the corresponding light-emitting diode (cell region).

Referring to FIG. 14, a first upper electrode 181 is formed on the first interlayer insulating layer 170 in the first cell region 161, and the first semiconductor layer is opened through the via hole. A first upper electrode 181 is formed on a portion of 111. Further, the first upper electrode 181 causes a portion of the first lower electrode 151 to be opened in the first unit region 161 and formed on a portion of the second lower electrode 152 exposed in the second unit region 162.

A second upper electrode 182 is formed on a portion of the first semiconductor layer 112 exposed through the via hole in the second cell region 162, wherein the second upper electrode 182 and the first upper electrode 181 are in a state of being substantially separated. Further, a second upper electrode 182 is formed on the first interlayer insulating layer 170.

In FIG. 14, the first upper electrode 181 electrically connects the first semiconductor layer 111 in the first cell region 161 to the second semiconductor layer 132 in the second cell region 162. Although there is a via hole, the second lower electrode 152 in the second cell region 162 is still in a state of being fully electrically short-circuited in one cell region. Therefore, the first semiconductor layer 111 in the first cell region 161 is electrically connected to the second semiconductor layer 132 in the second cell region 162 via the second lower electrode 152.

In FIG. 15, a second upper electrode 182 is formed on a portion of the first semiconductor layer 112 exposed through the via hole in the second cell region 162, and the second upper electrode 182 is formed to extend to the third cell region 163. The third lower electrode 153. A third upper electrode 183 which is substantially separated from the second upper electrode 182 is also formed on a portion of the first semiconductor layer 113 exposed through the via hole in the third cell region 163.

In FIG. 15 , the second upper electrode 182 is electrically connected to the first semiconductor layer 112 via a via hole in the second cell region 162 , and the second upper electrode 182 is electrically connected to the third cell region 163 . Three lower electrodes 153. Therefore, the first semiconductor layer 112 in the second cell region 162 can remain with the second semiconductor in the third cell region 163 Layer 113 has the same potential.

Referring to FIG. 16, a third upper electrode 183 is formed on a portion of the first semiconductor layer 113 exposed through the via hole in the third cell region 163, and the third upper electrode 183 is formed to extend to the fourth cell region 164. The fourth lower electrode 154 in the middle. Therefore, the first semiconductor layer 113 in the third cell region 163 is electrically connected to the second semiconductor layer 134 in the fourth cell region 164. The fourth upper electrode 184, which is substantially separated from the third upper electrode 183, is electrically connected to a portion of the first semiconductor layer 114 exposed through the via hole in the fourth cell region 164.

Referring to FIG. 17, a fourth upper electrode 184 is formed on a portion of the first semiconductor layer 114 exposed through the via hole in the fourth cell region 164. A first upper electrode 181 that is substantially separated from the fourth upper electrode 184 is formed on a portion of the first semiconductor layer 111 exposed through the via hole in the first cell region 161, and the first upper electrode 181 makes the first lower electrode A portion of 151 is exposed in the first unit area 161.

The contents disclosed in FIGS. 13 to 17 will be summarized below. The first semiconductor layer 111 in the first cell region 161 and the second semiconductor layer 132 in the second cell region 162 establish the same potential via the first upper electrode 181. The first semiconductor layer 112 in the second cell region 162 and the second semiconductor layer 133 in the third cell region 163 establish the same potential via the second upper electrode 182. The first semiconductor layer 113 in the third cell region 163 establishes the same potential as the second semiconductor layer 134 in the fourth cell region 164 via the third upper electrode 183. The first lower electrode 151 electrically connected to the second semiconductor layer 131 in the first unit region 161 is exposed.

Of course, the same potential is ignoring the upper electrodes 181, 182, 183, and 184. The impedance and the state of the contact impedance between the upper electrodes 181, 182, 183, and 184 and the lower electrodes 151, 152, 153, and 154 are established by a hypothetical ideal electrical connection. Therefore, in the operation of the real element, sometimes the impedance components of the upper electrodes 181, 182, 183, and 184 and the lower electrodes 151, 152, 153, and 154, which are various metal wires, may cause a voltage drop.

Meanwhile, the upper electrodes 181, 182, 183, and 184 may include a reflective conductor layer 180b. The reflective conductor layer 180b may include Al, Ag, Rh, Pt, or a combination thereof. The upper electrodes 181, 182, 183, and 184 including the reflective conductor layer 180b can reflect light toward the substrate 100, and light is generated by the active layers 121, 122, 123, and 124 in the respective unit regions 161, 162, 163, and 164. Further, the upper electrodes 181, 182, 183, and 184 may constitute an omnidirectional reflector together with the first interlayer insulating layer 170. Meanwhile, even when the first interlayer insulating layer 170 is formed as a distributed Bragg reflector, the upper electrodes 181, 182, 183, and 184 including the reflective conductor layer 180b can improve the light reflectance.

The upper electrodes 181, 182, 183, and 184 may also include an ohmic contact layer 180a. The reflective conductor layer 180b may be located on the ohmic contact layer 180a. The ohmic contact layer 180a includes a material such as Ni, Cr, Ti, Rh, Al, or a combination thereof that can be in ohmic contact with the first semiconductor layers 111, 112, 113, and 114 and the lower electrodes 151, 152, 153, and 154. However, the ohmic contact layer 180a is not limited thereto, and any material may be used for the ohmic contact layer 180a as long as it is in ohmic contact with the lower electrodes 151, 152, 153, and 154 made of a metal material while being in contact with the first semiconductor The layers 111, 112, 113 and 114 are in ohmic contact material. A film layer of, for example, a conductive oxide of ITO can be used.

Light generated by the active layers 121, 122, 123, and 124 in the respective unit regions 161, 162, 163, and 164 can be reflected from the lower electrodes 151, 152, 153, and 154 toward the substrate 100. In addition, the first interlayer insulating layer 170 and/or the upper electrodes 181, 182, 183, and 184, which are separated by gaps between adjacent ones of the cell regions 161, 162, 163, and 164, are reflected via the cell regions 161, 162, Light transmitted by the gap between adjacent ones of 163 and 164. The active layer 121, 122, 123 is reflected by the first interlayer insulating layer 170 disposed on the sidewall of the via or the via and/or by the upper electrodes 181, 182, 183 and 184 having the reflective conductor layer 180b. And 124 light L that is generated and directed to the gap between the vias or adjacent ones of the cell regions 161, 162, 163, and 164, and thus light can be extracted to the outside via the substrate 100. Therefore, it is possible to reduce the light loss, thereby improving the light extraction efficiency.

For this reason, it is preferable that the upper electrodes 181, 182, 183, and 184 occupy a large area in the array of light emitting diodes. For example, the upper electrodes 181, 182, 183, and 184 may cover the entire area of the light emitting diode array of not less than 70%, not less than 80%, or even not less than 90%. The interval between the upper electrodes 181, 182, 183, and 184 may be in the range of about 1 μm to 100 μm. More preferably, the interval between the upper electrodes 181, 182, 183, and 184 may be 5 μm to 15 μm. Therefore, it is possible to prevent light leakage in the gap between the vias or adjacent ones of the cell regions 161, 162, 163, and 164.

The upper electrodes 181, 182, 183, and 184 may further include a barrier layer 180c disposed on the reflective conductor layer 180b. The barrier layer 180c may include Ti, Ni, Cr, Pt, TiW, W, Mo, or a combination thereof. In a subsequent etching or cleaning process, the barrier layer 180c The reflective conductor layer 180b can be prevented from being damaged. The barrier layer 180c may be formed in a single layer or a multilayer structure and has a thickness ranging from 300 nm to 5000 nm.

If the first semiconductor layers 111, 112, 113, and 114 have n-type conductivity and the second semiconductor layers 131, 132, 133, and 134 have p-type conductivity, each of the upper electrodes may be shaped as a light-emitting diode. The cathode electrode is simultaneously used as a wire for connecting the cathode electrode of the light-emitting diode to the lower electrode, and the lower electrode is an anode electrode of the light-emitting diode formed in the adjacent cell region. That is, in the light-emitting diode formed in the cell region, the upper electrode may be shaped to form a cathode electrode and simultaneously serve as a light-emitting diode for electrically connecting the cathode electrode of the light-emitting diode to the adjacent cell region. The wire of the anode electrode of the polar body.

Figure 18 is a perspective view of the structure in the plan view of Figure 13.

Referring to FIG. 18, first to third upper electrodes 181 to 183 are formed over at least two unit regions. Mask the gap between adjacent unit areas. The upper electrode allows light (which may leak between adjacent cell regions) to be reflected through the substrate, and the upper electrode is electrically connected to the first semiconductor layer in each cell region. The upper electrode is electrically connected to the second semiconductor layer in the adjacent cell region.

Figure 19 is an equivalent circuit diagram obtained by modeling the structures of Figures 13 through 18 in accordance with an embodiment of the present invention.

Referring to Fig. 19, the wiring relationship between the four light-emitting diodes D1, D2, D3, and D4 and the light-emitting diodes is shown.

A first light-emitting diode D1 is formed in the first cell region 161, a second light-emitting diode D2 is formed in the second cell region 162, and a first light-emitting diode D2 is formed in the third cell region 163. The three light emitting diode D3 has a fourth light emitting diode D4 formed in the fourth unit region 164. The first semiconductor layers 111, 112, 113, and 114 in the cell regions 161, 162, 163, and 164 are formed as n-type semiconductors, and the second semiconductor layers 131, 132, 133, and 134 are formed as p-type semiconductors. .

The first upper electrode 181 is electrically connected to the first semiconductor layer 111 in the first unit region 161, and the first upper electrode 181 extends to the second unit region 162 to be electrically connected to the second one of the second unit regions 162. Semiconductor layer 132. Therefore, the first upper electrode 181 is shaped as a wire for connecting the cathode end of the first light-emitting diode D1 to the anode electrode of the second light-emitting diode D2.

The second upper electrode 182 is shaped as a wire for connecting the cathode end of the second light-emitting diode D2 and the anode end of the third light-emitting diode D3. The third upper electrode 183 is formed as a wire for connecting the cathode electrode of the third light-emitting diode D3 and the anode terminal of the fourth light-emitting diode D4. The fourth upper electrode 184 is shaped as a wire for forming a cathode electrode of the fourth light-emitting diode D4.

Therefore, the anode end of the first LED Dipole D1 and the cathode end of the fourth LED Dipole D4 are in an electrically open state with respect to the external power source, and the other LEDs D2 and D3 are electrically connected in series. .

Figure 20 is a plan view showing the application of a second interlayer insulating layer on the entire surface of the structure of Figure 13, the portion of the first electrode in the first cell region being exposed, and the fourth in the fourth cell region A portion of the electrode is exposed.

Figure 21 is a cross-sectional view taken along line B1-B2 in the plan view of Figure 20, Figure 22 is a cross-sectional view taken along line C1-C2 in the plan view of Figure 20, Figure 23 is at A cross-sectional view taken along line D1-D2 in the plan view of Fig. 20, and Fig. 24 is a cross-sectional view taken along line E1-E2 in the plan view of Fig. 20.

Referring to FIG. 21, in the first unit region 161, a portion electrically connected to the first lower electrode 151 of the second semiconductor layer 131 is opened. The remaining portion of the first cell region is covered with a second interlayer insulating layer 190 also over the second cell region 162.

Referring to FIG. 22, the second interlayer insulating layer 190 completely covers the second cell region 162 and the third cell region 163.

Referring to FIGS. 23 and 24, a portion of the fourth upper electrode 184 in the fourth unit region 164 is exposed, and a portion of the first lower electrode 151 in the first unit region 161 is exposed.

The second interlayer insulating layer 190 is an insulating material selected from a film that can protect the underlying film from the outside. In particular, the second interlayer insulating layer may include SiN or an equivalent having insulating properties and blocking temperature or humidity changes.

In FIGS. 20 to 24, the second interlayer insulating layer 190 is applied to the entire structure formed on the substrate, and the second interlayer insulating layer 190 is also exposed to the first lower electrode 151 in the first unit region 161. The fourth upper electrode 184 is partially and exposed in the fourth unit region 164.

Figure 25 is a plan view showing the formation of a first pad and a second pad in the structure of Figure 20;

Referring to FIG. 25, a first pad 210 may be formed over the first cell region 161 and the second cell region 162. Therefore, the first pad 210 can be electrically connected to the first lower electrode 151 in the first unit region 161 (exposed in FIG. 20).

Moreover, the second pad 220 is formed to be separated from the first pad 210 by a predetermined distance, and the second pad 220 may be formed over the third cell region 163 and the fourth cell region 164. The second pad 220 is electrically connected to the fourth upper electrode 184 (exposed in FIG. 20) in the fourth cell region 164.

Figure 26 is a cross-sectional view taken along line B1-B2 in the plan view of Figure 25, Figure 27 is a cross-sectional view taken along line C1-C2 in the plan view of Figure 25, and Figure 28 is along line D1- in the plan view of Figure 25. A cross-sectional view taken at D2, and Fig. 29 is a cross-sectional view taken along line E1-E2 in the plan view of Fig. 25.

Referring to FIG. 26, a first pad 210 is formed over the first cell region 161 and the second cell region 162. A first pad 210 is formed on the first lower electrode 151 exposed in the first unit region 161 and on the second interlayer insulating layer 190 in the other unit regions. Therefore, the first pad 210 is electrically connected to the second semiconductor layer 131 in the first cell region 161 via the first lower electrode 151.

Referring to FIG. 27, a first pad 210 is formed in the second cell region 162, and a second pad 220 is formed in the third cell region 163 such that the first pad 210 is separated from the second pad 220. In the second cell region 162 and the third cell region 163, the electrical contact of the first pad 210 or the second pad 220 with the lower electrode or the upper electrode is blocked.

Referring to FIG. 28, a second pad 220 is formed over the third cell region 163 and the fourth cell region 164. In particular, the second pad 220 is electrically connected to the fourth upper electrode 184 that is opened in the fourth cell region 164. Therefore, the second pad 220 is electrically connected to the first semiconductor layer 114 in the fourth cell region 164.

Referring to FIG. 29, a second pad 220 is formed in the fourth cell region 164. And the first pad 210 is formed to be separated from the second pad 220 in the first unit region 161. A first pad 210 is formed on the first lower electrode 151 in the first cell region 161, and the first pad 210 is electrically connected to the second semiconductor layer 131.

Figure 30 is a perspective view taken along line C2-C3 in the plan view of Figure 25.

Referring to FIG. 30, the first semiconductor layer 113 in the third cell region 163 is electrically connected to the third upper electrode 183. The third upper electrode 183 shields the gap between the third unit region 163 and the fourth unit region 164, and the third upper electrode 183 is electrically connected to the fourth lower electrode 154 of the fourth unit region 164. The first pads 210 and the second pads 220 are separated from each other and formed on the second interlayer insulating layer 190. Of course, as described above, the first pad 210 is electrically connected to the second semiconductor layer 131 in the first cell region 161, and the second pad 220 is electrically connected to the first semiconductor layer 114 in the fourth cell region 164. .

Referring to the model of FIG. 19, the first semiconductor layers 111, 112, 113, and 114 in the respective cell regions are formed as n-type semiconductors, and the second semiconductor layers 131, 132, 133, and 134 in the respective cell regions are formed. It is formed into a p-type semiconductor. The first lower electrode 151 formed on the second semiconductor layer 131 in the first unit region 161 is shaped as an anode electrode of the first light-emitting diode D1. Therefore, the first pad 210 can be shaped as a wire connected to the anode electrode of the first light-emitting diode D1. The fourth upper electrode 184 electrically connected to the first semiconductor layer 114 in the fourth unit region 164 is shaped as a cathode electrode of the fourth light-emitting diode D4. Therefore, the second pad 220 can be shaped as a wire connected to the cathode electrode of the fourth light-emitting diode D4.

Therefore, the array structure of the four light-emitting diodes D1 to D4 connected in series is formed, and via the two pads 210 and the pads 220 formed on the single substrate 100 The electrical connection of the above array structure to the outside is achieved.

In the present invention, it is shown that four light emitting diodes are formed while four light emitting diodes are separated from each other, and an anode end of one of the light emitting diodes is electrically connected to the light emitting diode via the lower electrode and the upper electrode. The cathode end of the other of the bodies. However, the four light-emitting diodes in this embodiment are only a vane, and various numbers of light-emitting diodes can be formed.

31 is a circuit diagram obtained by connecting a connection of ten light-emitting diodes in series according to an embodiment of the present invention.

Referring to FIG. 31, ten unit areas 301 to 310 are defined using the processing in FIG. The first semiconductor layer, the active layer, the second semiconductor layer, and the lower electrode in each of the cell regions 301 to 310 are separated from those in the other cell regions. The respective lower electrodes are formed on the second semiconductor layer to facilitate formation of the anode electrodes of the light-emitting diode D1 to the light-emitting diode D10.

Thereafter, the first interlayer insulating layer and the first to tenth upper electrodes 181, 182, 183, 184, 185, 186, 187, 188, 189, and 189' are formed using the processes shown in FIGS. 6 to 17. The upper electrodes 181, 182, 183, 184, 185, 186, 187, 188, 189, and 189' shield the gap between adjacent unit regions. The first to ninth upper electrodes 181, 182, 183, 184, 185, 186, 187, 188, and 189 function as an anode electrode for achieving one of a pair of adjacent light-emitting diodes and a light adjacent to the pair An electrically connected wire between the first semiconductor layers of the other of the diodes. The tenth upper electrode 189' is electrically connected to the first semiconductor layer of the light emitting diode D10.

Furthermore, the process shown in FIGS. 20 to 29 is used to form the second interlayer Insulation. The lower electrode of the first light-emitting diode D1 connected to the positive voltage V+ on the power supply path is exposed, and the upper electrode of the tenth light-emitting diode D10 connected to the negative voltage V- on the power supply path is opened. Next, the first pad 320 is formed and the first pad 320 is connected to the anode end of the first LED D1, and the second pad 330 is formed and the second pad 330 is connected to the tenth LED. The cathode end of D10.

Other light emitting diodes are connected in series/parallel to facilitate formation of the array.

Figure 32 is a circuit diagram of an array of light-emitting diodes having series/parallel connections according to an embodiment of the present invention.

Referring to FIG. 32, a plurality of light emitting diodes D1 to D8 are connected in series/parallel to each other. The light-emitting diode D1 to the light-emitting diode D8 are independently formed via the defined cell region 401 to the cell region 408, respectively. As described above, the anode electrode of each of the light-emitting diode D1 to the light-emitting diode D8 is formed via the lower electrode. A wire between the cathode electrode of each of the light-emitting diode D1 to the light-emitting diode D8 and the anode electrode of the adjacent light-emitting diode is manufactured by forming an upper electrode and performing appropriate wiring processing. However, a lower electrode is formed on the second semiconductor layer, and an upper electrode is formed to shield a gap between adjacent unit regions.

Finally, the first pad 410 supplied with the positive voltage V+ is electrically connected to the lower electrode formed on the second semiconductor layer of the first light emitting diode D1 or the third light emitting diode D3, and is supplied with a negative The second pad 420 of the voltage V- is electrically connected to the upper electrode as the cathode electrode of the sixth light emitting diode D6 or the eighth light emitting diode D8.

According to the invention as described above, the light generated in the active layer of each of the light-emitting diodes is reflected from the lower electrode and the upper electrode toward the substrate, and the flip-chip light-emitting diode The body is electrically connected via wires of the upper electrode on a single substrate. Specifically, the upper electrode functions between a first semiconductor layer for achieving one of a pair of adjacent light emitting diodes and a second semiconductor layer of the other of the pair of adjacent light emitting diodes Electrically connected wires. In this case, the upper electrode includes a reflective conductor layer to reflect light emitted by the luminescent layer to enhance light extraction efficiency.

The upper electrode is shielded from the outside via a second interlayer insulating layer. The first pad, which is supplied with a positive voltage, is electrically connected to the lower electrode of the light-emitting diode closest to the positive voltage connection. The second pad, which is supplied with a negative voltage, is electrically connected to the upper electrode of the light-emitting diode that is closest to the negative voltage connection.

Therefore, it is possible to solve the inconvenience in the process of loading a plurality of flip-chip type light-emitting diodes on the sub-mount substrate and performing the processing of both ends via the wires disposed on the sub-substrate to the external power source. In addition, the light reflection toward the substrate can be maximized by shielding the gap between adjacent cell regions by the upper electrode.

Further, the second interlayer insulating layer protects the laminated structure disposed between the substrate and the second interlayer insulating layer from external temperature or humidity and the like. Therefore, it is possible to realize a structure that can be directly loaded on a substrate without intervention of any separate packaging method.

In particular, since a plurality of flip-chip type light-emitting diodes are realized on a single substrate, there is an advantage that a commercial power source can be directly used while eliminating voltage drop, voltage level conversion, or waveform conversion for a commercial power source.

Although the preferred embodiments have been described to describe the present invention, the invention is not limited thereto. Therefore, it will be understood by those of ordinary skill in the art to which the present invention pertains. Various changes and modifications of the invention may be made without departing from the spirit and scope of the invention as defined by the appended claims.

100‧‧‧Substrate

111, 112‧‧‧ first semiconductor layer

121, 122‧‧‧ active layer

131, 132‧‧‧ second semiconductor layer

151, 152‧‧‧ lower electrode

161, 162‧‧‧ unit area

170‧‧‧First interlayer insulation

180a‧‧‧ohm contact layer

180b‧‧‧reflective conductor layer

180c‧‧‧Barrier layer

181, 182‧‧‧ upper electrode

B1-B2‧‧‧ line

L‧‧‧Light

Claims (25)

An array of light emitting diodes includes: a growth substrate; a plurality of light emitting diodes disposed on the growth substrate, each of the plurality of light emitting diodes having a first semiconductor layer, an active layer, and a second a semiconductor layer; and a plurality of upper electrodes disposed on the plurality of the light emitting diodes and formed of the same material, each of the plurality of upper electrodes being electrically connected to a corresponding one of the light emitting diodes The first semiconductor layer, wherein at least one of the upper electrodes is electrically connected to the second semiconductor layer adjacent to one of the light emitting diodes, and another one of the upper electrodes Is insulated from the second semiconductor layer of one of the light emitting diodes, and wherein each of the light emitting diodes has a second semiconductor layer via the second a semiconductor layer and the exposed via hole of the active layer, and wherein each of the upper electrodes is connected to the first one of a corresponding one of the light emitting diodes via the via hole Semiconductor layer. The light emitting diode array of claim 1, wherein the upper electrode comprises an ohmic contact layer in ohmic contact with the first semiconductor layer. The luminescent diode array of claim 2, wherein the ohmic contact layer comprises any one of the group consisting of Cr, Ni, Ti, Rh, and Al. The light emitting diode array of claim 2, wherein the ohmic contact layer comprises ITO. The light emitting diode array of claim 2, wherein the upper electrode comprises a reflective conductor layer on the ohmic contact layer. The light emitting diode array of claim 1, further comprising a first interlayer insulating layer disposed between the light emitting diode and the upper electrode, wherein the upper electrode is The first interlayer insulating layer is insulated from the side surface of the light emitting diode. The light emitting diode array of claim 6, further comprising a lower electrode respectively disposed on the second semiconductor layer of the light emitting diode, wherein the first interlayer insulating layer is exposed a portion of the lower electrode on each of the light emitting diodes, and wherein the upper electrode of the second semiconductor layer electrically connected to the adjacent light emitting diodes is via the A first interlayer insulating layer is attached to the exposed portion of the lower electrode. The light emitting diode array of claim 7, wherein each of the lower electrodes comprises a reflective layer. The illuminating diode array of claim 7, further comprising a second interlayer insulating layer covering the upper electrode, wherein the second interlayer insulating layer exposes one of the lower electrodes and The upper electrode of the adjacent second semiconductor layer of the light emitting diode is insulated. The light emitting diode array of claim 9, wherein the light emitting diodes are connected in series by the upper electrodes, and wherein the second interlayer insulating layer exposes the corresponding to the series connection Illuminate The lower electrode and the upper electrode of the light emitting diode at both ends of the diode. The illuminating diode array of claim 9, further comprising a first pad and a second pad disposed on the second interlayer insulating layer, wherein the first pad is connected to the via The lower electrode exposed by the second interlayer insulating layer is described, and the second pad is connected to the upper electrode exposed through the second interlayer insulating layer. The light emitting diode array of claim 1, wherein the upper electrode occupies at least 30% and less than 100% of an overall area of the light emitting diode array. The light-emitting diode array of claim 1, wherein each of the upper electrodes is in the form of a plate or sheet having an aspect ratio in the range of 1:3 to 3:1. The light emitting diode array of claim 1, wherein a breadth or a width of at least one of the upper electrodes is greater than a breadth or a width of a corresponding one of the light emitting diodes. The light emitting diode array of claim 1, wherein the upper electrode comprises a reflective conductor layer. The light emitting diode array of claim 15, further comprising a first interlayer insulating layer disposed between the light emitting diode and the upper electrode, wherein the upper electrode is The first interlayer insulating layer is insulated from the side surface of the light emitting diode. An array of light-emitting diodes according to claim 16 of the patent application, wherein The first interlayer insulating layer and the upper electrode constitute an omnidirectional reflector. The light emitting diode array of claim 16, wherein the first interlayer insulating layer comprises a distributed Bragg reflector. A method for forming a light emitting diode array, comprising: forming a plurality of light emitting diodes, each of the plurality of light emitting diodes having a first semiconductor layer, an active layer, and a second semiconductor layer on a growth substrate Each of the plurality of light emitting diodes has the first semiconductor layer exposed through a via hole formed by selectively removing the second semiconductor layer and the active layer Forming a first interlayer insulating layer for covering the light emitting diode, wherein the first interlayer insulating layer exposes the exposed first semiconductor layer and has the light emitting diode Openings on the second semiconductor layer of each of; and forming a plurality of upper electrodes on the first interlayer insulating layer with the same material, wherein each of the upper electrodes passes through the via a window hole connected to the first semiconductor layer of a corresponding one of the light emitting diodes, and wherein at least one of the upper electrodes is electrically connected via the opening of the first interlayer insulating layer To the adjacent one of the light emitting diodes A second semiconductor layer, and the other of the upper electrodes and the light-emitting diode in an adjacent one of the second insulating semiconductor. The method for forming a light emitting diode array according to claim 19, further comprising: before forming the first interlayer insulating layer, in each of the light emitting diodes A lower electrode is formed on the second semiconductor layer. The method for forming a light emitting diode array according to claim 20, further comprising: forming a second interlayer insulating layer on the upper electrode, wherein the second interlayer insulating layer exposes the lower electrode And one of the other upper electrodes insulated from the second semiconductor layer of the adjacent light emitting diode. The method for forming a light-emitting diode array according to claim 21, further comprising: forming a first pad and a second pad on the second interlayer insulating layer, wherein the first pad is connected To the lower electrode, and the second pad is connected to the upper electrode. The method of forming a light emitting diode array according to claim 19, further comprising: cutting the growth substrate into individual cells, wherein the upper electrode occupies each of the individual cells that are cut The area of the array of light emitting diodes is at least 30% and less than 100%. The method of forming a light emitting diode array according to claim 19, wherein each of the upper electrodes comprises a reflective conductor layer. The method of forming a light-emitting diode array according to claim 24, wherein the first interlayer insulating layer comprises a distributed Bragg reflector.