KR20130102030A - Light emitting device having plurality of light emitting cells and method of fabricating the same - Google Patents

Abstract

PURPOSE: A light emitting device having light emitting cells and a method for fabricating the same are provided to prevent electrical short circuits in the light emitting cells by preventing the generation of metal etching byproducts. CONSTITUTION: A first and a second light emitting cell (LS1,LS2) are positioned on the surface of a substrate. The first and the second light emitting cell include a first conductivity type upper semiconductor layer, a second conductivity type lower semiconductor layer, and an active layer respectively. Protection metal layers (135a,135b) are positioned under the first and the second light emitting cell respectively. The upper surface of the first conductivity type upper semiconductor layer and the protection metal layers are electrically connected by a line (155). The protection metal layers are electrically separated by an insulating layer.

Description

FIELD OF THE INVENTION [0001] The present invention relates to a light emitting device having a plurality of light emitting cells and a method of manufacturing the same.

The present invention relates to a light emitting device and a method of manufacturing the same, and more particularly, to a light emitting device having a plurality of light emitting cells and a method of manufacturing the same.

Gallium nitride-based light emitting diodes are widely used as display devices and backlights. In addition, the light emitting diode consumes less power and has a longer lifespan than existing light bulbs or fluorescent lamps, thereby replacing its incandescent lamps and fluorescent lamps, thereby expanding its use area for general lighting.

Recently, light emitting diodes that emit light by directly connecting a light emitting diode to a high voltage direct current power source or a high voltage alternating current power source have been commercialized. A light emitting diode which can be used in connection with a high voltage direct current or an alternating current power source is disclosed in, for example, International Publication No. WO 2004/023568 (A1), entitled " LIGHT-EMITTING DEVICE HAVING LIGHT-EMITTING ELEMENTS "Quot;, by SAKAI et al.

According to WO 2004/023568 (A1), a series LED array is formed in which LEDs are two-dimensionally connected on an insulating substrate such as a sapphire substrate. These series LED arrays can be driven under a high voltage direct current power supply. In addition, these LED arrays are connected in antiparallel on the sapphire substrate, and a single chip light emitting element capable of being driven by a high voltage AC power source is provided.

Since the light emitting device forms light emitting cells on a substrate used as a growth substrate, for example, a sapphire substrate, there is a limit to the structure of the light emitting cells, and there is a limit to improve light extraction efficiency. A method of manufacturing a light emitting device having a plurality of light emitting cells by applying a substrate separating process to solve such a problem is disclosed in Korean Registered Patent Application No. 10-0599012 entitled " Light Emitting Diode Having a Thermally Conductive Substrate and Method for Producing It " Lt; / RTI >

1 to 4 are cross-sectional views illustrating a method of manufacturing a light emitting device according to the related art.

1, semiconductor layers including a buffer layer 23, an N-type semiconductor layer 25, an active layer 27, and a P-type semiconductor layer 29 are formed on a sacrificial substrate 21, And a second metal layer 53 is formed on a substrate 51 separate from the sacrificial substrate 21. The first metal layer 31 is formed on the first metal layer 31, The first metal layer 31 may comprise a reflective metal layer. The second metal layer 53 is bonded to the first metal layer 31 and the substrate 51 is bonded to the upper portions of the semiconductor layers.

Referring to FIG. 2, after the substrate 51 is bonded, the sacrificial substrate 21 is separated using a laser lift-off process. After the substrate 21 is separated, the remaining buffer layer 23 is removed, and the surface of the N-type semiconductor layer 25 is exposed.

Referring to FIG. 3, the semiconductor layers 25, 27 and 29 and the metal layers 31 and 53 are patterned using photolithography and etching techniques to form metal patterns 40 spaced apart from each other, The light emitting cells 30 are formed on a partial region of the light emitting cells 30. [ The light emitting cells 30 include a patterned P-type semiconductor layer 29a, an active layer 27a, and an N-type semiconductor layer 25a.

Referring to FIG. 4, metal wires 57 electrically connecting the upper surface of the light emitting cells 30 and the metal patterns 40 adjacent thereto are formed. The metal wires 57 connect the light emitting cells 30 to form a serial array of light emitting cells. An electrode pad 55 may be formed on the N-type semiconductor layer 25a to connect the metal wires 57 and an electrode pad may be formed on the metal patterns 40. [ Two or more such arrays may be formed, and light emitting diodes are provided in which these arrays are connected in antiparallel and can be driven under an AC power source.

According to the above-described conventional techniques, the substrate 51 can be selected in various ways to improve the heat emission performance of the light emitting diode, and the light extraction efficiency can be improved by treating the surface of the N-type semiconductor layer 25a. In addition, since the first metal layer 31a includes the reflective metal layer and reflects light traveling from the light emitting cells 30 to the substrate 51 side, the light emitting efficiency can be further improved.

However, during the patterning of the semiconductor layers 25, 27 and 29 and the metal layers 31 and 53, the etching by-products of the metal material stick to the side walls of the light emitting cells 30 to form the N-type semiconductor layers 25a and the P-type semiconductor layer 29a. Also, the surface of the first metal layer 31a exposed during the etching of the semiconductor layers 25, 27 and 29 is liable to be damaged by the plasma. This etch damage is further exacerbated if the first metal layer 31a comprises a reflective metal layer such as Ag or Al. Damage to the surface of the metal layer 31a due to plasma deteriorates the adhesion of the wiring lines 57 or the electrode pads formed thereon, resulting in element failure.

Meanwhile, according to the prior art, the first metal layer 31 may include a reflective metal layer, thus reflecting light traveling from the light emitting cells 30 to the substrate side again. However, the reflective metal layer exposed in the space between the light emitting cells 30 is susceptible to etching damage as it is exposed to the outside. In particular, the oxidation of the exposed reflective metal layer is not limited to the exposed portion but proceeds to the region below the light emitting cells 30, thereby lowering the reflectance of the reflective metal layer.

Patent Document 1: International Publication No. WO 2004/023568 Patent Document 2: Korean Registered Patent Publication No. 10-0599012

SUMMARY OF THE INVENTION The present invention provides a light emitting device having a plurality of light emitting cells capable of preventing an electrical short circuit in a light emitting cell caused by a metal etch byproduct, and a method of manufacturing the same.

Another object of the present invention is to provide a light emitting device capable of preventing deformation of the reflective metal layer by etching or oxidation, and a method of manufacturing the same.

The present invention provides a light emitting device having a plurality of light emitting cells and a method of manufacturing the same. According to one aspect of the present invention, there is provided a light emitting device comprising: a substrate; A plurality of light emitting cells disposed on the substrate and spaced apart from each other, the plurality of light emitting cells including an upper semiconductor layer of a first conductive type, an active layer, and a lower semiconductor layer of a second conductive type; Electrodes spaced apart from each other and positioned between the substrate and the light emitting cells, each of the electrodes electrically connected to the corresponding lower conductive semiconductor layer of the second conductive type and having an extension extended to each adjacent light emitting cell; An etch stop layer disposed between the regions of the light emitting cells and the electrodes, the etching preventing layer having at least a portion extending below edges of neighboring light emitting cells and having an opening exposing an extension of the electrode; Side insulating layers covering side surfaces of the light emitting cells; And the other end of the wiring is electrically connected to the upper semiconductor layer of one light emitting cell and the other end of the wiring is electrically connected to the opening of the etch stop layer And the wirings electrically connected to the electrode electrically connected to the lower semiconductor layer of the neighboring light emitting cell. By employing the etch stop layer, it is possible to prevent the electrodes from being exposed during the etching of the light emitting cells, thereby preventing the generation of metal etch byproducts.

Meanwhile, an interlayer insulating layer may be interposed between the substrate and the electrodes. The interlayer insulating layer prevents the electrodes from being electrically short-circuited by the bonding metal.

In addition, the electrodes may include a reflective layer and a protective metal layer, respectively. The reflective layer may be formed of a reflective metal, but the present invention is not limited thereto, and a reflective layer in the form of a multi-layered film in which layers having different refractive indexes are stacked may be formed.

In addition, the reflective layer is confined within the lower region of the lower semiconductor layer, and the protective metal layer may cover the side and lower surfaces of the reflective layer. Thus, the reflective layer is prevented from being exposed to the outside, and oxidation of the reflective layer can be prevented.

On the other hand, the upper semiconductor layers may each have a roughened surface. The light extraction efficiency is increased by the roughened surface.

The substrate may be a sapphire substrate. In general, when a substrate separation process is used, a thermally conductive substrate different from sapphire is adopted as the bonded substrate, but the present invention is not particularly limited to the bonded substrate, but rather adopts a sapphire substrate as a preferable substrate. Therefore, by using the same substrate as the growth substrate of the semiconductor layers as the bonding substrate, the substrate separation process and the subsequent patterning processes can be performed more safely.

According to another aspect of the present invention, a method of manufacturing a light emitting device having a plurality of light emitting cells includes forming compound semiconductor layers on a sacrificial substrate, forming an etch stop layer having openings exposing the compound semiconductor layers on the compound semiconductor layers And forming the electrodes to fill the openings and partially extend over the etch stop layer. Thereafter, the sacrificial substrate is removed, and the compound semiconductor layers are patterned to separate the light emitting cells. At this time, the electrodes are prevented from being exposed by the etch stop layer, thereby preventing occurrence of metal etching by-products.

Specifically, the method for manufacturing a light emitting device includes the steps of: forming a first conductive semiconductor layer, a second conductive semiconductor layer, and a compound semiconductor layer including an active layer interposed between the first and second conductive semiconductor layers on a sacrificial substrate; Wherein the first conductivity type semiconductor layer is disposed close to the sacrificial substrate; Forming an anti-etching layer on the compound semiconductor layers, the anti-etching layer having openings exposing the second conductivity type semiconductor layer; Forming electrodes having an extension filling the openings of the etch stop layer and extending over the etch stop layer, the electrodes being spaced apart from each other; Forming an interlayer insulating layer on the electrodes; Bonding the substrate on the interlayer insulating layer; Removing the sacrificial substrate to expose the first conductivity type semiconductor layer; Patterning the compound semiconductor layers to expose the etch stop layer to form a plurality of light emitting cells spaced from each other; A side insulating layer covering the light emitting cells and exposing at least a part of the upper surface of the first conductive semiconductor layer, and patterning the etch stop layer to form openings for exposing the electrodes; And forming wirings connecting the first conductive semiconductor layer and the exposed electrodes.

According to the above manufacturing method, when the plurality of light emitting cells are formed by patterning the compound semiconductor layers, the etch stop layer prevents the electrodes from being exposed. Therefore, it is possible to prevent the metal etching by-products from sticking to the side walls of the light emitting cells. The etch stop layer is formed of an insulating layer such as a silicon oxide film or a silicon nitride film.

Further, forming the electrodes may include forming a reflective layer within the openings of the etch stop layer, and forming a protective metal layer covering the reflective layer. Thus, the reflective layer can be prevented from being exposed to the outside.

In addition, a roughened surface can be formed on the exposed surface of the first conductive semiconductor layer.

According to the present invention, it is possible to provide a light emitting device having a plurality of light emitting cells capable of preventing electrical short circuit in a light emitting cell by preventing metal etching byproducts from being generated, and a method of manufacturing the same. Further, according to the present invention, since the reflective layer is not exposed to the etching process and is not exposed to the outside, deformation due to etching or oxidation is prevented.

1 to 4 are cross-sectional views illustrating a method of manufacturing a light emitting device having a plurality of light emitting cells according to a related art.
5 is a cross-sectional view illustrating a light emitting device having a plurality of light emitting cells according to an embodiment of the present invention.
6 to 15 are cross-sectional views illustrating a method of manufacturing a light emitting device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the width, length, thickness, and the like of the components may be exaggerated for convenience. Like numbers refer to like elements throughout.

5 is a cross-sectional view illustrating a light emitting device having a plurality of light emitting cells according to an embodiment of the present invention.

5, the light emitting device includes a substrate 151, a plurality of light emitting cells LS1 and LS2, wirings 155, electrodes E1 and E2, an etch stop layer 131, 153, and may include an interlayer insulating layer 137, bonding metals 141, 143, and the like.

The substrate 151 is a bonded substrate which is separated from a growth substrate for growing compound semiconductor layers and is bonded to the already grown compound semiconductor layers. The bonding substrate 151 may be a sapphire substrate, but is not limited thereto, and may be another type of insulating or conductive substrate. Particularly, when a sapphire substrate is used as a growth substrate, it is preferable because it has the same thermal expansion coefficient as that of the growth substrate.

The plurality of light emitting cells LS1 and LS2 are spaced apart from each other on the substrate 151 and include a first conductive type upper semiconductor layer 125a, an active layer 127a, (129a). The active layer 127a is interposed between the upper and lower semiconductor layers 125a and 129a. Meanwhile, the lower semiconductor layer 129a and the upper semiconductor layer 125a may have the same area.

The active layer 127a and the upper and lower semiconductor layers 125a and 129a may be formed of a III-N compound semiconductor, for example, an (Al, Ga, In) N semiconductor. The upper and lower semiconductor layers 125a and 129a may be a single layer or a multi-layer, respectively. For example, the upper and / or lower semiconductor layers 125a and 129a may include a contact layer and a clad layer, and may also include a superlattice layer. Further, the active layer 127a may be a single quantum well structure or a multiple quantum well structure. Preferably, the first conductivity type is n-type, and the second conductivity type is p-type. The upper semiconductor layers 125a can be formed of the n-type semiconductor layer having a relatively small resistance, so that the thickness of the upper semiconductor layers 125a can be relatively increased. Therefore, it is easy to form a rough surface R on the upper surface of the upper semiconductor layer 125a, and the rough surface R improves extraction efficiency of light generated in the active layer 127a.

The electrodes E1 and E2 are spaced apart from each other between the substrate 151 and the light emitting cells LS1 and LS2. The electrode E1 is electrically connected to the lower semiconductor layer 129a of the light emitting cell LS1 and the electrode E2 is electrically connected to the lower semiconductor layer 129a of the light emitting cell LS2. On the other hand, each of the electrodes E1 and E2 has an extension extending toward the adjacent light emitting cell. That is, the electrode E1 has an extension extending to the light emitting cell (not shown) adjacent thereto and the electrode E2 has an extension extending toward the light emitting cell LS1.

The electrodes E1 and E2 may have reflective layers 133a and 133b and protective metal layers 135a and 135b. The reflective layers 133a and 133b may be formed of a metal material having a high reflectance, such as silver (Ag) or aluminum (Al), or an alloy thereof. Further, the reflective layers 133a and 133b may be formed in a multi-layered structure having different refractive indexes. In this case, the reflective layer may have through holes, and the protective metal layer may be connected to the light emitting cells through the through holes. The reflective layers 133a and 133b may be directly in contact with the lower semiconductor layers 129a of the light emitting cells LS1 and LS2 but other ohmic contact layers may be interposed between the reflective layer and the lower semiconductor layer. The protective metal layers 135a and 135b cover the reflective layer to prevent the reflective layer from being exposed to the outside. The protective metal layer may be formed of a single layer or a multilayer, and may be formed of, for example, Ni, Ti, Ta, Pt, W, Cr, Pd or the like. As shown, the protective metal layers 135a and 135b may extend outward to form an extended portion.

The etch stop layer 131 is located between the regions between the light emitting cells LS1 and LS2 and the electrodes E1 and E2. That is, the etch stop layer 131 is located at the bottom of the spaces generated as the light emitting cells LS1 and LS2 are separated. The etch stop layer 131 prevents the extensions of the electrodes E1 and E2 from being exposed in the separated region. The etch stop layer 131 extends under the edges of at least some neighboring light emitting cells LS1 and LS2. The etch stop layer 131 may be located below the bottom surface of the light emitting cells LS1 and LS2. Alternatively, a part of the etch stopping layer 131 may protrude into a region between the light emitting cells. The etch stop layer 131 is formed of an insulating layer such as a silicon oxide layer or a silicon nitride layer.

The extension of the electrodes extends below the etch stop layer 131 and the etch stop layer 131 has openings exposing the extensions of the electrodes E1 and E2. These openings provide a passage through which the wires 155 can be electrically connected to the electrodes E1 and E2.

On the other hand, the side insulating layer 153 covers the side surfaces of the light emitting cells LS1 and LS2 to prevent the wires 155 from shorting the upper semiconductor layer and the lower semiconductor layer of the light emitting cells. The side insulating layer 153 may cover a part of the upper surface of the light emitting cells and may extend to an upper portion of the etch stop layer 131. In this case, the side insulating layer 153 has openings for exposing the openings of the etch stop layer.

The wirings 155 electrically connect the light emitting cells LS1 and LS2 to form a serial array. Each of the wirings 155 is electrically connected to an electrode electrically connected to the upper semiconductor layer 125a of one light emitting cell at one end and electrically connected to the lower semiconductor layer 129a of the light emitting cell at the other end thereof, . One end of the wiring 155 is electrically connected to the upper semiconductor layer 125a of the light emitting cell LS1 and the other end of the wiring 155 is electrically connected to the electrode E2 through the opening of the etch stop layer 131. [ Pads (not shown) may be formed on the upper semiconductor layers 125a and the electrodes E1 and E2 to electrically connect the wirings 155. [ The wiring lines 155 are insulated from the side surfaces of the light emitting cells LS1 and LS2 by the side insulating layer 153. [

A serial array of light emitting cells is formed on the substrate 151 by the wires 155. Accordingly, the serial array can be connected to a high voltage DC power source and driven. On the other hand, at least two serial arrays may be formed on the substrate 151 by the wires 155, and the arrays may be connected in antiparallel to each other to be driven by an AC power source. Alternatively, a series array may be formed by wirings on the substrate, and the series array may be driven to an alternating current source by being connected to a bridge rectifier formed on the substrate. The bridge rectifier may also be formed by connecting the light emitting cells by wirings.

An interlayer insulating layer 137 may be interposed between the electrodes E1 and E2 and the substrate 151. Bonding metals 141 and 143 may be interposed between the interlayer insulating layer 137 and the substrate 151. [ Can be intervened. The interlayer insulating layer 137 prevents the electrodes E1 and E2 from being shorted to each other by the substrate 151 or the bonding metals 141 and 143. [

The bonding metals 141 and 143 improve adhesion between the interlayer insulating layer 137 and the bonding substrate 151 to prevent the bonding substrate 151 from being separated from the interlayer insulating layer 137.

6 to 11 are cross-sectional views illustrating a method of manufacturing a light emitting device according to an embodiment of the present invention.

Referring to FIG. 6, compound semiconductor layers are formed on the sacrificial substrate 121. The sacrificial substrate 121 may be a sapphire substrate, but is not limited thereto, and may be another heterogeneous substrate. Meanwhile, the compound semiconductor layers include a first conductive semiconductor layer 125, a second conductive semiconductor layer 129, and an active layer 129 interposed therebetween. The first conductive semiconductor layer 125 is positioned close to the sacrificial substrate 121. The first and second conductive semiconductor layers 125 and 129 may be formed of a single layer or a multilayer. In addition, the active layer 127 may be formed of a single quantum well structure or a multiple quantum well structure.

The compound semiconductor layers may be formed of a III-N compound semiconductor and may be grown on the sacrificial substrate 121 by a process such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) .

Meanwhile, before forming the compound semiconductor layers, a buffer layer (not shown) may be formed. The buffer layer is employed for relieving the lattice mismatch between the sacrificial substrate 121 and the compound semiconductor layers, and may be a layer of a gallium nitride based material such as gallium nitride or aluminum nitride.

Referring to FIG. 7, an anti-etching layer 131 is formed on the compound semiconductor layers, for example, the second conductive semiconductor layer 129. The etching prevention layer 131 has openings for exposing the second conductivity type semiconductor layer 129. The openings are formed corresponding to the respective light emitting cell regions on the light emitting cell regions, and are formed in a smaller area than the light emitting cell regions.

The etch stop layer 131 is formed by forming an insulating layer such as a silicon oxide layer or a silicon nitride layer on the second conductive type semiconductor layer 129 and patterning the insulating layer using a photolithography and etching process.

And reflection layers 133a and 133b are formed in the openings. The reflective layers 133a and 133b may be formed of a metal material having a high reflectance such as Ag, Al, or an alloy thereof. Alternatively, the reflective layers 133a and 133b may be formed by laminating layers having different refractive indices. When the reflective layer 131 is formed of a metal layer, the reflective layer 131 may be formed using a plating or deposition technique, for example, using a lift-off process. Meanwhile, an ohmic contact layer (not shown) may be formed on the second conductive semiconductor layer 129 before forming the reflective layers. In addition, the reflective layers may be formed first, and the etch stop layer 131 may be formed thereafter.

Referring to FIG. 8, protective metal layers 135a and 135b are formed to cover the reflective layers 133a and 133b. The protective metal layers 135a and 135b fill the openings of the etch stop layer 131 and extend to the top surface of the etch stop layer 131, respectively. The protective metal layers 135a and 135b are formed to be spaced apart from each other. The protective metal layers 135a and 135b may be formed of a single layer or a multilayer and may be formed of, for example, Ni, Ti, Ta, Pt, W, Cr, Pd or the like.

In the present embodiment, the reflective layers 133a and 133b and the protective metal layers 135a and 135b constitute electrodes E1 and E2. However, the electrodes E1 and E2 are not limited thereto and may be formed of a single metal layer. For example, the formation of the reflective layers may be omitted, and the electrodes may be formed of only the protective metal layers 135a and 135b.

Referring to FIG. 9, an interlayer insulating layer 137 is formed on the electrodes E1 and E2. The interlayer insulating layer 137 covers the electrodes E1 and E2 and can fill gaps between the electrodes E1 and E2. The material of the interlayer insulating layer is not particularly limited, and may be formed of a silicon oxide film or a silicon nitride film.

Referring to FIG. 10, a bonding metal 141 is formed on the interlayer insulating layer 137, and a bonding metal 143 is formed on a separate substrate 151. The bonding metal 141 may be formed of, for example, AuSn (80/20 wt%). The substrate 151 is not particularly limited, but may be a substrate having the same thermal expansion coefficient as that of the sacrificial substrate 121, and may be, for example, a sapphire substrate.

Referring to FIG. 11, a substrate 151 is bonded on the interlayer insulating layer 137 by bonding the bonding metals 141 and 143 to face each other. Then, the sacrificial substrate 121 is removed and the first conductive type semiconductor layer 125 is exposed. The sacrificial substrate 121 may be separated by a laser lift off (LLO) technique or other mechanical or chemical method. At this time, the buffer layer is also removed to expose the first conductivity type semiconductor layer 125. 12 is a view showing the first conductivity type semiconductor layer 125 facing upward after the sacrificial substrate 121 is removed.

Referring to FIG. 13, the compound semiconductor layers are patterned to form a plurality of light emitting cells LS1 and LS2. The light emitting cells LS1 and LS2 each include a patterned first conductive semiconductor layer 125a, a patterned active layer 127a, and a patterned second conductive semiconductor layer 129a. The compound semiconductor layers can be patterned using a photolithography and etching process, which process is commonly known as a mesa etching process. At this time, the compound semiconductor layers between the light emitting cells are removed by the etching process, and the etching preventing layer 131 is exposed. The etch stop layer 131 prevents the underlying electrodes E1 and E2 from being exposed during the etching process. To this end, etching is performed in a confined region above the etch stop layer 131.

Referring to FIG. 14, a side insulating layer 153 is formed to cover the side surfaces of the light emitting cells LS1 and LS2. The side insulating layer 153 may be formed by forming an insulating layer covering the light emitting cells and then patterning the insulating layer using a photolithography and etching process. The side insulating layer may be formed of, for example, SiO ₂ , SiN, MgO, TaO, TiO ₂ , or a polymer. The side insulating layer 153 covers the first conductivity type semiconductor layer 125a, the active layer 127a, and the second conductivity type semiconductor layer 129a exposed at the sides of the light emitting cells. The side insulating layer 153 can also cover a part of the upper surface of the light emitting cells LS1 and LS2, as shown in the figure. Further, the side insulating layer 153 may extend over the etch stop layer 131. Openings 131a for exposing the extensions of the electrodes E1 and E2 are formed in the etch stop layer 131 during or after the side insulating layer 153 is formed.

Referring to FIG. 15, wirings 155 for electrically connecting the light emitting cells LS1 and LS2 are formed. The wires 155 are electrically connected to the electrode E2 electrically connected to the first conductivity type semiconductor layer 125a of the light emitting cell LS1 and the second conductivity type semiconductor layer 129a of the light emitting cell LS2 do. That is, one end of the wiring 155 is electrically connected to the first conductivity type semiconductor layer 125a of the light emitting cell LS1 and the other end is electrically connected to the second conductivity type semiconductor layer 129a of the light emitting cell LS2. And is electrically connected to the electrically connected electrode E2.

Pads (not shown) are formed on the first conductivity type semiconductor layers 125a and / or the electrodes E1 and E2 to improve the adhesion or ohmic contact characteristics of the wirings before forming the wirings 155. [ Lt; / RTI >

On the other hand, a rough surface R may be formed on the first conductivity type semiconductor layers 125a on the light emitting cells by PEC (photoelectrochemical) etching or the like. The roughened surface R may be performed before forming the wirings. Thus, the light emitting element of Fig. 5 is completed.

Although the embodiments of the present invention have been described above by way of example, the present invention is not limited to the above-described embodiments and may be variously modified and changed by those skilled in the art without departing from the spirit of the present invention. . Such variations and modifications are intended to fall within the scope of the invention as defined in the following claims.

Claims (6)

Board;
A first conductive type upper semiconductor layer, a second conductive type lower semiconductor layer, and an active layer between the first conductive type upper semiconductor layer and the second conductive type lower semiconductor layer, Second light emitting cells;
Protective metal layers located under the first and second light emitting cells, respectively;
A wiring electrically connecting the upper surface of the first conductive upper semiconductor layer of the first light emitting cell and the protective metal layer below the first light emitting cell and the neighboring second light emitting cell; And
And an insulating layer electrically insulating the protective metal layers under the first and second light emitting cells. The light emitting device of claim 1, further comprising a reflective layer between each protective metal layer and each of the light emitting cells. The light emitting device of claim 2, wherein the protective metal layer covers the reflective layer to prevent the reflective layer from being exposed to the outside. The light emitting device of claim 1, wherein the protective metal layer under the second light emitting cell extends below a region between the first light emitting cell and the second light emitting cell and is connected to the wiring. The light emitting device of claim 1, further comprising a bonding metal disposed below the insulating layer. The light emitting device of claim 1, wherein the upper surface of the first conductive upper semiconductor layer comprises a roughened surface.

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