KR101893578B1 - Light emitting diode array on wafer level - Google Patents

Abstract

An array of flip chip type light emitting diodes is disclosed. A plurality of light emitting diodes are formed on the same substrate. On the second semiconductor layer of the light emitting diode, lower electrodes capable of serving as an anode electrode are formed in a separated state. A first interlayer insulating film is formed on the lower electrode, and upper electrodes are formed on the first interlayer insulating film. Each upper electrode is formed across a spacing space between the cell regions in which the light emitting diodes are formed and is electrically connected to the first semiconductor layer opened by a via hole in the cell region. A second interlayer insulating film is formed on the upper electrode, and the anode electrode and the cathode electrode are exposed through the second interlayer insulating film. The plurality of light emitting diodes are sequentially connected through the upper electrode, the first pad is connected to the anode terminal of the input light emitting diode to which the positive power voltage is applied, and the second pad is connected to the output light emitting diode And is connected to the cathode terminal.

Description

[0001] LIGHT EMITTING DIODE ARRAY ON WAFER LEVEL [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a light emitting diode array, and more particularly, to a light emitting diode array in which a plurality of light emitting diodes are connected to each other through a wiring and formed into a flip chip type.

The light emitting diode is an element that performs a light emitting operation when a voltage higher than a turn-on voltage is applied through the anode terminal and the cathode terminal. Generally, the turn-on voltage that induces the light emitting operation of the light emitting diode has a very low value compared to the commercial power supply used. Therefore, the light emitting diode is disadvantageous in that it is difficult to directly use it under a commercial AC power source of 110V or 220V. In order to operate a light emitting diode using a commercial AC power source, a voltage converter is required to drop the supplied AC voltage. Accordingly, the driving circuit of the light emitting diode must be provided, and the manufacturing cost of the lighting device including the light emitting diode is increased. In addition, since a separate driving circuit must be provided, the volume of the lighting apparatus is increased, unnecessary heat is generated, and the power factor against the applied electric power remains.

In order to use commercial AC power without excluding a separate voltage converting means, a method of constructing an array by connecting a plurality of light emitting diode chips in series is proposed. In order to implement light emitting diodes as an array, the light emitting diode chips must be formed in individual packages. Accordingly, a substrate separation process, a packaging process for the separated light emitting diode chip, and the like are required. A mounting process for disposing the individual packages on the array substrate and a wiring process for the electrodes between the packages are separately required. Therefore, there is a problem that the process time for constructing the array increases and the manufacturing cost increases.

Further, wire bonding is used in the wiring step constituting the array, and a separate molding layer for protecting the bonding wire is formed on the entire surface of the array. Therefore, there is a problem that a molding forming process for forming a molding layer is further required, thereby increasing the complexity of the process. Particularly, when a chip type of a lateral structure is applied, deterioration of the light emitting performance and deterioration of the quality of the light emitting diode due to heat generation remain.

In order to solve the above-described problems, there is proposed a light emitting diode chip array in which an array of a plurality of light emitting diode chips is formed into a single package.

Korean Patent Publication No. 2007-0035745 discloses that a plurality of horizontal type light emitting diode chips are electrically connected to each other through a metal wiring formed by an air bridge process on a single substrate. According to the above-described patent, there is no need for a separate packaging process in individual chip units, and there is an advantage of forming an array at a wafer level. However, since it has an air bridge connection structure, its durability is poor, and the light emitting performance or heat generation performance is deteriorated due to the horizontal chip type.

In addition, U.S. Patent No. 6,573,537 discloses a plurality of flip chip type light emitting diodes on a single substrate. However, the n-electrode and the p-electrode of each light emitting diode are exposed while being separated from each other. Therefore, in order to use a single power source, a wiring process for connecting a plurality of electrodes to each other must be added. To this end, the submount substrate is used in the above patent. That is, flip chip type light emitting diodes should be mounted on a separate submount substrate for wiring between the electrodes. At least two electrodes for electrical connection with the substrate must be formed on the back surface of the submount substrate. Since the flip chip type is used, the light emitting performance and the heat generating performance are improved. On the other hand, the use of the submount substrate increases the manufacturing cost and increases the thickness of the final product. In addition, there is a disadvantage that an additional wiring process for the submount substrate and an additional process for mounting the submount substrate to the new substrate are required.

Korean Patent Publication No. 2008-0002161 discloses a configuration in which flip chip type light emitting diodes are connected in series to each other. According to the above-described patent, a chip-based packaging process is not required, and the use of the flip-chip type improves the light emitting characteristic and the heat generating performance. However, a separate reflective layer is used in addition to the wiring between the n-type semiconductor layer and the p-type semiconductor layer, and interconnection wiring is used on the n-type electrode. Therefore, a plurality of metalized metal layers must be formed, and various types of masks must be used for this purpose. Also, due to the difference in thermal expansion coefficient between the n electrode and the interconnection electrode, peeling or cracking is generated and electrical contact is opened.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a flip chip type light emitting diode array capable of high voltage driving.

Another object of the present invention is to provide a light emitting diode array which can be directly mounted on a printed circuit board or the like without a submount.

Another object of the present invention is to provide a flip chip type light emitting diode array capable of preventing light loss in addition to a wiring for connecting a plurality of light emitting diodes without a separate reflective metal layer.

Another object of the present invention is to provide a light emitting diode array having improved reliability by preventing cracks from occurring in the layers covering the light emitting diodes.

Other features and advantages of the present invention will become apparent from the following description and from the description that follows.

A light emitting diode array according to an embodiment of the present invention includes a growth substrate; A plurality of light emitting diodes arranged on the substrate, the plurality of light emitting diodes including a first semiconductor layer, an active layer and a second semiconductor layer, respectively; A plurality of upper electrodes arranged on the plurality of light emitting diodes and formed of the same material as each other and electrically connected to the first semiconductor layers of the corresponding light emitting diodes; And a first pad and a second pad arranged on the upper electrodes. Wherein at least one of the upper electrodes is electrically connected to a second semiconductor layer of an adjacent light emitting diode and the other of the upper electrodes is insulated from a second semiconductor layer of an adjacent light emitting diode. In addition, the light emitting diodes are connected in series by the upper electrodes. Further, the first pad is electrically connected to the input light emitting diode among the series-connected light emitting diodes, and the second pad is electrically connected to the output light emitting diode among the series connected light emitting diodes.

Thereby, a flip chip type light emitting diode array capable of high voltage driving is provided. Further, since the light emitting diodes are connected in series by the upper electrodes, it is not necessary to use a submount for electrically connecting the light emitting diodes.

Further, each of the light emitting diodes is separated by a mesa etching region exposing the substrate, and the sides of the films exposed by the mesa etching have an inclination angle of 10 to 60 degrees with respect to the substrate. As a result, it is possible to prevent cracks from being generated in the layers covering the mesa etching region.

The light emitting diode array may further include a first interlayer insulating film disposed between the light emitting diodes and the upper electrodes. The side surfaces of the upper electrodes positioned above the first interlayer insulating layer may include side surfaces having an inclination angle of 10 degrees to 45 degrees with respect to the upper surface of the first interlayer insulating layer. Thus, it is possible to prevent cracks from being generated in the layers covering the upper electrodes. In addition, the upper electrode may have a thickness within the range of 2000 Å to 10000 Å.

The light emitting diode array may further include lower electrodes aligned on a second semiconductor layer of each light emitting diode. The first interlayer insulating film exposes a part of the lower electrode on each light emitting diode. The upper electrode (s) electrically connected to the second semiconductor layer of the adjacent light emitting diode may be connected to the exposed lower electrode through the first interlayer insulating film.

The side surfaces of the lower electrodes located above the second semiconductor layer may each include a side surface having an inclination angle of 10 degrees to 45 degrees with respect to the upper surface of the second semiconductor layer. Accordingly, it is possible to prevent cracks from being generated in the layers covering the lower electrodes. The thickness of the lower electrode may be 2000 ANGSTROM to 10,000 ANGSTROM.

The side surface of the first interlayer insulating film located on the upper part of the lower electrodes on which a part is exposed may include a side surface having an inclination angle of 10 degrees to 60 degrees with respect to the upper surface of the lower electrodes. As a result, cracks can be prevented from being generated in the layers covering the first interlayer insulating film. The first interlayer insulating layer may have a thickness of 2000 ANGSTROM to 20000 ANGSTROM.

The light emitting diode array may further include a second interlayer insulating film covering the upper electrodes. The second interlayer insulating layer exposes a lower electrode aligned on the second semiconductor layer of the input light emitting diode and an upper electrode connected to the first semiconductor layer of the output light emitting diode. The first pad and the second pad are connected to the lower electrode and the upper electrode through the second interlayer insulating film, respectively.

Furthermore, the side surface of the second interlayer insulating film located above the upper electrode may include a side surface having an inclination angle of 10 degrees to 60 degrees with respect to the upper surface of the upper electrode. Therefore, it is possible to prevent cracks from occurring in the first and second pads covering the second interlayer insulating film. Meanwhile, the second interlayer insulating layer may have a thickness of 2000 ANGSTROM to 20000 ANGSTROM.

Each of the light emitting diodes may have a via hole exposing a part of the first semiconductor layer and the upper electrodes may be connected to the first semiconductor layer of the corresponding light emitting diode through the via hole.

The side inclination angle of the films exposed through the via hole may be in the range of 10 degrees to 60 degrees. Thus, cracks can be prevented from being generated in the layers covering the via holes.

On the other hand, the upper electrode may occupy an area of 30% or more and less than 100% of the total area of the LED array.

In addition, the upper electrode may have a plate or sheet shape with a ratio of width to width being in the range of 1: 3 to 3: 1. Unlike the conventional linear wiring, the upper electrode may be formed in a plate or sheet shape to facilitate current dispersion and reduce the forward voltage of the light emitting diode array.

At least one of the upper electrodes has a greater width or width than the width or width of the corresponding light emitting diode. Therefore, the upper electrode covers the region between the light emitting diodes and can reflect the light generated in the active layer to the substrate side.

According to embodiments of the present invention, it is possible to provide a wafer-level flip-chip type light emitting diode array capable of improving reliability by forming side surfaces of light emitting diodes at an angle to be inclined. Furthermore, by forming the side surfaces of the lower electrode, the first interlayer insulating film, the upper electrode, or the second interlayer insulating film so as to be inclined at a predetermined angle, it is possible to prevent cracks from being generated in other layers formed on the respective layers.

Meanwhile, a light emitting diode array capable of driving at a high voltage can be provided by connecting the light emitting diodes in series using the upper electrode. By adopting relatively wide upper electrodes, it is possible to improve the current dispersion performance and improve the reflection efficiency Emitting diode array.

1 and 2 are a plan view and a cross-sectional view, respectively, illustrating formation of via holes in a plurality of stacked structures, according to an embodiment of the present invention.
FIGS. 3 and 4 are a plan view and a cross-sectional view illustrating that lower electrodes are formed on the second semiconductor layer of FIG.
5 is a plan view showing a state in which cell regions are separated from the structure of FIG.
6 is a cross-sectional view taken along the line A 1 -A 2 in the plan view of FIG. 5;
7 is a perspective view of the plan view of Fig.
8 is a plan view showing a first interlayer insulating film formed on the entire surface of the structures of FIGS. 5 to 7 and partially exposing the first semiconductor layer and the lower electrode in each cell region.
9 to 12 are cross-sectional views taken along a specific line in the plan view of FIG.
13 is a plan view showing top electrodes formed on the structure shown in Figs. 8 to 12. Fig.
Figs. 14 to 17 are cross-sectional views taken along a specific line in the plan view of Fig.
Fig. 18 is a perspective view showing the plan view of Fig. 13. Fig.
19 is an equivalent circuit diagram modeling the structures of FIGS. 13 to 18 according to a preferred embodiment of the present invention.
FIG. 20 is a plan view of the structure of FIG. 13 in which a second interlayer insulating film is applied to the entire surface of the structure, a part of the first lower electrode of the first cell region is exposed, to be.
FIGS. 21 to 24 are cross-sectional views of the plan view of FIG. 20 taken along a specific line.
FIG. 25 is a plan view showing a first pad and a second pad formed on the structure of FIG. 20. FIG.
26 to 29 are cross-sectional views taken along a specific line in the plan view of Fig.
Fig. 30 is a perspective view of the plan view of Fig. 25 taken along line C2-C3.
31 is a circuit diagram modeling 10 LEDs connected in series according to an embodiment of the present invention.
32 is a circuit diagram modeling an array of light emitting diodes in a serial / parallel form according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms.

In the present embodiments, "first "," second ", or "third" is not intended to impose any limitation on the elements, but merely as terms for distinguishing the elements.

1 and 2 are a plan view and a cross-sectional view, respectively, illustrating formation of via holes in a plurality of stacked structures, according to an embodiment of the present invention.

Particularly, Fig. 2 is a sectional view taken along line A1-A2 of the plan view of Fig.

1 and 2, a first semiconductor layer 110, an active layer 120, and a second semiconductor layer 130 are formed on a substrate 100, and a surface of the first semiconductor layer 110 is exposed The via holes 140 are formed.

The substrate 100 may have a material of sapphire, silicon carbide, or GaN, and any material capable of inducing growth of a thin film to be formed may be used. The first semiconductor layer 110 may have an n-type conductivity. The active layer 120 may have a multiple quantum well structure, and the second semiconductor layer 130 may be formed on the active layer 120. When the first semiconductor layer 110 has an n-type conductivity, the second semiconductor layer 130 has a p-type conductivity. In addition, a buffer layer (not shown) may be further formed between the substrate 100 and the first semiconductor layer 110 to facilitate the single crystal growth of the first semiconductor layer 110.

Then, selective etching is performed on the structure formed up to the second semiconductor layer 130, and a plurality of via holes 140 are formed. A part of the lower first semiconductor layer 110 is exposed through the via hole 140. The via hole 140 may be formed according to a conventional etching process. For example, after a photoresist is applied, a photoresist pattern is formed by removing the photoresist in a region to be formed through a normal patterning process. Thereafter, the etching process is performed using the photoresist pattern as an etching mask. The etching process proceeds until a portion of the first semiconductor layer 110 is exposed. The remaining photoresist pattern is then removed.

The via hole 140 has a predetermined inclination angle a with respect to the surface of the first semiconductor layer 110 exposed by the surface or etching of the substrate. Particularly, when the via hole 140 does not have a predetermined inclination angle in a metal deposition process or an insulating material application process to be formed later, a crack may occur in a part of the metal layer or the insulating layer to be deposited. In addition, even if no crack occurs in the manufacturing process, it causes a problem of reliability in the process of using the light emitting diode thereafter. The thermal and electrical stress generated during the light emitting operation due to the supply of electric power causes a crack in the metal layer or the insulating layer formed on the via hole 140 formed outside the specific inclination angle a. The generated crack causes a malfunction of the light emitting diode and causes a decrease in luminance.

The via hole 140 preferably has an angle of 10 to 60 degrees with respect to the surface of the substrate 100 or the surface of the first semiconductor layer 110.

If the inclination angle a is less than 10 degrees, the area of the active layer 120 is reduced due to an excessively low slope. The reduction of the active layer area causes a decrease in luminance. In addition, a substantial area of the second semiconductor layer 130 is much lower than that of the first semiconductor layer 110. In general, the second semiconductor layer 130 has a p-type conductivity, and the first semiconductor layer 110 has an n-type conductivity. In the light emitting operation, the first semiconductor layer 110 supplies electrons to the active layer 120, and the second semiconductor layer 130 supplies holes to the active layer 120. The improvement in the luminous efficiency tends to be dependent on the uniform and smooth supply of holes rather than the supply of electrons. Therefore, an excessive reduction in the area of the second semiconductor layer 130 may cause a decrease in luminous efficiency. In addition, when the inclination angle a exceeds 60 degrees, cracks may occur in the metal layer or the insulating layer formed later due to the high inclination.

The shape and the number of the via holes 140 may be variously changed.

FIGS. 3 and 4 are a plan view and a cross-sectional view illustrating formation of lower electrodes on the second semiconductor layer of FIG. 1. Particularly, FIG. 4 is a cross-sectional view taken along the line A1-A2 of FIG.

3 and 4, the lower electrodes 151, 152, 153, and 154 are formed in a region except for the via hole 140, and through the formation of the lower electrodes 151, 152, 153, and 154 A plurality of cell areas 161, 162, 163, and 164 may be defined. Further, the lower electrodes 151, 152, 153, and 154 may be formed using a lift-off process used in forming the metal electrode. For example, a photoresist is formed in an isolation region except the imaginary cell regions 161, 162, 163, and 164 and an area where the via hole 140 is formed, and a metal layer is formed through normal thermal evaporation or the like. Thereafter, the photoresist is removed to form lower electrodes 151, 152, 153, and 154 on the second semiconductor layer 130. The lower electrodes 151, 152, 153, and 154 may be formed of any metal that performs ohmic contact with the second semiconductor layer 130. The lower electrodes 151, 152, 153, and 154 may include Ni, Cr, or Ti, and may be formed of a composite metal layer of Ti / Al / Ni / Au.

The lower electrodes 151, 152, 153, and 154 may have a thickness in the range of 2000 Å to 10000 Å. When the thickness of the lower electrodes 151, 152, 153, and 154 is less than 2000 angstroms, reflection of light from the lower electrodes 151, 152, 153, and 154 toward the substrate 100 is not smooth, , 152, 153, and 154 is generated. When the thickness of the lower electrodes 151, 152, 153, and 154 exceeds 10000 angstroms, an excessive time is consumed in the lower electrode forming process such as thermal evaporation.

4, the side surfaces of the lower electrodes 151, 152, 153, and 154 located on the upper portion of the second semiconductor layer 120 are in contact with the upper surface of the second semiconductor layer 130 in a range of 10 degrees to 45 degrees And can have an inclination angle b. When the inclination angle b of the lower electrodes 151, 152, 153, and 154 is less than 10 degrees, the efficiency of reflection of light is reduced due to a very gentle inclination. In addition, there arises a problem that the uniformity of the thickness on the surface of the lower electrode can not be secured due to the low inclination angle. If the inclination angle b of the lower electrodes 151, 152, 153, and 154 exceeds 45 degrees, cracks may be generated in the film formed later due to the high inclination angle.

The adjustment of the inclination angle b of the lower electrode 151, 152, 153, 154 with respect to the surface of the second semiconductor layer 130 can be performed by adjusting the angle of the substrate with respect to the arrangement of the substrate, Can be achieved through changes.

The region where four lower electrodes 151, 152, 153, and 154 are formed in FIGS. 3 and 4 defines four cell regions 161, 162, 163, and 164. The second semiconductor layer 130 is exposed in the spacing space between the cell regions 161, 162, 163, The number of the cell regions 161, 162, 163, and 164 may correspond to the number of the light emitting diodes included in the array to be formed. Therefore, the number of cell regions can be changed variously.

4, the lower electrodes 151, 152, 153 and 154 are depicted as being separated in the same cell region 161, 162, 163 and 164, It is a phenomenon that occurs according to the cutting. 3, the lower electrodes 151, 152, 153, and 154 formed on the same cell regions 161, 162, 163, and 164 are physically connected. Therefore, the lower electrodes 151, 152, 153, and 154 formed on the same cell region are electrically short-circuited despite the formation of the via hole 140.

FIG. 5 is a plan view showing a state in which cell regions are separated from the structure of FIG. 3, FIG. 6 is a cross-sectional view taken along line A 1 -A 2 of FIG. 5, and FIG. 7 is a perspective view of a plan view of FIG. .

Referring to FIGS. 5, 6 and 7, a mesa etch region is formed through a mesa etch for a spacing space between four cell regions 161, 162, 163, and 164. The substrate 100 is exposed to the mesa etching region through the mesa etching. Therefore, the four cell regions 161, 162, 163, and 164 are completely electrically separated from each other. If the buffer layer is interposed between the substrate 100 and the first semiconductor layer 110 in FIGS. 1 to 4, the buffer layer may remain in the separation process of the cell regions 161, 162, 163, and 164 have. However, the buffer layer between the cell regions 161, 162, 163, and 164 may be removed through the mesa etching in order to completely separate the cell regions 161, 162, 163, and 164.

The sides of the first semiconductor layer 110, the active layer 120, the second semiconductor layer 130, and the lower electrodes 151, 152, 153, and 154 are exposed through the mesa etching. The exposed sides may have an inclination angle c of 10 to 60 degrees with respect to the surface of the substrate 100. Adjustment of the inclination angle c of the exposed side faces can be achieved by adjusting the angle of the substrate with respect to the direction of the advancement of the etchant.

In addition, when the inclination angle c of the films exposed through the mesa etching is less than 10 degrees, the light incidence area may be reduced due to a low inclination, and the light efficiency may be lowered. When the inclination angle c is greater than 60 degrees, the thickness of the film formed later may be uneven due to a high inclination angle, or cracks may occur. This is a cause of lowering the reliability of the device.

Further, the range of the inclination angle c of the films exposed through the mesa etching affects the reflection of light by the metal layer formed in the subsequent process. For example, if a metal layer is formed on the sidewall of the film exposed through the mesa etching and the inclination angle c is less than 10 degrees, the light formed in the active layer is scattered without being reflected to a predetermined range with respect to the substrate. Also, even if the inclination angle c exceeds 60 degrees, reflection of light does not progress to a predetermined region, and scattering occurs.

The first semiconductor layers 111, 112, 113, 114 and the active layer (not shown) are formed for each of the cell regions 161, 162, 163, 164 through the separation process between the respective cell regions 161, 162, 163, The second semiconductor layers 131, 132, 133 and 134 and the lower electrodes 151, 152, 153 and 154 are formed. Accordingly, the first lower electrode 151 is exposed on the first cell region 161, and the first semiconductor layer 111 is exposed through the via hole 140. The second lower electrode 152 is exposed on the second cell region 162 and the first semiconductor layer 112 is exposed through the via hole 140. The third lower electrode 153 and the first semiconductor layer 113 are exposed on the third cell region 163 and the fourth lower electrode 154 and the first semiconductor layer 114 ) Is exposed.

In the present invention, the light emitting diode includes a structure in which the first semiconductor layers 111, 112, 113 and 114, the active layers 121, 122, 123 and 124 and the second semiconductor layers 131, 132, 133 and 134 are stacked Quot; Therefore, one light emitting diode is formed in one cell region. When the first semiconductor layers 111, 112, 113 and 114 have an n-type conductivity and the second semiconductor layers 131, 132, 133 and 134 have a p-type conductivity, The lower electrodes 151, 152, 153 and 154 formed on the second semiconductor layers 131, 132, 133 and 134 may be referred to as an anode electrode of the light emitting diode.

8 is a plan view showing a first interlayer insulating film formed on the entire surface of the structures of FIGS. 5 to 7 and partially exposing the first semiconductor layer and the lower electrode in each cell region.

9 to 12 are cross-sectional views of the plan view of FIG. 8 taken along a specific line. 8 is a cross-sectional view taken along line C1-C2 in FIG. 8, and FIG. 11 is a cross-sectional view taken along line D1-D2 in FIG. 12 is a cross-sectional view taken along line E1-E2 of the plan view of FIG. 8. FIG.

First, a first interlayer insulating film 170 is formed on the structures of FIGS. In addition, a part of the first semiconductor layers 111, 112, 113, 114 and the lower electrodes 151, 152, 153, 154 under the via hole is exposed through patterning.

For example, in the first cell region 161, two preformed via holes are opened to expose the first semiconductor layer 111, and a portion of the first lower electrode 151 formed on the formed second semiconductor layer 131 Is exposed. The first semiconductor layer 112 exposed through the previously formed via hole is exposed in the second cell region 162 and the second semiconductor layer 112 is etched through a portion of the first interlayer insulating film 170, Some are exposed. In addition, the first semiconductor layer 113 is exposed through the via hole in the third cell region 163, and a part of the third lower electrode 153 is exposed through etching of a part of the first interlayer insulating film 170 . In the fourth cell region 164, the first semiconductor layer 114 is exposed through the via hole, and a part of the fourth lower electrode 154 is exposed through etching of a part of the first interlayer insulating film 170.

8 to 12, a first interlayer insulating film 170 is formed on the entire surface of the substrate, and a first semiconductor layer 111 (not shown) in the via hole is formed for each of the cell regions 161, 162, 163, Portions of the lower electrodes 151, 152, 153 and 154 on the second semiconductor layers 131, 132, 133 and 134 are exposed. And the remaining region is shielded by the first interlayer insulating film 170.

The first interlayer insulating layer 170 may be formed of an insulating material having predetermined light transmittance. For example, the first interlayer insulating film 170 may include SiO2.

In addition, the first interlayer insulating layer 170 may have a thickness of 2000 ANGSTROM to 20000 ANGSTROM.

If the thickness of the first interlayer insulating film 170 is less than 2000 ANGSTROM, it is difficult to secure the insulating property due to the low thickness. Particularly, when the first interlayer insulating film 170 is formed on the side wall of the via hole 140 or the mesa region, since the first interlayer insulating film 170 has a constant slope, insulation breakdown may occur in the first interlayer insulating film 170 having a low thickness.

If the thickness of the first interlayer insulating film 170 exceeds 20000 angstroms, the selective etching process for the first interlayer insulating film 170 becomes difficult. For example, a portion of the first semiconductor layer and the lower electrodes of the via hole 140 should be exposed. For this purpose, the entire surface of the first interlayer insulating layer 170 and the selective etching process are performed. For the selective etching process, application and patterning of the photoresist are performed. In addition, etching is performed on the open region by the remaining photoresist pattern. If the thickness of the first interlayer insulating film 170 exceeds 20000 angstroms, the photoresist pattern acting as an etch mask in the step of selectively etching the first interlayer insulating film 170 can also be removed. Thus, a process error occurs in which an etching at an undesired site can be performed.

In addition, the first interlayer insulating film 170 may have an inclination angle d of 10 to 60 degrees with respect to the lower electrode surface exposed by selective etching. 9, the side surface of the interlayer insulating film 170, which is located above the lower electrodes 151, 152, 153, and 154, is partially exposed from the upper surface of the lower electrodes 151, 152, 153, The angle?

If the inclination angle d of the first interlayer insulating film 170 is less than 10 degrees, there is a problem that the area of the exposed lower electrode surface is reduced or the substantial thickness of the first interlayer insulating film 170 is reduced, do. That is, in the case of the first interlayer insulating film 170, the lower electrode is electrically insulated from other conductive films formed on the first interlayer insulating film 170. Therefore, the first interlayer insulating film 170 should have a sufficient thickness, and the lower electrode must be exposed with a certain area for other electrical connection. If the first interlayer insulating film 170 has a very low inclination, the area of the lower electrode exposed for realizing the first interlayer insulating film 170 of a constant thickness must be reduced. In addition, when the area of the lower electrode to be exposed is desired to be equal to or larger than a predetermined value, dielectric breakdown due to the first interlayer insulating film 170 having a low thickness due to low inclination may occur.

If the inclination angle d of the first interlayer insulating film 170 is more than 60 degrees, if another film quality is formed on the first interlayer insulating film 170, the quality of the other film quality may be degraded due to a rapid inclination angle Is generated.

Adjustment of the inclination angle of the first interlayer insulating film 170 can be achieved by adjusting the angle of etching in the partial etching process of the first interlayer insulating film 170 formed on the lower electrode.

13 is a plan view showing top electrodes formed on the structure shown in Figs. 8 to 12. Fig. 14 to 17 are cross-sectional views of the plan view of FIG. 13 taken along a specific line. 13 is a cross-sectional view taken along the line C1-C2 in FIG. 13, and FIG. 16 is a cross-sectional view taken along line D1-D2 in FIG. 17 is a cross-sectional view of the plan view of FIG. 13 taken along line E1-E2.

Referring to FIG. 13, upper electrodes 181, 182, 183 and 184 are formed. The upper electrodes 181, 182, 183 and 184 are divided into four regions. For example, the first upper electrode 181 is formed over a portion of the first cell region 161 and the second cell region 162. Also, the second upper electrode 182 is formed over a portion of the second cell region 162 and a portion of the third cell region 163. The third upper electrode 183 is formed over a portion of the third cell region 163 and a portion of the fourth cell region 164 while the fourth upper electrode 184 is formed over a portion of the fourth cell region 164 . Thus, each of the upper electrodes 181, 182, 183, and 184 is formed to shield the spacing space between adjacent cell regions. The upper electrodes 181, 182, 183, and 184 may cover 30% or more, more than 50%, or 90% or more of the spacing space between cell areas. However, since the upper electrodes 181, 182, 183 and 184 are spaced apart from each other, the upper electrodes 181, 182, 183 and 184 cover less than 100% of the area between the light emitting diodes.

The entire upper electrodes 181, 182, 183, and 184 may occupy 30% or more of the total area of the LED array, and more than 50% or 90% or more of the total area of the LED array. Since the upper electrodes 181, 182, 183, and 184 are spaced apart from each other, they occupy less than 100% of the total area of the LED array. In addition, the upper electrodes 181, 182, 183 and 184 have a plate or sheet shape with a width-to-width ratio in the range of 1: 3 to 3: 1. Further, at least one of the upper electrodes 181, 182, 183, and 184 has a greater width or width than the width or width of the corresponding light emitting diode (cell region).

14, a first upper electrode 181 is formed on the first semiconductor layer 111 formed on the first interlayer insulating film 170 of the first cell region 161 and opened through a via hole . The first upper electrode 181 exposes a portion of the first lower electrode 151 of the first cell region 161 and the second lower electrode 152 of the second cell region 162 .

The second upper electrode 182 is formed on the first semiconductor layer 112 exposed through the via hole of the second cell region 162 while being physically separated from the first upper electrode 181, The first interlayer insulating film 170 is formed.

14, the first upper electrode 181 electrically connects the first semiconductor layer 111 of the first cell region 161 and the second semiconductor layer 132 of the second cell region 162. The second lower electrode 152 on the second cell region 162 is entirely electrically short-circuited in one cell region despite the presence of the via hole. The first semiconductor layer 111 of the first cell region 161 is electrically connected to the second semiconductor layer 132 of the second cell region 162 through the second lower electrode 152.

15, the second upper electrode 182 is formed on the first semiconductor layer 112 exposed through the via hole of the second cell region 162, and the third lower electrode 182 of the third cell region 163, (153).

The third upper electrode 183 physically separated from the second upper electrode 182 is formed on the first semiconductor layer 113 exposed through the via hole of the third cell region 163.

The second upper electrode 182 is electrically connected to the first semiconductor layer 112 exposed through the via hole of the second cell region 162 and the third lower electrode of the third cell region 163 153, respectively. Therefore, the first semiconductor layer 112 of the second cell region 162 can maintain the same potential as the second semiconductor layer 133 of the third cell region 163.

16, the third upper electrode 183 is formed on the first semiconductor layer 113 exposed through the via hole of the third cell region 163, and the fourth lower electrode 183 of the fourth cell region 164 Electrode 154 as shown in Fig. Therefore, the first semiconductor layer 113 of the third cell region 163 and the second semiconductor layer 134 of the fourth cell region 164 are electrically connected.

The fourth upper electrode 184 physically separated from the third upper electrode 183 is electrically connected to the first semiconductor layer 114 exposed through the via hole of the fourth cell region 164.

Referring to FIG. 17, a fourth upper electrode 184 is formed on the first semiconductor layer 114 exposed through the via hole of the fourth cell region 164. The first upper electrode 181 physically separated from the fourth upper electrode 184 is formed on the first semiconductor layer 111 exposed through the via hole on the first cell region 161, A portion of the first lower electrode 151 of the region 161 is exposed.

13 to 17, the first semiconductor layer 111 of the first cell region 161 and the second semiconductor layer 132 of the second cell region 162 are connected to the first upper electrode 181 ) To form an equipotential. The first semiconductor layer 112 of the second cell region 162 and the second semiconductor layer 133 of the third cell region 163 form an equal potential through the second upper electrode 182. The first semiconductor layer 113 of the third cell region 163 forms an equal potential with the second semiconductor layer 134 of the fourth cell region 164 through the third upper electrode 183. The first lower electrode 151 electrically connected to the second semiconductor layer 131 in the first cell region 161 is exposed. Of course, the formation of the equipotential may be accomplished by changing the contact resistances of the upper electrodes 181, 182, 183 and 184 and the upper electrodes 181, 182, 183 and 184 and the lower electrodes 151, 152, 153 and 154 It is assumed that an ideal electrical connection is made in the ignored state. Therefore, in the actual operation of the device, a voltage drop due to resistance components of the upper electrodes 181, 182, 183, and 184 and the lower electrodes 151, 152, 153, and 154,

The upper electrodes 181, 182, 183, and 184 may be any material that can form an ohmic contact with the first semiconductor layers 111, 112, 113, and 114. The upper electrodes 181, 182, 183, and 184 may be used as the material that can form ohmic contact with the lower electrodes 151, 152, 153, and 154 made of metal. Accordingly, the upper electrodes 181, 182, 183, and 184 may include a metal layer including Ni, Cr, Ti, Rh, or Al, or a conductive oxide layer such as ITO as an ohmic contact layer.

In order to reflect light generated from the active layers 121, 122, 123 and 124 of the respective cell regions 161, 162, 163 and 164 toward the substrate 100, the upper electrodes 181, 182 and 183 , 184 may comprise a reflective layer such as Al, Ag, Rh or Pt. In particular, light generated in each of the active layers 121, 122, 123, and 124 is reflected toward the substrate 100 from the lower electrodes 151, 152, 153, and 154. The light transmitted through the spacing space between the cell regions 161,162, 163 and 164 also includes the upper electrodes 181,182, < RTI ID = 0.0 > 182, < / RTI & 183 and 184, respectively.

The thickness of the upper electrodes 181, 182, 183, and 184 may range from 2000 Å to 10000 Å. If the thickness of the upper electrodes 181, 182, 183 and 184 is less than 2000 angstroms, reflection of light from the upper electrodes 181, 182, 183 and 184 toward the substrate 100 is not smooth, , 182, 183, and 184 are generated. If the thickness of the upper electrodes 181, 182, 183, and 184 exceeds 10000 angstroms, an excessive time is consumed in the upper electrode forming process such as thermal evaporation.

14, side surfaces of the upper electrodes 181, 182, 183, and 184 located on the upper portion of the first interlayer insulating film 170 may be in contact with the upper surface of the first interlayer insulating film 170, The inclination angle e. When the inclination angle e of the upper electrodes 181, 182, 183 and 184 is less than 10 degrees, the efficiency of light reflection is reduced due to a very gentle slope. In addition, there arises a problem that the thickness uniformity on the surface of the upper electrode can not be ensured due to the low inclination angle. If the inclination angle e of the upper electrodes 181, 182, 183 and 184 exceeds 45 degrees, cracks may be generated in the film formed later due to the high inclination angle.

The adjustment of the inclination angle e of the upper electrodes 181, 182, 183 and 184 with respect to the surface of the first interlayer insulating film 170 can be performed by adjusting the angle of the substrate with respect to the arrangement of the substrate and the direction of the metal atoms Can be achieved through changes.

When the first semiconductor layers 111, 112, 113 and 114 have an n-type conductivity and the second semiconductor layers 131, 132, 133 and 134 have a p-type conductivity, May be modeled as a cathode electrode of a light emitting diode and the cathode electrode may be simultaneously modeled as a wiring connected to a lower electrode which is an anode electrode of a light emitting diode formed in an adjacent cell region. That is, in the light emitting diode formed on the cell region, the upper electrode may be modeled as a wiring which is electrically connected to the anode electrode of the light emitting diode of the adjacent cell region while forming the cathode electrode.

Fig. 18 is a perspective view showing the plan view of Fig. 13. Fig.

Referring to FIG. 18, the first to third upper electrodes 181 to 183 are formed over at least two cell regions. Thus, the spacing space between adjacent cell regions is shielded. In the case of the upper electrodes, light that may leak between adjacent cell regions is reflected through the substrate, and is electrically connected to the first semiconductor layer of each cell region. And is electrically connected to the second semiconductor layer of the adjacent cell region.

19 is an equivalent circuit diagram modeling the structures of FIGS. 13 to 18 according to an embodiment of the present invention.

Referring to Fig. 19, four light emitting diodes D1, D2, D3, and D4 and a wiring relationship therebetween are disclosed.

The first light emitting diode D1 is formed in the first cell region 161, the second light emitting diode D2 is formed in the second cell region 162, the third light emitting diode D3 is formed in the third cell region 163, And the diode D4 is formed in the fourth cell region 164. The first semiconductor layers 111, 112, 113 and 114 of the respective cell regions 161, 162, 163 and 164 are modeled as n-type semiconductors and the second semiconductor layers 131, 132, Is modeled as a p-type semiconductor.

The first upper electrode 181 is electrically connected to the first semiconductor layer 111 of the first cell region 161 and extends to the second cell region 162, And is electrically connected to the semiconductor layer 132. Accordingly, the first upper electrode 181 is modeled as wiring connecting the cathode terminal of the first light emitting diode D1 and the anode terminal of the second light emitting diode D2.

The second upper electrode 182 is modeled as wiring connecting between the cathode terminal of the second light emitting diode D2 and the anode terminal of the third light emitting diode D3 and the third upper electrode 183 is modeled as a wire connecting the anode terminal of the third light emitting diode D3 The cathode terminal and the anode terminal of the fourth light emitting diode D4. In addition, the fourth upper electrode 184 is modeled as wiring forming the cathode terminal of the fourth light emitting diode D4.

Accordingly, the anode terminal of the first light emitting diode D1 and the cathode terminal of the fourth light emitting diode D4 are electrically opened to the external power source, and the remaining light emitting diodes D2 and D3 form a series connection structure. In order to perform the light emitting operation, the anode terminal of the first light emitting diode D1 is connected to the positive power supply voltage V + and the cathode terminal of the fourth light emitting diode D4 is connected to the negative power supply voltage V-. Therefore, the light emitting diode connected to the positive power supply voltage V + may be referred to as an input light emitting diode, and the light emitting diode connected to the negative power supply voltage V- may be referred to as an output light emitting diode.

In the above-described structure, in the cell region where the cathode terminal connected to the negative power supply voltage V- is formed in the connection relation of the plurality of light emitting diodes, the upper electrode that shields only a part of the cell region is formed. An upper electrode for shielding between cell regions electrically connected to each other is formed in the cell region forming the other connection relationship.

FIG. 20 is a plan view showing a plan view of FIG. 13 in which a second interlayer insulating film is applied to a front surface of a structure, a part of a first lower electrode of a first cell region is exposed and a part of a fourth upper electrode of a fourth cell region is exposed to be.

Referring to FIG. 20, the upper electrodes are shielded through the second interlayer insulating film 190, and a part of the first lower electrode 151 and a part of the fourth upper electrode 184 are exposed. This means that only the anode terminal of the first light emitting diode D1 is exposed and only the cathode terminal of the fourth light emitting diode is exposed in FIG.

20 is a cross-sectional view taken along the line B 1 -B 2 in FIG. 20, FIG. 22 is a cross-sectional view taken along line C 1 -C 2 of FIG. 20, FIG. 24 is a cross-sectional view of the plan view of FIG. 20 taken along line E1-E2.

Referring to FIG. 21, the first lower electrode 151 electrically connected to the second semiconductor layer 131 in the first cell region 161 is opened. And the remaining region is covered with the second interlayer insulating film 190 over the second cell region 162.

Referring to FIG. 22, the second cell region 162 and the third cell region 163 are completely covered with the second interlayer insulating film 190.

23 and 24, the fourth upper electrode 184 of the fourth cell region 164 is exposed, and the first lower electrode 151 of the first cell region 161 is exposed.

Exposure of the fourth upper electrode 184 and the first lower electrode 151 is performed through selective etching of the second interlayer insulating film 190.

The second interlayer insulating film 190 is selected from an insulating material capable of protecting the underlying film from the external environment. Particularly, SiN, which has an insulating property and can block changes in temperature and humidity, can be used.

The thickness of the second interlayer insulating film 190 may have a predetermined range. For example, when the second interlayer insulating film 190 has SiN, the second interlayer insulating film 190 may have a thickness of 2000 ANGSTROM to 20000 ANGSTROM.

If the thickness of the second interlayer insulating film 190 is less than 2000 angstroms, it is difficult to secure the insulating characteristics due to the low thickness. In addition, the low thickness results in a problem of protecting the underlying film from external moisture or penetration of chemicals.

When the thickness of the second interlayer insulating film 190 exceeds 20000 angstroms, it is difficult to selectively etch the second interlayer insulating film 190 through the formation of the photoresist pattern. That is, in the etching process, the photoresist pattern acts as an etch mask, and the second interlayer insulating layer 190 is etched selectively with the selective etching of the second interlayer insulating layer 190 due to the excessive thickness of the second interlayer insulating layer 190. If the thickness of the second interlayer insulating film 190 is excessive, a problem may occur that the photoresist pattern is removed before the selective etching of the second interlayer insulating film 190 is completed and the etching is performed at an undesired position.

The second interlayer insulating film 190 may have an inclination angle f of 10 degrees to 60 degrees with respect to the surface of the fourth upper electrode 184 or the first lower electrode 151 exposed at the bottom. 24, the side surface of the second interlayer insulating film 190 located above the fourth upper electrode 184 or the first lower electrode 151 may be formed on the upper surface or the lower surface of the fourth upper electrode 184, The electrode 151 may have an inclination angle f with respect to the upper surface.

If the inclination angle f of the second interlayer insulating film 190 is less than 10 degrees, the substantial area of the exposed fourth upper electrode 184 or the first lower electrode 151 decreases. Further, if the area of the exposed portion is increased so as to secure a substantial area, there arises a problem that the insulation property can not be secured due to the low inclination angle.

If the inclination angle f of the second interlayer insulating film 190 is more than 60 degrees, the quality of another film formed on the second interlayer insulating film 190 may be deteriorated or a crack may be generated in the film due to a sharp profile or an inclination . In addition, when the light emitting operation is continuously performed due to the supply of electric power, the characteristics are degraded.

FIG. 25 is a plan view showing a first pad and a second pad formed on the structure of FIG. 20. FIG.

Referring to FIG. 25, the first pad 210 may be formed over the first cell region 161 and the second cell region 162. The first pad 210 achieves electrical contact with the first lower electrode 151 of the first cell region 161 exposed in FIG.

The second pad 220 may be spaced apart from the first pad 210 by a predetermined distance and may extend over the third cell region 163 and the fourth cell region 164. The second pad 220 is electrically connected to the fourth upper electrode 184 of the fourth cell region 164 exposed in FIG.

25 is a cross-sectional view taken along the line C1-C2 in FIG. 25, and FIG. 28 is a cross-sectional view taken along the line D1-D2 in the plan view of FIG. And Fig. 29 is a cross-sectional view of the plan view of Fig. 25 taken along line E1-E2.

Referring to FIG. 26, a first pad 210 is formed over a first cell region 161 and a second cell region 162. The first pad 210 is formed on the first lower electrode 151 exposed in the first cell region 161. And is formed on the second interlayer insulating film 190 in the remaining region. Accordingly, the first pad 210 is electrically connected to the second semiconductor layer 131 of the first cell region 161 through the first lower electrode 151.

Referring to FIG. 27, a first pad 210 is formed on the second cell region 162 and a second pad 220 is formed on the third cell region 163 apart from the first pad 210 . The first pad 210 or the second pad 220 in the second cell region 162 and the third cell region 163 are electrically disconnected from the lower electrode or the upper electrode.

Referring to FIG. 28, a second pad 220 is formed over the third cell region 163 and the fourth cell region 164. In particular, the fourth upper electrode 184 opened in the fourth cell region 164 and the second pad 220 are electrically connected. Accordingly, the second pad 220 is electrically connected to the first semiconductor layer 114 of the fourth cell region 164.

29, a second pad 220 is formed on the fourth cell region 164 and a first pad 210 is formed on the first cell region 161 to be spaced apart from the second pad 220 . The first pad 210 is formed on the first lower electrode 151 of the first cell region 161 and is electrically connected to the second semiconductor layer 131.

Fig. 30 is a perspective view of the plan view of Fig. 25 taken along line C2-C3.

Referring to FIG. 30, the first semiconductor layer 113 of the third cell region 163 is electrically connected to the third upper electrode 183. The third upper electrode 183 shields the spaces between the third cell region 163 and the fourth cell region 164 and is electrically connected to the fourth lower electrode 154 of the fourth cell region 164. do. Also, the first pad 210 and the second pad 220 are spaced apart from each other and are formed on the second interlayer insulating film 190. Of course, as described above, the first pad 210 is electrically connected to the second semiconductor layer 131 of the first cell region 161, and the second pad 220 is electrically connected to the second semiconductor layer 131 of the fourth cell region 164 1 < / RTI >

The first pad 210 and the second pad 220 may have a first layer containing Ti, Cr or Ni and a second layer containing Al, Cu, Ag or Au on the first layer. Also, the first pad 210 and the second pad 220 may be formed using a lift-off process. Alternatively, a metal layer of a double layer or a single layer may be formed, and then a pattern may be formed through a conventional photolithography process, and may be formed by dry etching or wet etching using the metal layer as an etching mask. However, etchant during dry etching and wet etching can be set differently depending on the material of the metal to be etched.

The first pad 210 and the second pad 220 may be simultaneously formed through a single process.

A pad barrier layer (not shown) of conductive material may be formed on the first pad 210 or the second pad 220. The pad barrier layer is provided to prevent diffusion of metals that may occur during bonding or soldering operations on the pads 210 and 220. For example, during the bonding or soldering operation, the phenomenon that the tin atoms contained in the bonding metal or the soldering material diffuses into the pads 210 and 220 to increase the resistivity of the pads is prevented. For this, the pad barrier layer may be composed of Cr, Ni, TiW, TiW, Mo, Pt, or a composite layer thereof.

Referring to the modeling of FIG. 19, the first semiconductor layers 111, 112, 113, and 114 of each cell region are modeled as n-type semiconductors, and the second semiconductor layers 131, 132, 133, Type semiconductor. The first lower electrode 151 formed on the second semiconductor layer 131 of the first cell region 161 is modeled as an anode electrode of the first light emitting diode D1. Accordingly, the first pad 210 may be modeled as a wiring connected to the anode electrode of the first light emitting diode D1. The fourth upper electrode 184 electrically connected to the first semiconductor layer 114 of the fourth cell region 164 is modeled as a cathode electrode of the fourth light emitting diode D4. Accordingly, the second pad 220 can be understood as a wiring connected to the cathode electrode of the fourth light emitting diode D4.

Through this, an array structure in which four light emitting diodes D1 to D4 are connected in series is formed, and electrical connection to the outside is achieved through two pads 210 and 220 formed on one substrate 100. [

19, the first lower electrode 152 of the first light emitting diode D1 connected to the positive power supply voltage V + is electrically connected to the first pad 210, and the first power supply voltage V- The fourth upper electrode 184 of the fourth light emitting diode D4 is electrically connected to the second pad 220. [

In the present invention, four light emitting diodes are formed in a mutually separated form, and an anode terminal of one light emitting diode is electrically connected to a cathode terminal of another light emitting diode through a lower electrode and an upper electrode. However, according to the present embodiment, four light emitting diodes are only one embodiment, and various numbers of light emitting diodes can be formed according to the present invention.

31 is a circuit diagram modeling 10 LEDs connected in series according to an embodiment of the present invention.

Referring to FIG. 31, ten cell areas 301 to 310 are defined using the process disclosed in FIG. The first semiconductor layer, the active layer, the second semiconductor layer, and the lower electrode in each of the cell regions 301 to 310 are separated from other cell regions. Each lower electrode is formed on the second semiconductor layer to form an anode electrode of the light emitting diodes D1 to D10.

Subsequently, the first interlayer insulating film and the upper electrodes are formed using the processes shown in FIGS. However, the formed upper electrodes shield the spacing space between adjacent cell regions and function as wiring to achieve an electrical connection between the anode electrodes of the adjacent light emitting diodes.

20 to 29, a lower electrode of the first light emitting diode D1, which is an input light emitting diode connected to the positive power supply voltage V + in the current path, is exposed, The upper electrode of the tenth light emitting diode D10, which is an output light emitting diode connected to the power supply voltage V- of the light emitting diode D10. Then, the first pad 320 is formed to connect the anode terminal of the first light emitting diode D1. Also, the second pad 330 is formed to connect the cathode terminal of the tenth light emitting diode D10.

In addition, the connection of the light emitting diodes may be composed of an array of a serial / parallel type.

32 is a circuit diagram modeling that light emitting diodes constitute an array in a linear / parallel form according to an embodiment of the present invention.

Referring to FIG. 32, the plurality of light emitting diodes D1 to D8 have a series connection and are connected in parallel with adjacent light emitting diodes. Each of the light emitting diodes D1 to D8 is formed independently of each other through the definition of the cell regions 401 to 408. [ As described above, the anode electrodes of the light emitting diodes D1 to D8 are formed through the lower electrode. Further, the wiring between the cathode electrode of the light emitting diodes D1 to D8 and the anode electrode of the adjacent light emitting diode is formed through formation of the upper electrode and proper wiring. However, the lower electrode is formed on the second semiconductor layer, and the upper electrode is formed to shield the spacing space between adjacent cell regions.

Finally, the first pad 410 to which the positive power supply voltage V + is supplied is electrically connected to the lower electrode formed on the second semiconductor layer of the first light emitting diode D1 or the third light emitting diode D3, and the negative power supply voltage V- The second pad 420 is electrically connected to the upper electrode, which is the cathode terminal of the sixth light emitting diode D6 or the eighth light emitting diode D8.

Accordingly, in FIG. 32, the input light emitting diodes correspond to the first light emitting diode D1 and the third light emitting diode D3, and the output light emitting diodes correspond to the sixth light emitting diode D6 and the eighth light emitting diode D8.

According to the present invention, the light generated in the active layer of each light emitting diode is reflected toward the substrate from the lower electrode and the upper electrode, and the flip chip type light emitting diodes are electrically connected to one substrate through the wiring of the upper electrode . The upper electrode is shielded from the outside through the second interlayer insulating film. The first pad to which the positive power supply voltage is supplied is electrically connected to the lower electrode of the light emitting diode which is connected closest to the positive power supply voltage. Also, a second pad to which a negative power supply voltage is supplied is electrically connected to an upper electrode of the light emitting diode connected closest to the negative power supply voltage.

Therefore, a complicated process of mounting two chips on an external power source through the wiring arranged on the submount substrate is achieved by mounting a plurality of chips on the submount substrate in the flip chip type. In addition, the spacing space between the cell areas can be shielded through the top electrode to maximize the reflection of light towards the substrate.

Further, the second interlayer insulating film protects a plurality of laminated structures disposed between the substrate and the second interlayer insulating film from external temperature, humidity, and the like. Therefore, a structure that can be directly mounted on the substrate without the intervention of another packaging means is realized.

In particular, since a plurality of light emitting diodes are implemented as a flip chip type on one substrate, there is an advantage that a commercial power supply can be directly used in a state in which a voltage drop, a level conversion, or a wave form conversion to a supplied commercial power supply is excluded .

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, This is possible.

100: substrate 111, 112, 113, 114: first semiconductor layer
121, 122, 123, 124: active layer 131, 132, 133, 134: second semiconductor layer
140: via hole 151: first lower electrode
152: second lower electrode 153: third lower electrode
154: fourth lower electrode 161: first cell region
162: second cell region 163: third cell region
164: fourth cell region 170: first interlayer insulating film
181: first upper electrode 182: second upper electrode
183: third upper electrode 184: fourth upper electrode
190: second interlayer insulating film 210: first pad
220: second pad

Claims (16)

Growth substrate;
A plurality of light emitting diodes arranged on the substrate, the plurality of light emitting diodes including a first semiconductor layer, an active layer and a second semiconductor layer, respectively;
A plurality of upper electrodes arranged on the plurality of light emitting diodes and formed of the same material as each other and electrically connected to the first semiconductor layers of the corresponding light emitting diodes;
A first interlayer insulating film disposed between the light emitting diodes and the upper electrodes;
Lower electrodes arranged on a second semiconductor layer of the light emitting diodes; And
A first pad and a second pad arranged on the upper electrodes,
Wherein at least one of the upper electrodes is electrically connected to a second semiconductor layer of an adjacent light emitting diode and the other of the upper electrodes is insulated from a second semiconductor layer of an adjacent light emitting diode,
The light emitting diodes are connected in series by the upper electrodes,
Wherein the first pad is electrically connected to the input light emitting diode among the series-connected light emitting diodes,
The second pad is electrically connected to the output LED of the series-connected light emitting diodes,
Wherein each of the light emitting diodes is separated by a mesa etch region exposing the substrate, the sides of the films exposed by the mesa etch have an inclination angle of 10 to 60 degrees relative to the substrate,
The lower electrode covering the upper portion of the second semiconductor layer,
Wherein the upper electrode is positioned above the plurality of light emitting diodes and the growth substrate,
At least a portion of the upper electrode is located on the lower electrode,
Wherein the upper electrode and the lower electrode reflect light. The method according to claim 1,
And the side surfaces of the upper electrodes located above the first interlayer insulating film include side surfaces having an inclination angle of 10 degrees to 45 degrees with respect to the upper surface of the first interlayer insulating film. The method of claim 2,
Wherein the upper electrode has a thickness within the range of 2000 ANGSTROM to 10,000 ANGSTROM. The method according to claim 1,
The first interlayer insulating layer exposes a part of the lower electrode on each light emitting diode,
And the upper electrode (s) electrically connected to the second semiconductor layer of the adjacent light emitting diode are connected to the exposed lower electrode through the first interlayer insulating film. The method according to claim 1,
And the side surfaces of the lower electrodes located above the second semiconductor layer each include a side surface having an inclination angle of 10 degrees to 45 degrees with respect to an upper surface of the second semiconductor layer. 5. The light emitting diode array of claim 4, wherein the thickness of the lower electrode is 2000 ANGSTROM to 10,000 ANGSTROM. The method according to claim 1,
Wherein a side surface of the first interlayer insulating film located at an upper portion of the exposed lower electrodes includes a side surface having an inclination angle of 10 to 60 degrees with respect to an upper surface of the lower electrode. The method of claim 7,
Wherein the first interlayer insulating layer has a thickness of 2000 ANGSTROM to 20000 ANGSTROM. The method of claim 4,
And a second interlayer insulating film covering the upper electrodes,
The second interlayer insulating layer exposes the lower electrode aligned on the second semiconductor layer of the input light emitting diode and the upper electrode connected to the first semiconductor layer of the output light emitting diode,
Wherein the first pad and the second pad are connected to the lower electrode and the upper electrode through the second interlayer insulating film, respectively. The method of claim 9,
Wherein a side surface of the second interlayer insulating film located above the upper electrode includes a side surface having an inclination angle of 10 degrees to 60 degrees with respect to an upper surface of the upper electrode. The light emitting diode array according to claim 9, wherein the second interlayer insulating film has a thickness of 2000 Å to 20000 Å. The method according to claim 1,
Wherein each of the light emitting diodes has a via hole exposing a part of the first semiconductor layer and the upper electrodes are connected to the first semiconductor layer of the corresponding light emitting diode through the via hole. The method of claim 12,
Wherein a side inclination angle of the films exposed through the via hole is within a range of 10 degrees to 60 degrees. The method according to claim 1,
Wherein the upper electrode occupies at least 30% and less than 100% of the total area of the light emitting diode array. The method according to claim 1,
Wherein the upper electrode has a plate or sheet shape having a width-to-width ratio within a range of 1: 3 to 3: 1. The method according to claim 1,
Wherein at least one of the upper electrodes has a width or width greater than the width or width of the corresponding light emitting diode.

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