KR102429939B1 - Backlight module with mjt led and backlight unit having the same - Google Patents

Abstract

A backlight unit according to an embodiment of the present invention includes a printed circuit board including a plurality of blocks; and a backlight module including a plurality of MJT LEDs disposed on the plurality of blocks, wherein the MJT LEDs include: a growth substrate; a plurality of light emitting cells arranged on the substrate and each including a first semiconductor layer, an active layer, and a second semiconductor layer; a plurality of upper electrodes arranged on the plurality of light emitting cells, formed of the same material as each other, and electrically connected to a first semiconductor layer of each corresponding light emitting cell; and a first pad and a second pad aligned on the upper electrodes, wherein at least one of the upper electrodes is electrically connected to a second semiconductor layer of an adjacent light emitting cell, and the other of the upper electrodes is Insulated from a second semiconductor layer of an adjacent light emitting cell, the light emitting cells are connected in series by the upper electrodes, the first pad is electrically connected to an input light emitting cell among the series connected light emitting cells, and the second A pad is electrically connected to an output light emitting cell among the series-connected light emitting cells, each of the light emitting cells is separated by a mesa etch region exposing the substrate, and the operation of each of the plurality of MJT LEDs is independently controlled can be

Description

A backlight module using MJT LED and a backlight unit including the same

The present invention relates to a backlight module using a multi-cell (Multi Junction Technology: MJT) LED and a backlight unit including the same.

A liquid crystal display implements an image by controlling the transmittance of a backlight light source. Conventionally, a Cold Cathode Fluorescent Lamp (CCFL) has been mainly used as a backlight light source, but a light emitting diode (hereinafter referred to as 'LED') is widely used due to various advantages such as power consumption, lifespan, and environmental characteristics.

There are edge-type backlight units and direct-type backlight units according to the positions of LEDs as a backlighting method for liquid crystal displays. The edge type backlight unit places LEDs on the side of the light guide plate and backlights the liquid crystal panel using the light guide plate with the light incident from the light source. It is advantageous and also has the advantage of being able to develop low-power products. However, the edge-type backlight unit is difficult to overcome the contrast between the corner portion and the center region of the liquid crystal display, and there is a limit in realizing high quality.

On the other hand, the direct backlight unit adopts a method of irradiating light directly to the front surface of the liquid crystal panel from a surface light source located at the bottom of the liquid crystal panel and having an area approximately equal to that of the liquid crystal panel. It has the advantage of being able to overcome it and realizing high quality.

However, in the case of a direct-type backlight unit, when each LED does not evenly backlight a relatively large area, a large number of LEDs must be densely arranged, and thus power consumption increases. Furthermore, when there is a quality deviation between the LEDs, the liquid crystal panel is non-uniformly backlit, making it difficult to secure the uniformity of the screen.

In particular, in recent years, as liquid crystal panels are becoming larger, direct-type backlight units have also been enlarged, and accordingly, stability and reliability of the enlarged direct-type backlight units are deteriorated. Specifically, the LED backlight unit controls the driving current supplied to the plurality of LED groups, that is, the LED arrays through the plurality of LED driving circuits. As the size of the LED backlight unit increases, the LED driving circuits and the corresponding LED array their number has increased significantly. Accordingly, there are cases in which a plurality of LEDs or LED arrays arranged adjacent to each other are short-circuited. In this case, the driving circuits are damaged due to overcurrent, overvoltage, or overheating, thereby deteriorating stability or reliability of the backlight unit.

1 is a block diagram of a backlight unit using an LED according to the prior art. With reference to FIG. 1, the problems according to the prior art will be looked at in more detail. As shown in FIG. 1 , the backlight unit 1 according to the prior art includes a backlight control module 2 and a backlight module 5 .

The backlight control module 2 includes a driving power generating unit 3 that generates/outputs DC driving power using an input power Vin input from the outside, and a plurality of LED arrays 6a constituting the backlight module 5 . ~6n) is configured to include a driving control unit 4 for controlling each operation. The driving power generator 3 generally generates and outputs DC voltages such as 12V, 24V, and 48V as driving power.

On the other hand, the backlight module 5 is an optical unit for improving the efficiency of light emitted from the plurality of LED arrays 6a to 6n and the plurality of LED arrays 6a to 6n, each of which is configured by connecting a plurality of LEDs in series. (not shown) is included. In the prior art illustrated in FIG. 1 , the backlight module 5 is illustrated in which n LED arrays 6a to 6n, each including five LEDs connected in series, are connected in parallel to each other. At this time, the LED according to the prior art used generally has a forward voltage level between 3V and 6.5V, and thus, by connecting these general LEDs to the driving power generating unit 3 as described above to individually control/drive Since it is difficult to configure an LED array by connecting a plurality of LEDs in series, a method of driving/controlling each LED array is taken. In the backlight unit 1 according to the prior art, the driving control unit 4 controls the backlight module 5 by PWM control of the driving power supplied to the backlight module 5 according to the dimming signal Dim input from the outside. It may be configured to control the luminance of all the constituting LED arrays (6a to 6n). Alternatively, in the backlight unit 1 according to the prior art, the driving control unit 4 controls a driving current flowing through a specific LED array among the n LED arrays 6a to 6n according to a dimming signal Dim input from the outside. By adjusting the size of can be configured to control the brightness of a particular LED array.

The LED used in the backlight unit 1 according to the prior art is generally a single-cell LED, and has a device characteristic that is driven by a small voltage and a large current. For example, the single-cell LED as described above may operate with a driving current of 250 to 500 mA with a driving voltage of 3.6V. Therefore, in order to control the driving of the backlight module 5 composed of such a single-cell LED, the peripheral circuits including the driving control unit 4 according to the prior art must be composed of large-capacity electronic devices capable of handling large currents. Accordingly, there is a problem in that the manufacturing cost of the backlight unit 1 is increased. In addition, due to the high current driving characteristics of the conventional single-cell LED as described above, peripheral circuits including the driving control unit 4 are damaged, so that the stability or reliability of the backlight unit 1 is deteriorated. In addition, due to the high current driving characteristics of the single-cell LED, there is a problem in that power consumption increases and a droop phenomenon occurs.

An object of the present invention is to provide a backlight module capable of low current driving using an MJT LED having a plurality of light emitting cells and a backlight unit including the same.

In addition, the present invention enables the low current driving of the backlight module using the MJT LED as described above, thereby improving the stability and reliability of the driving circuit for controlling the driving of the backlight module, and reducing the manufacturing cost. It is another object to provide a backlight unit.

Another object of the present invention is to provide a backlight unit capable of improving power efficiency and light efficiency and preventing droop caused by high current driving by configuring a backlight module to be driven with a small current using an MJT LED. The purpose.

In addition, another object of the present invention is to provide a backlight unit capable of minimizing the number of required LEDs and driving control for each MJT LED by configuring a backlight module using the MJT LEDs as described above.

A backlight unit according to an embodiment of the present invention includes a printed circuit board including a plurality of blocks; and a backlight module including a plurality of MJT LEDs disposed on the plurality of blocks, wherein the MJT LEDs include: a growth substrate; a plurality of light emitting cells arranged on the substrate and each including a first semiconductor layer, an active layer, and a second semiconductor layer; a plurality of upper electrodes arranged on the plurality of light emitting cells, formed of the same material as each other, and electrically connected to a first semiconductor layer of each corresponding light emitting cell; and a first pad and a second pad aligned on the upper electrodes, wherein at least one of the upper electrodes is electrically connected to a second semiconductor layer of an adjacent light emitting cell, and the other of the upper electrodes is Insulated from a second semiconductor layer of an adjacent light emitting cell, the light emitting cells are connected in series by the upper electrodes, the first pad is electrically connected to an input light emitting cell among the series connected light emitting cells, and the second A pad is electrically connected to an output light emitting cell among the series-connected light emitting cells, each of the light emitting cells is separated by a mesa etch region exposing the substrate, and the operation of each of the plurality of MJT LEDs is independently controlled can be

The backlight unit further includes a first interlayer insulating film arranged between the light emitting cells and the upper electrodes, wherein the upper electrodes include side surfaces having an inclination angle of 10 degrees to 45 degrees with respect to the surface of the first interlayer insulating film can do.

The upper electrode may have a thickness within a range of 2000 Å to 10000 Å.

The backlight unit further includes lower electrodes arranged on a second semiconductor layer of each light emitting cell, wherein the first interlayer insulating film exposes a portion of the lower electrode on each light emitting cell, and the second semiconductor layer of the adjacent light emitting cell The upper electrode(s) electrically connected to may be connected to the exposed lower electrode through the first interlayer insulating layer.

Each of the lower electrodes may include a side surface having an inclination angle of 10 degrees to 45 degrees with respect to the surface of the second semiconductor layer.

The thickness of the lower electrode may be in the range of 2000 Å to 10000 Å.

The first interlayer insulating layer may include a side surface having an inclination angle of 10 degrees to 60 degrees with respect to the exposed lower electrode surface.

The first interlayer insulating layer may have a thickness of 2000 Å to 20000 Å.

The backlight unit further includes a second interlayer insulating film covering the upper electrodes, wherein the second interlayer insulating film is connected to the lower electrode aligned on the second semiconductor layer of the input light emitting cell and the first semiconductor layer of the output light emitting cell The upper electrode may be exposed, and the first pad and the second pad may be respectively connected to the lower electrode and the upper electrode through the second interlayer insulating layer.

The second interlayer insulating layer may include a side surface having an inclination angle of 10 degrees to 60 degrees with respect to the upper electrode surface.

The second interlayer insulating layer may have a thickness of 2000 Å to 20000 Å.

Each of the light emitting cells may have a via hole exposing a portion of the first semiconductor layer, and the upper electrodes may be connected to a first semiconductor layer of a corresponding light emitting cell through the via hole.

A side inclination angle of the layers exposed through the via hole may be in a range of 10 degrees to 60 degrees.

The upper electrode may occupy an area of 30% or more and less than 100% of the total area of the MJT LED.

The upper electrode may have a plate or sheet shape in which a ratio of width to width is in a range of 1:3 to 3:1.

At least one of the upper electrodes may have a width or a width greater than that of a corresponding light emitting cell.

Side surfaces of the layers exposed by the mesa etching may have an inclination angle of 10 degrees to 60 degrees with respect to the substrate.

The backlight unit further includes a backlight control module for providing a driving voltage to the plurality of MJT LEDs in the backlight module, the block including at least one MJT LED, wherein the backlight control module includes the plurality of MJT LEDs Each of these can be independently controlled.

The backlight control module may include a driving power generator; and a driving control unit.

The driving power generation unit independently provides the driving voltage to each of the plurality of MJT LEDs in the backlight module, and the driving controller performs PWM control according to a dimming signal of the backlight control module to dim the at least one MJT LED. It may be characterized in that the control is performed.

The driving controller may generate a dimming control signal in which a pulse width is modulated or a duty ratio is modulated.

The driving control unit may be configured to independently detect and control a driving current of each of the plurality of MJT LEDs in the backlight module.

The driving controller may perform dimming control of the at least one MJT LED by controlling a driving current of at least one MJT LED among the plurality of MJT LEDs according to a dimming signal.

A first pad of the MJT LED may be connected to the driving power generator, and a second pad of the MJT LED may be connected to a driving controller.

The backlight unit may further include an optical member disposed on the MJT LED or the substrate to correspond to the plurality of MJT LEDs.

Each of the plurality of blocks may include the one optical member.

The plurality of blocks may be M×N, and the plurality of blocks may constitute an M×N matrix arrangement.

At least one block among the plurality of blocks may include a plurality of the MJT LEDs.

The backlight unit further includes a plurality of FETs electrically connected to the plurality of MJT LEDs and an FET controller for controlling on and off of the FETs, wherein the number of the plurality of FETs is the plurality of FETs. It may be equal to the number of MJT LEDs.

The FET controller may include at least one of the plurality of FETs.

The number of FETs not included in the FET controller among the plurality of FETs may be less than the number of the plurality of MJT LEDs.

The FET controller may include all of the plurality of FETs.

According to embodiments of the present invention, by configuring the backlight module by using the MJT LED having a small current driving characteristic, it can be expected that the backlight module and the backlight unit including the same can be driven with a small current.

In addition, according to the embodiments of the present invention, the stability and reliability of the driving circuit for controlling the driving of the backlight module can be improved, and the effect of reducing the manufacturing cost can be expected.

In addition, according to embodiments of the present invention, power efficiency and light efficiency of the backlight unit may be improved, and an effect of preventing a droop phenomenon caused by driving a large current may be expected.

In addition, according to embodiments of the present invention, it can be expected that the number of LEDs required to configure the backlight module is minimized, and driving control is possible for each MJT LED constituting the backlight module.

1 is a block diagram of a backlight unit using an LED according to the prior art.
2 is a schematic block diagram of a backlight unit using an MJT LED according to an embodiment of the present invention.
3 is a schematic cross-sectional view for explaining an MJT LED module according to an embodiment of the present invention.
4 is a schematic perspective view for explaining an MJT LED according to an embodiment of the present invention.
5 is a schematic diagram for comparing backlight units according to an embodiment of the present invention.
6 and 7 are plan views and cross-sectional views illustrating via-holes formed in a plurality of stacked structures according to an embodiment of the present invention.
8 and 9 are plan views and cross-sectional views illustrating lower electrodes formed on the second semiconductor layer of FIG. 6 .
FIG. 10 is a plan view illustrating a state in which cell regions are separated with respect to the structure of FIG. 8 .
11 is a cross-sectional view taken along line A1-A2 in the plan view of FIG. 10 .
12 is a perspective view of the plan view of FIG. 10 .
13 is a plan view illustrating a first interlayer insulating film formed on the entire surface of the structures of FIGS. 10 to 12 and partially exposing a first semiconductor layer and a lower electrode in each cell region.
14 to 17 are cross-sectional views taken along a specific line in the plan view of FIG. 13 .
18 is a plan view illustrating upper electrodes formed on the structure illustrated in FIGS. 13 to 17 .
19 to 22 are cross-sectional views taken along a specific line in the plan view of FIG. 18 .
23 is a perspective view illustrating a plan view of FIG. 18 .
24 is an equivalent circuit diagram modeling the structures of FIGS. 18 to 23 according to a preferred embodiment of the present invention.
25 is a plan view showing a second interlayer insulating film applied to the entire surface of the structure in the plan view of FIG. 18 , part of the first lower electrode of the first cell region being exposed, and part of the fourth lower electrode of the fourth cell region being exposed; FIG. to be.
26 to 29 are cross-sectional views taken along a specific line in the plan view of FIG. 25 .
FIG. 30 is a plan view of the structure of FIG. 25 in which the first pad and the second pad are formed.
31 to 34 are cross-sectional views taken along a specific line in the plan view of FIG. 30 .
35 is a perspective view of the plan view of FIG. 30 cut along the line C2-C3.
36 is a circuit diagram modeled to connect ten light emitting cells in series according to an embodiment of the present invention.
37 is a circuit diagram modeling a case in which light emitting cells are configured in a series/parallel form according to an embodiment of the present invention.
38 is a cross-sectional view for explaining various modified examples of the optical member.
39 is a cross-sectional view of an optical member for explaining an MJT LED module according to another embodiment of the present invention.
40 is a cross-sectional view for explaining the dimensions of the MJT LED module used in the simulation.
41 is a graph for explaining the shape of the optical member of FIG.
FIG. 42 shows a light beam propagation direction of the optical member of FIG. 40 .
43 is a graph showing the illuminance distribution. (a) shows the illuminance distribution of the MJT LED, and (b) shows the illuminance distribution of the MJT LED module according to the use of the optical member.
44 is a graph showing the light directing distribution, (a) showing the light directing distribution of the MJT LED, (b) showing the light directing distribution of the MJT LED module according to the use of the optical member.
45 is a cross-sectional view illustrating an MJT LED module according to an embodiment of the present invention.
46 (a), (b) and (c) are views taken along lines aa, bb, and cc of FIG. 45 .
47 is a view for explaining the optical member of the MJT LED module shown in FIG. 45 in more detail.
FIG. 48 is a view showing distribution of a light beam direction when the optical member shown in FIG. 47 is used.
49 is a view for explaining an optical member according to another embodiment of the present invention.
FIG. 50 is a view showing a light beam distribution angle obtained by using the optical member of FIG. 49 .
51A and 51B are diagrams showing an optical member and a directivity angle distribution curve according to Comparative Example 1, respectively.
52A and 52B are diagrams showing an optical member and a directivity angle distribution curve according to Comparative Example 2, respectively.

Hereinafter, preferred embodiments according to the present invention will be described in more detail with reference to the accompanying drawings in order to describe the present invention in more detail. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms.

In the present embodiments, "first", "second", or "third" is not intended to impose any limitation on the components, but should be understood as terms for distinguishing the components.

[Preferred embodiment of the present invention]

In an embodiment of the present invention, the term "MJT LED chip" refers to a multi-cell LED chip in which a plurality of light emitting cells are connected to each other by wirings in one LED chip. In addition, the MJT LED chip may be configured to include N light emitting cells (N is a positive integer of 2 or more), and N may be variously set as needed. In addition, the forward voltage of each light emitting cell may preferably be between 3V and 3.6V, but is not limited thereto. Accordingly, the forward voltage of the MJT LED chip (or MJT LED) is proportional to the number of light emitting cells included in the corresponding MJT LED chip. Since the number of light emitting cells included in the MJT LED chip can be variously configured as needed, the MJT LED chip according to the present invention can be configured according to the specifications of the driving power generator (eg, DC converter) used in the backlight unit. It may be configured to have a driving voltage of 6 to 36V, but is not limited thereto. In addition, the driving current of the MJT LED chip is very small compared to the conventional single-cell LED, and for example, may preferably be between 20 mA and 40 mA, but is not limited thereto.

In addition, the term "MJT LED" refers to a light emitting device or LED package on which the MJT LED chip according to the present invention is mounted.

Also, the term “MJT LED module” refers to a component in which one MJT LED and a corresponding one optical member are combined. The corresponding optical member may be disposed directly on the MJT LED, or may be disposed on a printed circuit board on which the MJT LED is mounted. Regardless of the arrangement method of the optical member, when one MJT LED and one optical member corresponding to the optical member are referred to as being combined, it is referred to as an MJT LED module.

In addition, the term "backlight module" refers to a lighting module in which a plurality of MJT LEDs are disposed on a printed circuit board, and a plurality of optical members corresponding to each of the plurality of MJT LEDs are disposed. Accordingly, the term “backlight module” may mean a lighting module in which a plurality of MJT LED modules are mounted on a printed circuit board according to a predetermined rule. Meanwhile, in one embodiment, the backlight module according to the present invention may be a direct backlight module, but the present invention is not limited thereto, and the backlight module according to the present invention may be used as a light source for surface illumination in another embodiment. Accordingly, it will be apparent to those skilled in the art that, despite the name, it falls within the scope of the present invention as long as it includes the technical gist of the backlight module according to the present invention.

Overview of backlight unit using MJT LED

Before describing the configuration of the backlight unit according to the present invention in detail, important technical features of the present invention will be described. The present invention is an invention devised by focusing on the device characteristics of the MJT LED in order to solve the problems of the prior art as described above. That is, the present invention provides a high voltage and low current driving characteristic of an MJT LED (eg, a driving voltage of 6 to 36V and 20 to 40 mA of driving current), and to solve the problems of the prior art as described above by configuring a backlight module using these MJT LEDs. As described above, in the case of the MJT LED, unlike the conventional single-cell LED, an arbitrary number of light emitting cells may be included, and the forward voltage varies according to the number of light emitting cells included. In addition, since the MJT LED includes a plurality of light emitting cells, a wider range can be irradiated compared to the conventional single-cell LED, and since it is composed of one MJT LED chip, it is easy to design and apply an optical member for it. do. Therefore, when using such an MJT LED, one of the plurality of divided areas of the liquid crystal panel can be covered by one MJT LED module (MJT LED + optical member). Accordingly, the number of LEDs required to construct the backlight module is reduced compared to the conventional single-cell LED. In conclusion, the present invention is configured to achieve the object of the present invention by configuring a backlight module using a plurality of MJT LED modules and configuring the backlight unit to independently control each MJT LED constituting the backlight module. do.

Hereinafter, the backlight unit 1000 according to a preferred embodiment of the present invention will be described in more detail with reference to FIGS. 2 to 5 .

First, FIG. 2 is a schematic block diagram of a backlight unit using an MJT LED according to a preferred embodiment of the present invention. As shown in FIG. 2 , the backlight unit 1000 according to the present invention may include a backlight control module 800 and a backlight module 700 . Furthermore, the backlight unit according to the present invention may further include a Field Effect Transistor (FET) (not shown) and a floodlighting plate (not shown).

More specifically, the backlight control module 800 according to the present invention comprises a driving power generator 810 and a backlight module 700 that generate/output DC driving power using an input power Vin input from the outside. It is configured to include a driving control unit 820 for controlling the operation of each of the plurality of MJT LEDs 500 (on/off control and dimming control). The driving power generator 810 is generally configured to generate a stable DC voltage such as 12V, 24V, 48V as driving power and provide it to the plurality of MJT LEDs 500 constituting the backlight module 700 . In this case, the input power Vin supplied to the driving power generator 810 may be a commercial AC power of 220V or 110V. The driving power generating unit 810 may have substantially the same configuration as the driving power generating unit 810 according to the related art illustrated in FIG. 1 .

The backlight module 700 according to the present invention is a plurality of MJT LEDs 500 on a printed circuit board (not shown in FIG. 2 ) and an optical member (not shown in FIG. 2 ) corresponding to each MJT LED 500 . ) can be arranged regularly (eg, in the form of a matrix).

5 is a schematic diagram for explaining a configuration of a backlight unit according to the present invention. Referring to FIG. 5 , the printed circuit board 510 may include a plurality of blocks 510b. When the plurality of MJT LEDs are mounted on the printed circuit board, the block 510b means a partial area of the printed circuit board including the area in which the plurality of MJT LEDs are mounted. Specifically, one block 510b may include at least one MJT LED. More specifically, one block 510b may include one MJT LED. However, the present invention is not limited thereto, and one block 510b may include a plurality of MJT LEDs.

The plurality of blocks 510b may be arranged in M in the horizontal direction and N in the vertical direction to form an MxN matrix array. As shown in FIG. 5 , for example, 45 blocks 510b may constitute a 9x5 matrix arrangement. The horizontal length L1 of each of the blocks 510b may be 60 mm or less. In addition, the vertical length L2 of each of the blocks 510b may be 55 mm or less.

In the embodiment shown in Fig. 2, M MJT LEDs 500 are arranged in the horizontal direction in the backlight module 700, and N MJT LEDs 500 are arranged in the vertical direction to form an MxN matrix arrangement. It is assumed to be composed In this case, each MJT LED may be positioned in a one-to-one correspondence with the blocks. In addition, the MJT LED disposed at the upper left side is referred to as a 1-1 MJT LED 500_11 , and the MJT LED disposed at the lower right side is referred to as an M-N MJT LED 500_MN.

On the other hand, the most noteworthy point here is that the MJT LEDs 500 in the backlight module 700 of the embodiment shown in FIG. 2 different from the prior art shown in FIG. 1 are not connected to each other in series or in parallel or in series/parallel. The point is that it is configured to be independently connected to the driving power generation unit 810 and the driving control unit 820 . That is, in the embodiment shown in FIG. 2 , the anode end of each MJT LED 500 is independently connected to the driving power generating unit 810 , and the cathode end of each MJT LED 500 is independently connected to the driving control unit ( 820) is connected. When each MJT LED and each block correspond one-to-one, the blocks may be configured to be independently connected to the driving power generator 810 and the driving controller 820 .

Due to this configuration, the driving control unit 820 according to the present invention can independently control the operation of each of the plurality of MJT LEDs 500 constituting the backlight module 700 . More specifically, the driving control unit 820 according to the present invention is configured to control the dimming level of a specific MJT LED among the plurality of MJT LEDs 500 according to the dimming signal Dim. When each MJT LED and each block correspond to each other in a one-to-one correspondence, the driving control unit 820 may independently control the operation of each of the plurality of blocks.

In one embodiment, the driving control unit 820 according to the present invention includes a PWM control means (not shown), and PWM ( Pulse Width Modulation) control to perform dimming control. In particular, unlike the prior art shown in FIG. 1 , in the backlight unit 1000 according to the present invention shown in FIG. 2 , each of the plurality of MJT LEDs 500 is independently supplied to the driving power generator 810 . Since it is configured to be connected and independently supplied with driving power, this PWM control method of dimming control becomes possible. Specifically, the driving controller 820 may control the duty ratio of the driving power to be 0 to 100%. For example, when dimming control for the 1-1 MJT LED 500_11 is required, the driving control unit 820 applies the generated driving power to a predetermined duty ratio (eg, 60%) according to the dimming signal Dim. ), and by providing the pulse-width-modulated driving power to the 1-1 MJT LED 500_11, dimming control for the 1-1 MJT LED 500_11 may be performed. At this time, driving power having a duty ratio of 100% that is not pulse width modulated will be supplied to other MJT LEDs other than the 1-1 MJT LED 500_11. Or, at this time, the driving power modulated by pulse width with a normal duty ratio (duty ratio that has a basic duty ratio when there is no separate dimming control, for example, 80%) for other MJT LEDs other than the 1-1 MJT LED 500_11 This will be supplied. Accordingly, local dimming of only the 1-1 MJT LED (500_11) is possible. Of course, it will be apparent to those skilled in the art that dimming control at the same dimming level and/or at different dimming levels for each MJT LED is possible using PWM control for a plurality of MJT LEDs at the same time. The above-described driving power may be a DC driving voltage. The PWM control means for controlling the driving power by PWM itself adopts a known technology, and further detailed description thereof will be omitted.

Meanwhile, in another embodiment, the driving control unit 820 according to the present invention includes a driving current detecting means (not shown) and a driving current controlling means (not shown), and the dimming control target among the MJT LEDs 500 is It can be configured to perform dimming control by controlling the drive current supplied to a particular MJT LED that is turned on. In particular, unlike the prior art shown in FIG. 1 , in the backlight unit 1000 according to the present invention shown in FIG. 2 , each of the plurality of MJT LEDs 500 is independently connected to the driving control unit 820 . Therefore, the dimming control of the driving current control method for each MJT LED in this way is possible. At this time, the driving current detecting means and the driving current controlling means included in the driving control unit 820 correspond to each of the MJT LEDs 500 in one-to-one correspondence. Accordingly, as described above, when the backlight module 700 is configured with MxN MJT LEDs 500 , MxN driving current detecting means and driving current controlling means are included in the driving controller 820 . For example, when dimming control for the M-N-th MJT LED 500_MN is required, the driving control unit 820 detects a driving current currently flowing through the M-N-th MJT LED 500_MN using a driving current detection means, and a dimming signal Dimming control for the M-N MJT LED 500_MN is performed by changing the value of the driving current flowing through the M-N MJT LED 500_MN according to (Dim) (eg, to 100% of the maximum driving current). For example, the driving controller 820 may control the driving current to be 0 to 100%. At this time, the normal driving current (the driving current set by default when there is no separate dimming control, for example, 80% of the maximum driving current) flows to the MJT LEDs other than the M-N MJT LED (500_MN), so the M-N MJT Local dimming of only the LED 500_MN is enabled. Of course, it will be apparent to those skilled in the art that dimming control is possible to the same dimming level and/or different dimming levels for each MJT LED through simultaneous driving current control for a plurality of MJT LEDs. On the other hand, since there is no need for the MJT LEDs 500 to be independently supplied with driving power in this embodiment, unlike the embodiment shown in FIG. 2 , the anode end of each MJT LED 500 is the driving power source. Each of the driving power lines connected to the generator 810 may be configured to be connected in parallel. Since the driving current detecting means and the driving current controlling means themselves adopt a known technology, further detailed description will be omitted.

The driving control unit 820 of the present invention may include a plurality of switch control units (not shown). The switch control unit may be located between the plurality of MJT LEDs, respectively. Specifically, the switch control unit may be located between one MJT LED and an adjacent MJT LED. More specifically, the switch control unit may be located between one MJT LED and the other MJT LEDs. That is, the switch control unit may be located between one MJT LED among the MxN MJT LEDs and the remaining MxN-1 MJT LEDs, which corresponds to all MJT LEDs included in the backlight module 700 as well as the one MJT LED. can do.

Each switch control unit may electrically connect two MJT LEDs connected by the switch control unit, and may electrically insulate the two MJT LEDs. Accordingly, a plurality of MJT LEDs may be connected in series and/or in parallel through the switch control unit. Accordingly, a desired structure of the backlight module 700 can be easily realized.

The backlight unit according to the present invention may further include an FET (not shown). When the backlight unit of the present invention includes an FET, it may also include an FET controller (not shown) for controlling the FET. The FET controller (drive IC) senses the set voltage and controls the on or off of the FET. For example, the set voltage may be a voltage applied to a resistor (not shown) connected to one terminal of the FET. When the FET is on, no current is applied to the MJT LED, and when the FET is off, a current may be applied to the MJT LED.

The FET may be connected to the MJT LEDs. Specifically, the number of MJT LEDs and the number of FETs are the same, and the MJT LEDs and the FETs may be connected one-to-one. For example, there are 640 MJT LEDs, and 640 FETs may be connected one-to-one with each MJT LED.

The MJT LED according to the present invention can be driven with a large voltage and a small current. In the case of an MJT LED capable of driving a small current, since it can be used with a FET having a relatively small capacity, the FET used in the present invention may have a smaller size than a FET used in the prior art. Accordingly, since a printed circuit board having a size smaller than that of a conventional printed circuit board can be used, the backlight module can be miniaturized and the manufacturing cost is reduced.

In addition, since the FET can be miniaturized, at least a portion of the FET may be included in the FET controller, unlike a conventional backlight unit in which the FET controller and the FET are spaced apart from each other. Furthermore, the FET controller may include all FETs used in the backlight unit. Accordingly, the number of FETs located in a state not included in the FET controller among FETs may be reduced or may not exist, so that the backlight module can be miniaturized and manufacturing costs are reduced. For example, when there are 640 MJT LEDs, the number of FETs not included in the FET controller may be less than 640. Accordingly, the size of the printed circuit board may be reduced, for example, may be reduced by 70% or more.

The backlight unit according to the present invention may further include a floodlight plate (not shown). The floodlight may be positioned above the backlight module 700 . Specifically, the floodlight may be located on the printed circuit board 510 of the backlight module 700 . The floodlight may serve to diffuse light emitted from the MJT LED of the backlight module 700 . The distance between the lower surface of the floodlight and the upper surface of the printed circuit board may be 18 mm or more.

Overview of MJT LEDs and MJT LED Modules

Figure 3 is a schematic cross-sectional view for explaining the MJT LED module according to an embodiment of the present invention, Figure 4 is a perspective view for explaining the MJT LED used in the MJT LED module. Hereinafter, a detailed configuration of the MJT LED 100 and the MJT LED module according to the present invention will be described with reference to FIGS. 3 and 4 .

Referring to FIG. 3 , the MJT LED module includes an MJT LED 100 and an optical member 530 . The MJT LED 500 is mounted on the printed circuit board 510 , and the corresponding optical member 530 is mounted on the printed circuit board 510 at a position matching the MJT LED 500 . For example, each block of the printed circuit board 510 may include one optical member. As described above, in another embodiment, the optical member 530 may be directly connected to the MJT LED 100 . Specifically, the optical member 530 may be formed by molding a resin on the MJT LED. Although a part of the printed circuit board 510 is shown, a plurality of MJT LEDs 500 and corresponding optical members 530 are arranged in various ways, such as in a matrix or honeycomb shape, on one printed circuit board 510 . Thus, the backlight module 500 as described above is configured.

The printed circuit board 510 includes conductive land patterns to which terminals of the MJT LED 500 are bonded. Also, the printed circuit board 510 may include a reflective film on its upper surface. The printed circuit board 510 may be a metal-core PCB (MCPCB) based on a metal having good thermal conductivity. Also, the printed circuit board 510 may be based on an insulating substrate material such as FR4. Although not shown, a heat sink may be disposed under the printed circuit board 510 to dissipate heat generated from the MJT LED 100 .

The MJT LED 100 is, as well shown in FIG. 4 , a housing 521 and a wavelength conversion layer 525 covering the MJT LED chip 523 and the MJT LED chip 523 mounted on the housing 521 . ) may be included. The MJT LED 500 also includes lead terminals (not shown) supported on the housing 521 .

The housing 521 constituting the package body may be made by injection molding a plastic resin such as PA or PPA. In this case, the housing 521 may be molded to support the lead terminals by an injection molding process, and may have a cavity 521a for mounting the MJT LED chip 523 . The cavity 521a defines a light emitting area of the MJT LED 500 .

The lead terminals are disposed to be spaced apart from each other in the housing 521 , and are extended to the outside of the housing 521 and bonded to the land pattern on the printed circuit board 510 .

The MJT LED chip 123 is mounted on the bottom of the cavity 521a and is electrically connected to lead terminals. The MJT LED chip 523 may be a gallium nitride-based MJT LED emitting ultraviolet or blue light. A detailed configuration of the MJT LED chip 523 and a manufacturing method thereof according to the present invention will be described later with reference to FIGS. 6 to 37 .

Meanwhile, the wavelength conversion layer 125 covers the MJT LED chip 123 . In an embodiment, the wavelength conversion layer 525 may be formed by mounting the MJT LED chip 523 and then filling the cavity 521a with a molding resin containing a phosphor. In this case, the wavelength conversion layer 525 may fill the cavity 521a of the housing 121 and may have a substantially flat or convex top surface. In addition, a molding resin having an optical member shape may be further formed on the wavelength conversion layer 125 .

In another embodiment, the MJT LED chip 523 on which the conformal phosphor coating layer is formed may be mounted on the housing 521 . That is, a conformal coating layer of a phosphor is applied on the MJT LED chip 523 , and the MJT LED chip 523 having the phosphor coating layer may be mounted on the housing 521 . The MJT LED chip 523 having the conformal coating layer may be molded with a transparent resin. Furthermore, this molding resin can have an optical member shape, and thus can function as a primary optical member.

The wavelength conversion layer 525 converts light emitted from the MJT LED chip 523 to a wavelength to realize mixed color light, for example, white light.

The wavelength conversion layer 525 may include a KSF-based and/or UCD-based phosphor. Accordingly, light emitted from the MJT LED chip 523 and transmitted through the wavelength conversion layer 525 may have an NTSC color gamut of 70% or more.

The MJT LED 500 is designed to have a light directing distribution of a mirror plane symmetric structure, and in particular, may be designed to have a light directing distribution of a rotationally symmetric structure. At this time, the axis of the MJT LED toward the center of the light directing distribution is defined as the optical axis (L). That is, the MJT LED 500 is designed to have a symmetric light directing distribution with respect to the optical axis L. In general, the cavity 521a of the housing 521 may be formed to have a mirror plane symmetric structure, and the optical axis L may be defined as a straight line passing through the center of the cavity 521a.

The optical member 530 includes a light-incident surface that receives light from the MJT LED 500 and a light-exit surface that emits light at a light beam angle wider than that of the MJT LED 500 , the MJT LED 500 . ) to evenly distribute the light emitted from the The optical member 530 according to the present invention will be described later with reference to FIGS. 38 to 52 .

MJT LED chip configuration and manufacturing method thereof

6 and 7 are plan views and cross-sectional views illustrating via-holes formed in a plurality of stacked structures according to an embodiment of the present invention.

In particular, FIG. 7 is a cross-sectional view taken along line A1-A2 in the plan view of FIG. 6 .

6 and 7 , the first semiconductor layer 110 , the active layer 120 , and the second semiconductor layer 130 are formed on the substrate 100 , and the surface of the first semiconductor layer 110 is exposed. Via holes 140 are formed.

The substrate 100 may have a material of sapphire, silicon carbide, or GaN, and any material capable of inducing the growth of the formed thin film may be used. The first semiconductor layer 110 may have an n-type conductivity. In addition, the active layer 120 may have a multi-quantum well structure, and the second semiconductor layer 130 is formed on the active layer 120 . When the first semiconductor layer 110 has an n-type conductivity, the second semiconductor layer 130 has a p-type conductivity. Also, a buffer layer (not shown) may be additionally formed between the substrate 100 and the first semiconductor layer 110 to facilitate single crystal growth of the first semiconductor layer 110 .

Subsequently, selective etching is performed on the structure formed up to the second semiconductor layer 130 , and a plurality of via holes 140 are formed. A portion of the lower first semiconductor layer 110 is exposed through the via hole 140 . The via hole 140 may be formed according to a conventional etching process. For example, after the photoresist is applied, a photoresist pattern from which the photoresist in the region to be formed is removed is formed through a conventional patterning process. Thereafter, an etching process is performed using the photoresist pattern as an etching mask. The etching process is performed until a portion of the first semiconductor layer 110 is exposed. Thereafter, the remaining photoresist pattern is removed.

The via hole 140 has an inclination angle a within a predetermined range with respect to the surface of the substrate or the surface of the first semiconductor layer 110 exposed by water etching. In particular, when the via hole 140 does not have an inclination angle within a predetermined range during the subsequent metal deposition process or the insulating material application process, cracks may occur in the deposited metal layer or part of the insulating material layer. In addition, even if cracks do not occur in the manufacturing process, it causes a reliability problem in the subsequent use of the MJT LED. Thermal and electrical stress generated during the light emitting operation according to the supply of power causes cracks in the metal layer or the insulating material layer formed on the via hole 140 formed outside the specific inclination angle a. The generated crack causes a malfunction of the MJT LED and lowers the luminance.

The via hole 140 preferably has an angle of 10 to 60 degrees with the surface of the substrate 100 or the surface of the first semiconductor layer 110 .

If the inclination angle a is less than 10 degrees, the area of the active layer 120 is reduced due to the excessively low inclination. A decrease in the area of the active layer causes a decrease in luminance. In addition, the actual area of the second semiconductor layer 130 has a very low value compared to that of the first semiconductor layer 110 . Typically, the second semiconductor layer 130 has a p-type conductivity type, and the first semiconductor layer 110 has an n-type conductivity type. During the light-emitting operation, the first semiconductor layer 110 supplies electrons to the active layer 120 , and the second semiconductor layer 130 supplies holes to the active layer 120 . The improvement of luminous efficiency tends to be influenced by the uniform and smooth supply of holes rather than the supply of electrons. Accordingly, an excessive reduction in the area of the second semiconductor layer 130 may cause a decrease in luminous efficiency. In addition, when the inclination angle a exceeds 60 degrees, cracks may occur in the metal layer or the insulating material layer formed later due to the high inclination.

Meanwhile, the shape and number of the via holes 140 may be variously changed.

8 and 9 are a plan view and a cross-sectional view illustrating that lower electrodes are formed on the second semiconductor layer of FIG. 6 , and in particular, FIG. 9 is a cross-sectional view of the plan view of FIG. 8 taken along line A1-A2.

8 and 9 , the lower electrodes 151 , 152 , 153 , and 154 are formed in a region excluding the via hole 140 , and through the formation of the lower electrodes 151 , 152 , 153 , 154 . A plurality of cell regions 161 , 162 , 163 , and 164 may be defined. In addition, the lower electrodes 151 , 152 , 153 , and 154 may be formed using a lift-off process used for forming the metal electrode. For example, a photoresist is formed in the isolation region and the region in which the via hole 140 is formed except for the virtual cell regions 161 , 162 , 163 , and 164 , and a metal layer is formed through conventional thermal deposition or the like. Thereafter, the lower electrodes 151 , 152 , 153 , and 154 are formed on the second semiconductor layer 130 by removing the photoresist. The lower electrodes 151 , 152 , 153 , and 154 may be any metal material that makes an ohmic contact with the second semiconductor layer 130 . The lower electrodes 151 , 152 , 153 , and 154 may include Ni, Cr, or Ti, and may be formed of a Ti/Al/Ni/Au composite metal layer.

The lower electrodes 151 , 152 , 153 , and 154 may have a thickness in a range of 2000 Å to 10000 Å. When the thickness of the lower electrodes 151 , 152 , 153 , and 154 is less than 2000 Å, light reflection from the lower electrodes 151 , 152 , 153 , and 154 toward the substrate 100 is not smooth, and the lower electrode 151 in the form of a thin film , 152, 153, and 154) are leaked. In addition, when the thickness of the lower electrodes 151 , 152 , 153 , and 154 exceeds 10000 Å, excessive time is consumed in the lower electrode forming process such as thermal deposition.

In addition, the lower electrodes 151 , 152 , 153 , and 154 may have an inclination angle b of 10 degrees to 45 degrees with respect to the surface of the second semiconductor layer 130 . When the inclination angle b of the lower electrodes 151 , 152 , 153 , and 154 is less than 10 degrees, the efficiency of light reflection is reduced due to the very gentle inclination. In addition, due to the low inclination angle, there is a problem in that the uniformity of the thickness on the surface of the lower electrode cannot be secured. If the inclination angle b of the lower electrodes 151 , 152 , 153 , and 154 exceeds 45 degrees, cracks may occur in a film formed later due to the high inclination angle.

The adjustment of the inclination angle b of the lower electrodes 151 , 152 , 153 , and 154 with respect to the surface of the second semiconductor layer 130 is determined by the angle of the substrate with respect to the arrangement of the substrate and the moving direction of metal atoms in a process such as thermal evaporation. This can be achieved through change.

In FIGS. 8 and 9 , the region in which the four lower electrodes 151 , 152 , 153 , and 154 are formed defines four cell regions 161 , 162 , 163 and 164 . The second semiconductor layer 130 is exposed in the space between the cell regions 161 , 162 , 163 and 164 . The number of the cell regions 161 , 162 , 163 , and 164 may be formed to correspond to the number of light emitting cells included in the MJT LED to be formed. Accordingly, the number of cell regions can be variously changed.

Also, in FIG. 9 , the lower electrodes 151 , 152 , 153 , and 154 are depicted as being separated within the same cell regions 161 , 162 , 163 and 164 , but this is because the cut-off line A1-A2 crosses the via hole 140 . This is a phenomenon that occurs as a result of As can be seen from FIG. 8 , the lower electrodes 151 , 152 , 153 , and 154 formed on the same cell regions 161 , 162 , 163 and 164 are physically connected. Accordingly, the lower electrodes 151 , 152 , 153 , and 154 formed on the same cell region are electrically short-circuited despite the formation of the via hole 140 .

10 is a plan view illustrating a state in which cell regions are separated with respect to the structure of FIG. 8 , FIG. 11 is a cross-sectional view of the plan view of FIG. 10 taken along line A1-A2, and FIG. 12 is a perspective view of the plan view of FIG. .

Referring to FIGS. 10, 11 and 12 , a mesa-etched region is formed by mesa-etching the space between the four cell regions 161 , 162 , 163 and 164 . Through the mesa etching, the substrate 100 is exposed in the mesa etching area. Accordingly, the four cell regions 161 , 162 , 163 , and 164 are electrically completely isolated from each other. If the buffer layer is interposed between the substrate 100 and the first semiconductor layer 110 in FIGS. 1 to 9 , the buffer layer may remain in the separation process of the cell regions 161 , 162 , 163 and 164 . have. However, in order to completely separate the cell regions 161 , 162 , 163 and 164 , the buffer layer between the cell regions 161 , 162 , 163 and 164 may be removed through mesa etching.

Through the mesa etching, side surfaces of the first semiconductor layer 110 , the active layer 120 , the second semiconductor layer 130 , and the lower electrodes 151 , 152 , 153 and 154 are exposed on the side surfaces of the mesa region. The exposed side surfaces may have an inclination angle c of 10 degrees to 60 degrees with respect to the surface of the substrate 100 . Adjustment of the inclination angle c of the exposed side surfaces may be achieved through adjustment of the angle of the substrate with respect to the traveling direction of the etching etchant.

In addition, when the inclination angle c of the layers exposed through the mesa etching is less than 10 degrees, a reduction in the emission area may be induced due to the low inclination inclination, and light efficiency may be deteriorated. In addition, when the inclination angle c exceeds 60 degrees, the thickness of a film formed thereafter may become non-uniform or cracks may occur due to the high inclination angle. This is one factor that lowers the reliability of the device.

In addition, the range of the inclination angle c of the films exposed through the mesa etching affects the reflection of light by the metal layer formed in the subsequent process. For example, if a metal layer is formed on a sidewall of a film exposed through mesa etching and the inclination angle c is less than 10 degrees, light formed in the active layer is not reflected in a predetermined range with respect to the substrate and is scattered. In addition, even if the inclination angle c exceeds 60 degrees, the reflection of light does not proceed to a predetermined area, and a phenomenon of scattering occurs.

A first semiconductor layer 111, 112, 113, 114, an active layer ( 121 , 122 , 123 , 124 ), second semiconductor layers 131 , 132 , 133 , and 134 , and lower electrodes 151 , 152 , 153 , and 154 are formed. Accordingly, the first lower electrode 151 is exposed on the first cell region 161 , and the first semiconductor layer 111 is exposed through the via hole 140 . In addition, the second lower electrode 152 is exposed on the second cell region 162 , and the first semiconductor layer 112 is exposed through the via hole 140 . Similarly, the third lower electrode 153 and the first semiconductor layer 113 are exposed on the third cell region 163 , and the fourth lower electrode 154 and the first semiconductor layer 114 are exposed on the fourth cell region 164 . ) is exposed.

In addition, in the present invention, the light emitting cell has a structure in which a first semiconductor layer (111, 112, 113, 114), an active layer (121, 122, 123, 124), and a second semiconductor layer (131, 132, 133, 134) are stacked. refers to Accordingly, one light emitting cell is formed in one cell region. In addition, when it is modeled that the first semiconductor layers 111, 112, 113, and 114 have an n-type conductivity and the second semiconductor layers 131, 132, 133, and 134 have a p-type conductivity, The lower electrodes 151 , 152 , 153 , and 154 formed on the second semiconductor layers 131 , 132 , 133 and 134 may be referred to as anode electrodes of the light emitting cell.

13 is a plan view of a first interlayer insulating film formed on the entire surface of the structure of FIGS. 10 to 12 and a portion of the first semiconductor layer and the lower electrode are exposed in each cell region.

14 to 17 are cross-sectional views taken along a specific line in the plan view of FIG. 13 . In particular, FIG. 14 is a cross-sectional view taken along line B1-B2 of the plan view of FIG. 13, FIG. 15 is a cross-sectional view taken along line C1-C2 of FIG. 13, and FIG. 16 is a plan view of FIG. 13 taken along line D1-D2 It is a cross-sectional view taken along the line, and FIG. 17 is a cross-sectional view taken along E1-E2 of the plan view of FIG. 13 .

First, a first interlayer insulating layer 170 is formed with respect to the structures of FIGS. 10 to 12 . In addition, a portion of the first semiconductor layers 111 , 112 , 113 , and 114 under the via hole and the lower electrodes 151 , 152 , 153 and 154 are exposed through patterning.

For example, in the first cell region 161 , two preformed via holes are opened to expose the first semiconductor layer 111 , and a portion of the first lower electrode 151 formed on the preformed second semiconductor layer 131 . is exposed In addition, in the second cell region 162 , the first semiconductor layer 112 exposed through the pre-formed via hole is exposed, and the second lower electrode 152 is formed by etching a portion of the first interlayer insulating layer 170 . Some are exposed Also, in the third cell region 163 , the first semiconductor layer 113 is exposed through the via hole, and a portion of the third lower electrode 153 is exposed through etching of a portion of the first interlayer insulating layer 170 . . In the fourth cell region 164 , the first semiconductor layer 114 is exposed through the via hole, and a portion of the fourth lower electrode 154 is exposed through etching of a portion of the first interlayer insulating layer 170 .

As a result, in FIGS. 13 to 17 , the first interlayer insulating layer 170 is formed on the entire surface of the substrate, and through selective etching, the first semiconductor layer 111 in the via hole for each cell region 161 , 162 , 163 , and 164 . , 112 , 113 , and 114 , and portions of the lower electrodes 151 , 152 , 153 , and 154 on the second semiconductor layers 131 , 132 , 133 and 134 are exposed. The remaining region is shielded by the first interlayer insulating layer 170 .

The first interlayer insulating layer 170 may be formed of an insulating material having a predetermined light transmittance. For example, the first interlayer insulating layer 170 may include SiO2.

In addition, the first interlayer insulating layer 170 may have a thickness of 2000 Å to 20000 Å.

When the thickness of the first interlayer insulating layer 170 is less than 2000 Å, it is difficult to secure insulating properties due to the low thickness. In particular, when the first interlayer insulating layer 170 is formed on the sidewall of the via hole 140 or the mesa region, since it has a constant slope, the first interlayer insulating layer 170 having a low thickness may cause dielectric breakdown.

In addition, when the thickness of the first interlayer insulating layer 170 exceeds 20,000 Å, a selective etching process for the first interlayer insulating layer 170 becomes difficult. For example, a portion of the first semiconductor layer and the lower electrodes of the via hole 140 must be exposed, and for this purpose, the entire surface of the first interlayer insulating layer 170 and a selective etching process are performed. For the selective etching process, photoresist coating and patterning are performed. In addition, etching is performed on the area opened by the remaining photoresist pattern. If the thickness of the first interlayer insulating layer 170 exceeds 20,000 Å, the photoresist pattern serving as an etching mask may also be removed in the process of selectively etching the first interlayer insulating layer 170 . Accordingly, there is a process error in which etching may be performed at an unwanted site.

In addition, the first interlayer insulating layer 170 may have an inclination angle d of 10 degrees to 60 degrees with respect to the surface of the lower electrode exposed through selective etching.

When the inclination angle d of the first interlayer insulating layer 170 is less than 10 degrees, the area of the exposed lower electrode surface decreases or the substantial thickness of the first interlayer insulating layer 170 decreases, making it difficult to secure insulating properties. do. That is, in the case of the first interlayer insulating layer 170 , it functions to electrically insulate the lower electrode from other conductive layers formed thereon. Accordingly, the first interlayer insulating layer 170 must have a sufficient thickness, and the lower electrode must have a predetermined area and be exposed for other electrical connection. When the first interlayer insulating layer 170 has a very low inclination, the area of the exposed lower electrode must be reduced to implement the first interlayer insulating layer 170 having a constant thickness. In addition, when the exposed area of the lower electrode is to be secured to be greater than or equal to a predetermined value, insulation breakdown may occur due to the first interlayer insulating layer 170 having a low thickness due to a low inclination.

In addition, when the inclination angle d of the first interlayer insulating film 170 exceeds 60 degrees, when another film quality is formed on the first interlayer insulating film 170 , the quality of the other film quality is deteriorated due to the sharp inclination angle. is generated

The adjustment of the inclination angle of the first interlayer insulating layer 170 may be achieved by adjusting the etching angle in the partial etching process of the first interlayer insulating layer 170 formed on the lower electrode.

18 is a plan view illustrating upper electrodes formed on the structure illustrated in FIGS. 13 to 17 . 19 to 22 are cross-sectional views taken along a specific line in the plan view of FIG. 18 . In particular, FIG. 19 is a cross-sectional view of the plan view of FIG. 18 taken along line B1-B2, FIG. 20 is a cross-sectional view of the plan view of FIG. 18 taken along line C1-C2, and FIG. 21 is a plan view of FIG. 18 taken along line D1-D2 22 is a cross-sectional view taken along E1-E2 of the plan view of FIG. 18 .

Referring to FIG. 18 , upper electrodes 181 , 182 , 183 , and 184 are formed. The upper electrodes 181 , 182 , 183 , and 184 are divided into four regions. For example, the first upper electrode 181 is formed over a portion of the first cell region 161 and the second cell region 162 . In addition, the second upper electrode 182 is formed over a portion of the second cell region 162 and a portion of the third cell region 163 . The third upper electrode 183 is formed over a portion of the third cell region 163 and a portion of the fourth cell region 164 , and the fourth upper electrode 184 is formed over a portion of the fourth cell region 164 . is formed Accordingly, each of the upper electrodes 181 , 182 , 183 , and 184 is formed while shielding a space between adjacent cell regions. The upper electrodes 181 , 182 , 183 , and 184 may cover 30% or more, further 50% or more, or 90% or more of the spacing between cell regions. However, since the upper electrodes 181 , 182 , 183 , and 184 are spaced apart from each other, the upper electrodes 181 , 182 , 183 , and 184 cover less than 100% of an area between the light emitting diodes.

All of the upper electrodes 181 , 182 , 183 , and 184 may occupy 30% or more, further, 50% or more, or 90% or more of the total area of the MJT LED. Since the upper electrodes 181 , 182 , 183 , and 184 are spaced apart from each other, they occupy less than 100% of the total area of the MJT LED. In addition, the upper electrodes 181 , 182 , 183 , and 184 have a plate or sheet shape in which a width to width ratio is in a range of 1:3 to 3:1. Furthermore, at least one of the upper electrodes 181 , 182 , 183 , and 184 has a width or a width greater than that of a corresponding light emitting cell (cell region).

Referring to FIG. 19 , the first upper electrode 181 is formed on the first interlayer insulating layer 170 of the first cell region 161 and is formed on the first semiconductor layer 111 opened through a via hole. . In addition, the first upper electrode 181 exposes a portion of the first lower electrode 151 of the first cell region 161 , and is formed on the exposed second lower electrode 152 of the second cell region 162 . is formed

In addition, the second upper electrode 182 is formed on the first semiconductor layer 112 exposed through the via hole of the second cell region 162 in a state physically separated from the first upper electrode 181 , and the remaining In the region, it is formed on the first interlayer insulating layer 170 .

19 , the first upper electrode 181 electrically connects the first semiconductor layer 111 of the first cell region 161 and the second semiconductor layer 132 of the second cell region 162 . The second lower electrode 152 on the second cell region 162 is electrically short-circuited in one cell region despite the presence of the via hole. Accordingly, the first semiconductor layer 111 of the first cell region 161 is electrically connected to the second semiconductor layer 132 of the second cell region 162 through the second lower electrode 152 .

Also, in FIG. 20 , the second upper electrode 182 is formed on the first semiconductor layer 112 exposed through the via hole of the second cell region 162 , and the third lower electrode of the third cell region 163 . It is formed by extending to (153).

In addition, the third upper electrode 183 physically separated from the second upper electrode 182 is formed on the first semiconductor layer 113 exposed through the via hole of the third cell region 163 .

In FIG. 20 , the second upper electrode 182 is electrically connected to the first semiconductor layer 112 exposed through the via hole of the second cell region 162 , and the third lower electrode ( 163 ) of the third cell region 163 . 153) is electrically connected. Accordingly, the first semiconductor layer 112 of the second cell region 162 may maintain an equipotential with the second semiconductor layer 133 of the third cell region 163 .

Referring to FIG. 21 , the third upper electrode 183 is formed on the first semiconductor layer 113 exposed through the via hole of the third cell region 163 , and the fourth lower electrode 183 of the fourth cell region 164 . It is formed by extending to the electrode 154 . Accordingly, the first semiconductor layer 113 of the third cell region 163 and the second semiconductor layer 134 of the fourth cell region 164 are electrically connected.

In addition, the fourth upper electrode 184 physically separated from the third upper electrode 183 is electrically connected to the first semiconductor layer 114 exposed through the via hole of the fourth cell region 164 .

Referring to FIG. 22 , the fourth upper electrode 184 is formed on the first semiconductor layer 114 exposed through the via hole of the fourth cell region 164 . In addition, the first upper electrode 181 physically separated from the fourth upper electrode 184 is formed on the first semiconductor layer 111 exposed through the via hole on the first cell region 161, and the first cell A portion of the first lower electrode 151 in the region 161 is exposed.

18 to 22 , the first semiconductor layer 111 of the first cell region 161 and the second semiconductor layer 132 of the second cell region 162 have a first upper electrode 181 . ) to form an equipotential. In addition, the first semiconductor layer 112 of the second cell region 162 and the second semiconductor layer 133 of the third cell region 163 form an equipotential through the second upper electrode 182 . The first semiconductor layer 113 of the third cell region 163 forms an equipotential with the second semiconductor layer 134 of the fourth cell region 164 through the third upper electrode 183 . In the first cell region 161 , the first lower electrode 151 electrically connected to the second semiconductor layer 131 is exposed. Of course, the formation of the equipotential is the resistance of the upper electrodes 181 , 182 , 183 , 184 and the contact resistances of the upper electrodes 181 , 182 , 183 , 184 and the lower electrodes 151 , 152 , 153 , 154 . An ideal electrical connection is assumed in the neglected state. Therefore, in the actual operation of the device, a voltage drop due to the resistance component of the upper electrodes 181 , 182 , 183 , 184 and the lower electrodes 151 , 152 , 153 and 154 , which are a kind of metal wiring, may partially occur.

Also, any material capable of forming an ohmic contact with the first semiconductor layers 111 , 112 , 113 and 114 may be used for the upper electrodes 181 , 182 , 183 , and 184 . In addition, any material capable of forming an ohmic contact with the metal lower electrodes 151 , 152 , 153 , and 154 may be used as the upper electrodes 181 , 182 , 183 , and 184 . Accordingly, the upper electrodes 181 , 182 , 183 , and 184 may include a metal layer including Ni, Cr, Ti, Rh, or Al or a conductive oxide layer such as ITO as an ohmic contact layer.

In addition, the upper electrodes 181 , 182 , and 183 to reflect light generated from the active layers 121 , 122 , 123 , and 124 of each of the cell regions 161 , 162 , 163 and 164 toward the substrate 100 . , 184) may include a reflective layer such as Al, Ag, Rh or Pt. In particular, light generated from each of the active layers 121 , 122 , 123 and 124 is reflected from the lower electrodes 151 , 152 , 153 , and 154 toward the substrate 100 . In addition, light transmitted through the space between the cell regions 161 , 162 , 163 and 164 is transmitted through the upper electrodes 181 , 182 , which shield the space between the cell regions 161 , 162 , 163 and 164 . 183, 184).

The thickness of the upper electrodes 181 , 182 , 183 , and 184 may be in a range of 2000 Å to 10000 Å. When the thickness of the upper electrodes 181 , 182 , 183 , and 184 is less than 2000 Å, light reflection from the upper electrodes 181 , 182 , 183 , and 184 toward the substrate 100 is not smooth, and the upper electrode 181 in the form of a thin film , 182, 183, and 184) are leaked. In addition, when the thickness of the upper electrodes 181 , 182 , 183 , and 184 exceeds 10000 Å, excessive time is consumed in the upper electrode forming process such as thermal deposition.

In addition, the upper electrodes 181 , 182 , 183 , and 184 may have an inclination angle e of 10 degrees to 45 degrees with respect to the surface of the first interlayer insulating layer 170 . When the inclination angle e of the upper electrodes 181 , 182 , 183 , and 184 is less than 10 degrees, the efficiency of light reflection is reduced due to the very gentle inclination. In addition, due to the low inclination angle, there is a problem in that the uniformity of the thickness on the surface of the upper electrode cannot be ensured. If the inclination angle e of the upper electrodes 181 , 182 , 183 , and 184 is greater than 45 degrees, cracks in a film formed later may occur due to the high inclination angle.

Adjustment of the inclination angle e of the upper electrodes 181 , 182 , 183 , and 184 with respect to the surface of the first interlayer insulating film 170 is determined by the angle of the substrate with respect to the arrangement of the substrate and the traveling direction of metal atoms in a process such as thermal evaporation. This can be achieved through change.

In addition, when the first semiconductor layers 111 , 112 , 113 , and 114 have an n-type conductivity and the second semiconductor layers 131 , 132 , 133 , and 134 have a p-type conductivity, each upper electrode can be modeled as the cathode electrode of the light emitting cell, and the cathode electrode can be simultaneously modeled as a wiring connected to the lower electrode, which is the anode electrode of the light emitting cell formed in the adjacent cell region. That is, in the light emitting cell formed on the cell region, the upper electrode may be modeled as a wiring electrically connected to the anode electrode of the light emitting cell in the adjacent cell region while forming the cathode.

23 is a perspective view illustrating a plan view of FIG. 18 .

Referring to FIG. 23 , the first upper electrode 181 to the third upper electrode 183 are formed over at least two cell regions. Accordingly, the space between adjacent cell regions is shielded. The upper electrodes reflect light that may leak between adjacent cell regions through the substrate, and are electrically connected to the first semiconductor layer of each cell region. In addition, it is electrically connected to the second semiconductor layer of the adjacent cell region.

24 is an equivalent circuit diagram modeling the structures of FIGS. 18 to 23 according to an embodiment of the present invention.

Referring to FIG. 24 , four light emitting cells D1, D2, D3, and D4 and a wiring relationship therebetween are disclosed.

The first light emitting cell D1 is formed in the first cell region 161 , the second light emitting cell D2 is formed in the second cell region 162 , the third light emitting cell D3 is formed in the third cell region 163 , and the fourth light emission is performed. Cell D4 is formed in the fourth cell region 164 . In addition, the first semiconductor layers 111 , 112 , 113 , and 114 of each of the cell regions 161 , 162 , 163 and 164 are modeled as n-type semiconductors, and the second semiconductor layers 131 , 132 , 133 and 134 are modeled as n-type semiconductors. is modeled as a p-type semiconductor.

The first upper electrode 181 is electrically connected to the first semiconductor layer 111 of the first cell region 161 , extends to the second cell region 162 , and is a second electrode of the second cell region 162 . It is electrically connected to the semiconductor layer 132 . Accordingly, the first upper electrode 181 is modeled as a wiring connecting the cathode terminal of the first light emitting cell D1 and the anode terminal of the second light emitting cell D2.

In addition, the second upper electrode 182 is modeled as a wiring connecting the cathode terminal of the second light emitting cell D2 and the anode terminal of the third light emitting cell D3, and the third upper electrode 183 is the third light emitting cell D3. It is modeled as a wiring connecting the cathode terminal and the anode terminal of the fourth light emitting cell D4. In addition, the fourth upper electrode 184 is modeled as a wiring forming the cathode terminal of the fourth light emitting cell D4.

Accordingly, the anode terminal of the first light emitting cell D1 and the cathode terminal of the fourth light emitting cell D4 are electrically open to an external power source, and the remaining light emitting cells D2 and D3 form a series-connected structure. If the light emitting operation is to be performed, the anode terminal of the first light emitting cell D1 should be connected to a positive power voltage V+, and the cathode terminal of the fourth light emitting cell D4 should be connected to a negative power voltage V−. Accordingly, a light emitting cell connected to a positive power supply voltage V+ may be referred to as an input light emitting cell, and a light emitting cell connected to a negative power supply voltage V− may be referred to as an output light emitting cell.

In the above-described structure, in the cell region in which the cathode terminal connected to the negative power voltage V− is formed in the connection relationship of the plurality of light emitting cells, an upper electrode for shielding only a part of the corresponding cell region is formed. An upper electrode for shielding between the electrically connected cell regions is formed in the cell region forming the other connection relationship.

25 is a plan view showing a second interlayer insulating film applied to the entire surface of the structure in the plan view of FIG. 18 , part of the first lower electrode of the first cell region being exposed, and part of the fourth upper electrode of the fourth cell region being exposed; FIG. to be.

Referring to FIG. 25 , the upper electrodes are shielded through the second interlayer insulating layer 190 , and a portion of the first lower electrode 151 and a portion of the fourth upper electrode 184 are exposed. This means that only the anode terminal of the first light emitting cell D1 is exposed and only the cathode terminal of the fourth light emitting cell is exposed in FIG. 24 .

26 is a cross-sectional view taken along B1-B2 of the plan view of FIG. 25, FIG. 27 is a cross-sectional view of the plan view of FIG. 25 taken along C1-C2, and FIG. It is a cross-sectional view taken along the line, and FIG. 29 is a cross-sectional view taken along E1-E2 of the plan view of FIG. 25 .

Referring to FIG. 26 , the first lower electrode 151 electrically connected to the second semiconductor layer 131 in the first cell region 161 is opened. The remaining region is covered with the second interlayer insulating layer 190 over the second cell region 162 .

Referring to FIG. 27 , the second cell region 162 and the third cell region 163 are completely covered with the second interlayer insulating layer 190 .

Also, referring to FIGS. 28 and 29 , the fourth upper electrode 184 of the fourth cell region 164 is exposed, and the first lower electrode 151 of the first cell region 161 is exposed.

The fourth upper electrode 184 and the first lower electrode 151 are exposed through selective etching of the second interlayer insulating layer 190 .

The second interlayer insulating layer 190 is selected from an insulating material capable of protecting the underlying layer from the external environment. In particular, SiN, which has insulating properties and can block changes in temperature or humidity, may be used.

The thickness of the second interlayer insulating layer 190 may have a predetermined range. For example, when the second interlayer insulating layer 190 includes SiN, the second interlayer insulating layer 190 may have a thickness of 2000 Å to 20000 Å.

If the thickness of the second interlayer insulating layer 190 is less than 2000 Å, it is difficult to secure insulating properties due to the low thickness. In addition, due to the low thickness, there is a problem in protecting the lower membrane from the penetration of external moisture or chemicals.

When the thickness of the second interlayer insulating layer 190 exceeds 20000 Å, it is difficult to selectively etch the second interlayer insulating layer 190 through the formation of a photoresist pattern. That is, in the etching process, the photoresist pattern acts as an etching mask, and the photoresist pattern is etched along with the selective etching of the second interlayer insulating layer 190 due to the excessive thickness of the second interlayer insulating layer 190 . When the thickness of the second interlayer insulating layer 190 is excessive, the photoresist pattern is removed before the selective etching of the second interlayer insulating layer 190 is completed, so that etching is performed at an unwanted position may occur.

In addition, the second interlayer insulating layer 190 may have an inclination angle f of 10 degrees to 60 degrees with respect to the surface of the fourth upper electrode 184 or the first lower electrode 151 exposed thereunder.

If the inclination angle f of the second interlayer insulating layer 190 is less than 10 degrees, a substantial area of the exposed fourth upper electrode 184 or the first lower electrode 151 is reduced. In addition, if the area of the exposed portion is increased to secure a substantial area, insulation properties cannot be secured due to a low inclination angle.

In addition, when the inclination angle f of the second interlayer insulating film 190 exceeds 60 degrees, the quality of another film formed on the second interlayer insulating film 190 may be deteriorated or the film may be cracked due to the sharp profile or inclination. . In addition, during the light emitting operation according to the continuous supply of power, the characteristics are deteriorated.

FIG. 30 is a plan view of the structure of FIG. 25 in which the first pad and the second pad are formed.

Referring to FIG. 30 , the first pad 210 may be formed over the first cell region 161 and the second cell region 162 . Through this, the first pad 210 achieves electrical contact with the first lower electrode 151 of the first cell region 161 exposed in FIG. 25 .

In addition, the second pad 220 may be formed to be spaced apart from the first pad 210 by a predetermined distance, and may be formed over the third cell region 163 and the fourth cell region 164 . The second pad 220 is electrically connected to the fourth upper electrode 184 of the fourth cell region 164 exposed in FIG. 25 .

31 is a cross-sectional view of the top view of FIG. 30 taken along line B1-B2, FIG. 32 is a cross-sectional view of the plan view of FIG. 30 taken along line C1-C2, and FIG. 33 is a plan view of FIG. 30 taken along line D1-D2 It is a cross-sectional view, and FIG. 34 is a cross-sectional view taken along E1-E2 of the plan view of FIG.

Referring to FIG. 31 , the first pad 210 is formed over the first cell region 161 and the second cell region 162 . The first pad 210 is formed on the first lower electrode 151 exposed in the first cell region 161 . In the remaining region, it is formed on the second interlayer insulating layer 190 . Accordingly, the first pad 210 is electrically connected to the second semiconductor layer 131 of the first cell region 161 through the first lower electrode 151 .

Referring to FIG. 32 , a first pad 210 is formed on the second cell region 162 , and a second pad 220 is formed on the third cell region 163 to be spaced apart from the first pad 210 . . In the second cell region 162 and the third cell region 163 , the first pad 210 or the second pad 220 is cut off from electrical contact with the lower electrode or the upper electrode.

Referring to FIG. 33 , the second pad 220 is formed over the third cell region 163 and the fourth cell region 164 . In particular, the fourth upper electrode 184 and the second pad 220 opened in the fourth cell region 164 are electrically connected. Accordingly, the second pad 220 is electrically connected to the first semiconductor layer 114 of the fourth cell region 164 .

Referring to FIG. 34 , the second pad 220 is formed on the fourth cell region 164 , and the first pad 210 is formed on the first cell region 161 to be spaced apart from the second pad 220 . . The first pad 210 is formed on the first lower electrode 151 of the first cell region 161 and is electrically connected to the second semiconductor layer 131 .

35 is a perspective view of the plan view of FIG. 30 cut along the line C2-C3.

35 , the first semiconductor layer 113 of the third cell region 163 is electrically connected to the third upper electrode 183 . The third upper electrode 183 shields the space between the third cell region 163 and the fourth cell region 164 , and is electrically connected to the fourth lower electrode 154 of the fourth cell region 164 . do. Also, the first pad 210 and the second pad 220 are spaced apart from each other and formed on the second interlayer insulating layer 190 . Of course, as described above, the first pad 210 is electrically connected to the second semiconductor layer 131 of the first cell region 161 , and the second pad 220 is the second pad of the fourth cell region 164 . 1 is electrically connected to the semiconductor layer 111 .

The first pad 210 and the second pad 220 may have a first layer including Ti, Cr, or Ni and a second layer including Al, Cu, Ag or Au thereon. Also, the first pad 210 and the second pad 220 may be formed using a lift-off process. In addition, after forming a double-layer or single-layer metal film, a pattern is formed through a conventional photolithography process, and the pattern may be formed through dry etching or wet etching using this as an etching mask. However, the etchant during dry etching and wet etching may be set differently depending on the material of the metal to be etched.

Through this, the first pad 210 and the second pad 220 may be simultaneously formed through one process.

In addition, a pad barrier layer (not shown) made of a conductive material may be formed on the first pad 210 or the second pad 220 . The pad barrier layer is provided to prevent metal diffusion that may occur during bonding or soldering to the pads 210 and 220 . For example, during bonding or soldering, a phenomenon in which tin atoms included in the bonding metal or soldering material diffuse into the pads 210 and 220 to increase the resistivity of the pads is prevented. To this end, the pad barrier layer may be composed of Cr, Ni, TiW, TiW, Mo, Pt, or a composite layer thereof.

Referring to the modeling of FIG. 24 , the first semiconductor layers 111 , 112 , 113 , and 114 of each cell region are modeled as n-type semiconductors, and the second semiconductor layers 131 , 132 , 133 and 134 are p It is modeled as a type semiconductor. The first lower electrode 151 formed on the second semiconductor layer 131 of the first cell region 161 is modeled as the anode electrode of the first light emitting cell D1. Accordingly, the first pad 210 may be modeled as a wiring connected to the anode electrode of the first light emitting cell D1. In addition, the fourth upper electrode 184 electrically connected to the first semiconductor layer 114 of the fourth cell region 164 is modeled as a cathode electrode of the fourth light emitting cell D4. Accordingly, the second pad 220 may be understood as a wiring connected to the cathode electrode of the fourth light emitting cell D4.

Through this, a structure in which four light emitting cells D1 to D4 are connected in series is formed, and electrical connection to the outside is achieved through two pads 210 and 220 formed on one substrate 100 .

In particular, referring to FIG. 24 , the first lower electrode 152 of the first light emitting cell D1 connected to the positive power supply voltage V+ is electrically connected to the first pad 210, and the first lower electrode 152 connected to the negative power supply voltage V− The fourth upper electrode 184 of the fourth light emitting cell D4 is electrically connected to the second pad 220 .

In the present invention, four light emitting cells are formed in a form separated from each other, and an anode terminal of one light emitting cell is electrically connected to a cathode terminal of another light emitting cell through a lower electrode and an upper electrode. However, according to this embodiment, four light emitting cells are only one embodiment, and according to the present invention, various number of light emitting cells can be formed.

36 is a circuit diagram modeled to connect ten light emitting cells in series according to an embodiment of the present invention.

Referring to FIG. 36 , ten cell regions 301 to 310 are defined using the process illustrated in FIG. 10 . The first semiconductor layer, the active layer, the second semiconductor layer, and the lower electrode in each cell region 301 to 310 are separated from other cell regions. Each of the lower electrodes is formed on the second semiconductor layer to form the anode electrodes of the light emitting cells D1 to D10.

Next, a first interlayer insulating film and upper electrodes are formed using the processes shown in FIGS. 11 to 22 . However, the formed upper electrodes shield the spaced space between adjacent cell regions, and act as wiring for achieving electrical connection between the anode electrodes of adjacent light emitting cells.

In addition, based on the process introduced in FIGS. 25 to 34, a second interlayer insulating film is formed, and the lower electrode of the first light emitting cell D1, which is an input light emitting cell connected to the positive power voltage V+ on the current path, is exposed, and the negative The upper electrode of the tenth light emitting cell D10, which is an output light emitting cell connected to the power supply voltage V- of , is opened. Next, a first pad 320 is formed to connect the anode terminal of the first light emitting cell D1. In addition, the second pad 330 is formed to connect the cathode terminal of the tenth light emitting cell D10.

In addition, the connection of the light emitting cells may be configured in a series/parallel type structure.

37 is a circuit diagram modeling a case in which light emitting cells are configured in a series/parallel form according to an embodiment of the present invention.

Referring to FIG. 37 , a plurality of light emitting cells D1 to D8 has a structure connected in parallel with adjacent light emitting cells while having a series connection. Each of the light emitting cells D1 to D8 is formed independently of each other through the definition of the cell regions 401 to 408 . As described above, the anode electrodes of the light emitting cells D1 to D8 are formed through the lower electrode. Further, the wiring between the cathode electrode of the light emitting cells D1 to D8 and the anode electrode of the adjacent light emitting cell is formed through the formation of the upper electrode and appropriate wiring. However, the lower electrode is formed on the second semiconductor layer, and the upper electrode is formed while shielding the space between adjacent cell regions.

Finally, the first pad 410 to which the positive power voltage V+ is supplied is electrically connected to the lower electrode formed on the second semiconductor layer of the first light emitting cell D1 or the third light emitting cell D3, and the negative power supply voltage V− The second pad 420 to which is supplied is electrically connected to an upper electrode that is a cathode terminal of the sixth light emitting cell D6 or the eighth light emitting cell D8.

Accordingly, in FIG. 37 , the input light emitting cell corresponds to the first light emitting cell D1 and the third light emitting cell D3, and the output light emitting cell corresponds to the sixth light emitting cell D6 and the eighth light emitting cell D8.

According to the present invention described above, the light generated in the active layer of each light emitting cell is reflected toward the substrate from the lower electrode and the upper electrode, and the flip-chip type light emitting cells are electrically on one substrate through the wiring of the upper electrode. Connected. The upper electrode is shielded from the outside through the second interlayer insulating film. The first pad to which the positive power voltage is supplied is electrically connected to the lower electrode of the light emitting cell closest to the positive power voltage. In addition, the second pad to which the negative power voltage is supplied is electrically connected to the upper electrode of the light emitting cell that is closest to the negative power voltage.

Accordingly, in the flip-chip type, the process of mounting a plurality of chips on a sub-mount substrate and implementing two terminals for external power through wiring arranged on the sub-mount substrate is solved. In addition, the spaced space between the cell regions is shielded through the upper electrode, so that the reflection of light toward the substrate can be maximized.

In addition, the second interlayer insulating layer protects the plurality of laminated structures disposed between the substrate and the second interlayer insulating layer from external temperature and humidity. Accordingly, a structure capable of being directly mounted on a substrate without intervention of a separate packaging means is realized.

In particular, since a plurality of light emitting cells are implemented in a flip-chip type on one substrate, there is an advantage that commercial power can be directly used while excluding voltage drop, level conversion, or waveform conversion with respect to the supplied commercial power source. .

Configuration of the optical member and MJT LED module including the same according to the first embodiment

Hereinafter, with reference to FIGS. 3 and 4 and FIGS. 38 to 44 , a detailed configuration and function of the optical member and the MJT LED module including the optical member according to the first embodiment of the present invention will be described.

Referring back to FIG. 3 , the optical member 530 according to the first embodiment may include a lower surface 531 and an upper surface 535 , and may also include a flange 537 and a leg portion 539 . . The lower surface 531 includes a concave portion 531a, and the upper surface 535 includes a concave surface 535a and a convex surface 535b.

The lower surface 531 is made of a plane having a substantially disk shape, and the concave portion 531a is located in the central portion. The lower surface 531 need not be flat, and various concavo-convex patterns may be formed.

On the other hand, the inner surface of the concave portion 531a has a side surface 533a and an upper end surface 133b, the upper end surface 533b is perpendicular to the central axis C, and the side surface 533a is an upper end surface ( 533b) to the inlet of the concave portion 531a. Here, when the central axis (C) is aligned to coincide with the optical axis (L) of the MJT LED 500 , it is defined as the central axis of the optical member 530 which becomes the center of the light directing distribution emitted from the optical member 530 . do.

The concave portion 531a may have a shape that becomes narrower as it goes up from the inlet. That is, the side surface 533a approaches the central axis C from the entrance to the upper end surface 533b. Accordingly, the area of the top surface 533b can be made relatively smaller than the inlet. The side surface 533a may have a relatively gentle slope near the top surface 533b.

The top surface 533b area is defined in a narrower area than the inlet area of the concave portion 531a. Further, the area of the top surface 533b may be limited to a region smaller than the area surrounded by the inflection line formed by the concave surface 535a and the convex surface 535b of the upper surface 535 . Furthermore, the top surface 533b region may be located within the cavity 521a region of the MJT LED 500 , that is, a region narrower than the light emission region.

In the upper surface 533b region, when the optical axis L of the MJT LED and the central axis C of the optical member 530 are misaligned, the direction distribution of light emitted through the upper surface 535 of the optical member 530 changes. to alleviate Accordingly, the area of the top surface 533b may be minimized in consideration of the alignment error between the MJT LED 500 and the optical member 530 .

Meanwhile, the upper surface 535 of the optical member 530 includes a concave surface 535a and a convex surface 535b continuously connected from the concave surface 535a with respect to the central axis C. A line where the concave surface 535a and the convex surface 535b meet becomes an inflection line. The concave surface 535a refracts the light emitted near the central axis C of the optical member 530 at a relatively large angle to disperse the light near the central axis C. In addition, the convex surface 535b increases the amount of light emitted to the outside of the central axis C.

The upper surface 535 and the concave portion 531a have a symmetrical structure with respect to the central axis C. For example, the upper surface 535 and the concave portion 531a may have a mirror-symmetric structure with respect to a surface passing through the central axis C, and further, may have a rotating body shape with respect to the central axis C. In addition, the shape of the concave portion 531a and the upper surface 535 may have various shapes according to a required light directing distribution.

On the other hand, the flange 537 connects the upper surface 535 and the lower surface 531 and limits the external size of the optical member. Concave-convex patterns may be formed on the side surface and the lower surface 531 of the flange 537 . Meanwhile, the leg portion 539 of the optical member 530 is coupled to the printed circuit board 510 to support the lower surface 531 to be spaced apart from the printed circuit board 510 . The coupling is made in such a way that the tip of each of the leg parts 539 is adhered to the printed circuit board 510 by, for example, an adhesive, or each of the leg parts 539 is fitted into a hole formed in the printed circuit board 510 . .

The optical member 530 is positioned to be spaced apart from the MJT LED 500 , and thus, an air gap is formed in the concave portion 531a. The housing 521 of the MJT LED 500 is located below the lower surface 531 , and further, the wavelength conversion layer 525 of the MJT LED 500 is separated from the concave portion 531a and below the lower surface 531 . can be located Accordingly, it is possible to prevent light traveling in the concave portion 531a from being absorbed by the housing 521 or the wavelength conversion layer 525 and lost.

According to this embodiment, by forming a plane perpendicular to the central axis C in the concave portion 531a, even if an alignment error between the MJT LED 500 and the optical member 530 occurs, the output from the optical member 530 is generated. A change in the light directing distribution can be mitigated. Moreover, since a relatively sharp apex is not formed in the concave portion 531a, optical member fabrication becomes easy.

38 is a cross-sectional view for explaining various modified examples of the optical member. Here, various modifications of the concave portion 531a of FIG. 3 will be described.

In FIG. 38(a) , a portion near the central axis C among the top surfaces 533b perpendicular to the central axis C described in FIG. 3 forms a downwardly convex surface. Light incident near the central axis C can be primarily controlled by the convex surface.

FIG. 38(b) is similar to FIG. 38(a), except that, among the upper surfaces of FIG. 38(a), a surface perpendicular to the central axis C is formed to be convex upward. Since the top surface is a mixture of an upward convex surface and a downwardly convex surface, it is possible to mitigate the light directing distribution change due to an alignment error between the MJT LED and the optical member.

In FIG. 38(c) , a portion near the central axis C among the upper surfaces 533b perpendicular to the central axis C described in FIG. 3 forms a convex surface. Light incident near the central axis C can be further dispersed by the convex surface.

FIG. 38(d) is similar to FIG. 38(c), except that a surface perpendicular to the central axis C among the upper surfaces of FIG. 38(c) is convex downward. Since the top surface is a mixture of an upward convex surface and a downwardly convex surface, it is possible to mitigate the light directing distribution change due to an alignment error between the MJT LED and the optical member.

39 is a cross-sectional view of an optical member for explaining an MJT LED module according to another embodiment of the present invention.

Referring to FIG. 39A , a light scattering pattern 533c may be formed on the upper surface 533b. The light scattering pattern 533c may be formed as a concave-convex pattern. Furthermore, a light scattering pattern 535c may be formed on the concave surface 535a. The light scattering pattern 535c may also be formed as a concave-convex pattern.

In general, a relatively large luminous flux is concentrated near the central axis C of the optical member. Furthermore, in the embodiments of the present invention, since the top surface 533b is a plane perpendicular to the central axis C, the light flux may be more concentrated near the central axis C. Accordingly, by forming the light scattering patterns 533c and 535c on the upper end surface 533b and/or the concave surface 535a, the light flux near the central axis C can be dispersed.

Referring to FIG. 39(b) , a material layer 539a having a refractive index different from that of the optical member 530 may be positioned on the top surface 533b. The material layer 539a may have a higher refractive index than the optical member, and thus the path of light incident to the top surface 533b may be changed.

Furthermore, a material layer 39b having a refractive index different from that of the optical member 530 may be positioned on the concave surface 535a. The material layer 39b may have a higher refractive index than the optical member, and thus the refraction angle of light emitted through the concave surface 535a may be increased.

The light scattering patterns 533c and 535c of FIG. 39A and the material layers 539a and 539b of FIG. 39B may also be applied to various optical members of FIG. 38 .

40 is a cross-sectional view showing the dimensions of the MJT LED module used in the simulation. Here, the reference numerals of FIGS. 3 and 4 are used.

The diameter of the cavity 521a of the MJT LED 500 is 2.1 mm, and the height is 0.6 mm. The wavelength conversion layer 525 fills the cavity 521a and has a flat surface. On the other hand, the separation distance (d) of the lower surface 531 of the MJT LED 500 and the optical member 530 is 0.18 mm, and the optical axis L of the MJT LED 500 and the central axis C of the optical member are arranged to be aligned with each other.

Meanwhile, the height H of the optical member 530 is 4.7 mm, the width W1 of the upper surface is 15 mm, and the width W2 of the concave surface 535a is 4.3 mm. In addition, the width w1 of the inlet of the concave portion 531a located on the lower surface 531 is 2.3 mm, the width w2 of the upper surface 533b is 0.5 mm, and the height h of the concave portion 531a ) is 1.8 mm.

41 is a graph for explaining the shape of the optical member of FIG. Here, (a) is a cross-sectional view for explaining the reference point (P), the distance (R), the incident angle (θ1), and the emission angle (θ5), (b) is the change of the distance (R) according to the incident angle (θ1) and (c) shows the change of (θ5/θ1) according to the incident angle (θ1). On the other hand, FIG. 42 shows the beam propagation direction by setting the beams incident to the optical member 530 from the reference point P at intervals of 3°.

Referring to Figure 41 (a), the reference point (P) represents the light emission point of the MJT LED (500) located on the optical axis (L). It is appropriate to set the reference point P to be located on the outer surface of the wavelength conversion layer 525 in order to exclude the influence of light scattering by the phosphor in the MJT LED 500 .

Meanwhile, θ1 represents an angle incident to the optical member 530 from the reference point P, that is, an incident angle, and θ5 represents an angle emitted from the upper surface 535 of the optical member 530 , that is, an exit angle. Meanwhile, R represents the distance from the reference point P to the inner surface of the concave portion 531a.

Referring to Fig. 41(b), since the top surface 533b of the concave portion 531a is perpendicular to the central axis C, R slightly increases as θ1 increases. The enlarged graph shown inside the graph of FIG. 41(b) shows that R increases. On the other hand, R decreases as θ1 increases at the side surface 533a of the concave portion 531a, and has a shape that slightly increases near the inlet.

Referring to FIG. 41(c) , (θ5/θ1) sharply increases near the concave surface 535a as θ1 increases, and decreases relatively gently near the convex surface 535b. In this embodiment, as shown in Fig. 42, the luminous fluxes of light emitted from the vicinity of the concave surface 535a and the convex surface 535b may overlap each other. That is, the refraction angle of the light emitted toward the concave surface 535a near the inflection line among the light incident from the reference point P may be greater than the refraction angle of the light emitted toward the convex surface 535b. Therefore, by controlling the shapes of the concave surface 535a and the convex surface 535b while making the upper end surface 533b of the concave portion 531a a planar shape, the concentration of the light flux near the central axis C can be alleviated. have.

43 is a graph showing the illuminance distribution according to the MJT LED and the optical member of FIG. 40. (a) shows the illuminance distribution of the MJT LED, and (b) shows the illuminance distribution of the MJT LED module according to the use of the optical member. The illuminance distribution was expressed as the magnitude of the luminous flux density incident on the screen spaced apart by 25 mm.

As shown in Fig. 43(a), the MJT LED 500 exhibits a symmetrical illuminance distribution with respect to the optical axis C, and the luminous flux density is very high in the center and rapidly decreases toward the periphery. When the optical member 530 is applied to the MJT LED 500, as shown in FIG. 43(b), a substantially uniform luminous flux density within a radius of 40 mm can be obtained.

44 is a graph showing the light directing distribution according to the MJT LED and the optical member of FIG. 40, (a) is the light directing distribution of the MJT LED, (b) is the light directing distribution of the MJT LED module according to the use of the optical member indicates The light directivity distribution represents the luminous intensity according to the directivity angle at a point 5 m away from the reference point P, and the directivity distributions in directions orthogonal to each other are superimposed on one graph.

As shown in FIG. 44( a ), the light emitted from the MJT LED 500 has a luminous intensity of 0° at an irradiance angle, that is, a large luminous intensity at the center, and the luminous intensity tends to decrease as the directional angle increases. On the other hand, when an optical member is applied, as shown in FIG. 44(b) , the luminous intensity is relatively low at an orientation angle of 0°, and the luminous intensity is relatively large near 70°.

Therefore, by applying the optical member 530, by changing the light directing distribution of the strong MJT LED at the center, it is possible to uniformly backlight a relatively large area.

Configuration of the optical member and MJT LED module including the same according to the second embodiment

Hereinafter, with reference to FIGS. 45 to 52, the optical member according to the second embodiment of the present invention and a detailed configuration and function of the MJT LED module including the optical member will be described.

45 is a cross-sectional view illustrating an MJT LED module according to an embodiment of the present invention, and FIGS. 46 (a), (b) and (c) are views taken along lines a-a, b-b, and c-c of FIG. admit. In this case, the a-a line is a line on the lower surface of the optical member, the c-c line is a line on the upper surface of the optical member, and the b-b line is a cutting line in the middle of the height of the diffusion lens between the a-a line and the c-c line. In addition, FIG. 47 is a view for explaining the optical member of the MJT LED module shown in FIG. 45 in more detail, and FIG. 48 is a view showing the distribution of light beam angles when the optical member shown in FIG. 47 is used.

Referring to FIG. 45 , the MJT LED module includes an MJT LED 500 and an optical member 630 made of a resin or glass material disposed on the MJT LED 500 . Although the printed circuit board 510 is partially shown to show one MJT LED module, a plurality of MJT LED modules regularly arranged on one printed circuit board 510 are included to provide a backlight module ( 700) is formed.

First, since the MJT LED 500 and the printed circuit board 510 are the same as those described above with reference to FIGS. 3 and 4 in relation to the first embodiment, the overlapping description will be omitted, and the first embodiment of the present invention The optical member 630 according to the second embodiment will be mainly described.

Referring to FIG. 45 , the optical member 630 may include a lower surface 631 and an opposite light exit surface 635 , and may also include a leg portion 639 . The lower surface 631 includes a concave light incident portion 631a. The light exit surface 635 generally has a curved surface convex toward the upper portion, and includes a flat surface 635a in the upper center. The flat surface 635a is located at a position corresponding to the concave portion of the conventional optical member, and the optical member 630 of the present embodiment is provided without a concave portion in the upper center of the light exit surface due to the structure of the light incident portion 631a to be described in detail below. The light around the optical axis can be spread widely. The light incident part 631a has a substantially vertical cross-section, and has a shape that is gradually converged from the lower inlet adjacent to the MJT LED 500 toward the apex of the upper end.

Referring to (a) of FIG. 46 , the lower surface 631 of the optical member 630 has a circular shape. In addition, the lower portion of the light incident portion 631a is located in the center of the lower surface 631 , and the lower portion of the light incident portion 631a is circular. The light incident part 631a maintains a circular shape from the bottom entrance to just before the top apex, but its diameter gradually decreases from the bottom to the top. Referring to (c) of FIG. 46 , the upper flat surface 635a of the optical member 630 also has a circular shape.

46 (a), (b) and (c) of FIG. 46 , the optical member 630 has a circular lower surface 631 and a shape that gradually decreases toward the upper portion. A change in the diameter of the outer circular shape may be greater in the upper side of the optical member 630 compared to the change in the diameter of the outer circular shape in the lower side of the optical member 630 . The circular shape diameter of the light incident part 631a gradually decreases.

Referring to FIG. 47 , the optical axis L, which is the central axis of the optical member 630 , is shown. In order to obtain a uniform light distribution using the optical member 630, the luminous intensity peak must exist at an angle of 60 degrees or more from the optical axis L, and within 50 degrees from the optical axis L to obtain such optical characteristics. It is important to spread the light effectively. In FIG. 47 , a reference line r forming 50 degrees with respect to the optical axis L is shown.

In order to effectively spread the light within 50 degrees from the optical axis L, in the angular range between the optical axis L and the reference line r, that is, within 50 degrees from the optical axis L, any The shortest distance 'b' from one point p to the vertex of the light incident part 631a is greater than the shortest distance 'a' from the same point p to the side surface of the light incident part 631a. As described above, when b>a, the light incident part 631a may contribute to widely spreading the light traveling within 50 degrees from the optical axis L at an angle of 60 degrees or more from the optical axis L. On the other hand, when b < a, with respect to the light traveling within 50 degrees from the optical axis L, the light incident part 631a hardly contributes to spreading the light. For this reason, in the prior art, a separate concave portion was required to spread the light widely in the upper center of the light exit surface. In other words, the optical member 630 according to the present invention has a curvature structure of the light incident part 631a that satisfies the condition b > a in a range of 50 degrees from the optical axis L. It is now possible to omit the recesses.

In this case, the height of the light incident part 631a is preferably greater than the radius R of the lower end entrance of the light incident part 631a. Furthermore, it is even better that the height H is greater than 1.5 times the radius R. In addition, the light incident portion 631a forms a boundary with air having a lower refractive index than a resin or glass material at a lower portion thereof, and a light exit surface also forms a boundary with air having a lower refractive index than a resin or glass material at an upper portion thereof.

FIG. 48 well shows the distribution of light directivity angles obtained by using the optical member of FIG. 47 . Referring to FIG. 48 , it can be seen that the luminous intensity peak is formed at a position approximately 72 degrees away from the optical axis L, and the light is widely spread and distributed. From the result of FIG. 48, the optical member 630 according to the present invention, without a concave portion in the upper center of the light outgoing surface, of the light incident portion 631a satisfying the condition b > a within 50 degrees from the optical axis L It can be seen that, due to the curvature structure, light within 60 degrees from the optical axis L can be effectively diffused, and the light can be uniformly diffused and distributed.

49 is a view for explaining an optical member according to another embodiment of the present invention. 49, in the optical member 630 of this embodiment, the curvature structure of the light incident portion 631a is the same as that of the optical member of the previous embodiment shown in FIG. Accordingly, the light incident portion 631a satisfies the condition b>a within 50 degrees from the optical axis L. However, unlike the optical member of the previous embodiment including a flat flat surface in the upper center at the upper center of the light exit surface, the optical member 630 of the present embodiment is provided with a curved surface 35b convex in the upper center of the light exit surface.

FIG. 50 well shows a light beam distribution angle obtained by using the optical member of FIG. 49 . Referring to FIG. 50 , it can be seen that the luminous intensity peak is formed at a position approximately 72 degrees away from the optical axis L, and the light is widely spread and distributed. In addition, it is difficult to find a large difference when comparing the light directivity angle distribution shown in FIG. 50 with the light directivity angle distribution shown in FIG. 48 . If the light incident portion 631a satisfies the condition b > a within 50 degrees from the optical axis L, there is no significant difference in the distribution of the light beam angle whether the upper center of the light exit surface is formed as a flat surface or a convex surface. can be known

51 (a) and (b) each shows an optical member and a directivity angle distribution curve according to Comparative Example 1.

The optical member shown in FIG. 51(a) has the same shortest distance 'b' from any point on the optical axis to the vertex of the light incident portion within a range of 50 degrees from the optical axis to the side of the light incident portion. It is greater than the distance 'a' and at the same time has a concave portion in the upper center of the light exit surface. The distribution of the beam angle under this condition can be seen from FIG. 51 (b), and according to this, it can be seen that the distribution of the beam angle has little difference from the distribution of the beam angle of the previous embodiment. This means that the concave portion in the upper center of the light exit surface does little to change the distribution of the light beam angle under the condition b > a.

52 (a) and (b) each shows an optical member and a directivity angle distribution curve according to Comparative Example 2.

The optical member shown in Fig. 52(a) has the same shortest distance 'b' from any point on the optical axis to the vertex of the light incident portion within a range of 50 degrees from the optical axis to the side of the light incident portion. It is smaller than the distance 'a' and at the same time has a concave portion in the upper center of the light exit surface. It can be seen from FIG. 52 (b) that the light beam distribution angle distribution under this condition has little difference from the light beam angle distribution of Comparative Example 1 and the above-described Examples. . This shows that the concave part in the upper center of the light exit surface spread the light within 50 degrees from the optical axis under the condition b < a.

In the above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications and changes are made by those skilled in the art within the technical spirit and scope of the present invention. This is possible.

Claims (32)

a printed circuit board including a plurality of blocks and a plurality of MJT LEDs respectively disposed on the plurality of blocks; and
a backlight module including a backlight control module that generates a signal for driving control of each of the blocks;
each block contains at least one MJT LED,
The backlight control module includes a driving control unit for on/off control and dimming control of each block,
Each MJT LED,
A plurality of light emitting cells including a first light emitting cell and a second light emitting cell, which are disposed spaced apart from each other on a single growth substrate, respectively, a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer; and a plurality of light emitting cells including an active layer disposed between the first semiconductor layer and the second semiconductor layer;
a reflective layer disposed on the first light emitting cell and electrically connected to the first light emitting cell;
an upper electrode electrically connecting the first light emitting cell to the second light emitting cell;
a first interlayer insulating film insulating the upper electrode from a side surface of the first light emitting cell; and
a first pad and a second pad disposed on the upper electrode;
The plurality of light emitting cells are connected in series between an input light emitting cell and an output light emitting cell,
the first pad is electrically connected to the input light emitting cell, and the second pad is electrically connected to the output light emitting cell;
and the upper electrode has a side surface having an inclination angle of 10 degrees to 45 degrees with respect to a surface of the first interlayer insulating layer. a printed circuit board including a plurality of blocks and a plurality of MJT LEDs respectively disposed on the plurality of blocks; and
a backlight module including a backlight control module that generates a signal for driving control of each of the blocks;
each block contains at least one MJT LED,
The backlight control module includes a driving control unit for on/off control and dimming control of each block,
Each MJT LED,
A plurality of light emitting cells including a first light emitting cell and a second light emitting cell, which are disposed spaced apart from each other on a single growth substrate, respectively, a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer; and a plurality of light emitting cells including an active layer disposed between the first semiconductor layer and the second semiconductor layer;
a reflective layer disposed on the first light emitting cell and electrically connected to the first light emitting cell;
an upper electrode electrically connecting the first light emitting cell to the second light emitting cell;
a first interlayer insulating film insulating the upper electrode from a side surface of the first light emitting cell; and
a first pad and a second pad disposed on the upper electrode;
The plurality of light emitting cells are connected in series between an input light emitting cell and an output light emitting cell,
the first pad is electrically connected to the input light emitting cell, and the second pad is electrically connected to the output light emitting cell;
Each of the light emitting cells has a via hole exposing a part of the first semiconductor layer, and the upper electrodes are connected to the first semiconductor layer of the corresponding light emitting cell through the via hole,
The side inclination angle of the layers exposed through the via hole is in the range of 10 degrees to 60 degrees. 3. The method according to claim 2,
and the upper electrode has a side surface having an inclination angle of 10 degrees to 45 degrees with respect to a surface of the first interlayer insulating layer. 4. The method of claim 3,
The upper electrode has a thickness within a range of 2000 Å to 10000 Å. 4. The method of claim 3,
Further comprising lower electrodes aligned on the second semiconductor layer of each light emitting cell,
The first interlayer insulating film exposes a portion of the lower electrode on each light emitting cell,
The upper electrode(s) electrically connected to the second semiconductor layer of the adjacent light emitting cell are connected to the exposed lower electrode through the first interlayer insulating film. 6. The method of claim 5,
Each of the lower electrodes includes a side surface having an inclination angle of 10 degrees to 45 degrees with respect to the surface of the second semiconductor layer. 6. The method of claim 5,
The thickness of the lower electrode is a backlight unit, characterized in that 2000 Å to 10000 Å. 6. The method of claim 5,
and the first interlayer insulating layer includes a side surface having an inclination angle of 10 to 60 degrees with respect to the exposed lower electrode surface. 9. The method of claim 8,
The first interlayer insulating layer has a thickness of 2000 Å to 20000 Å for the backlight unit. 6. The method of claim 5,
Further comprising a second interlayer insulating film covering the upper electrodes,
The second interlayer insulating film exposes a lower electrode aligned on the second semiconductor layer of the input light emitting cell and an upper electrode connected to the first semiconductor layer of the output light emitting cell,
The first pad and the second pad are respectively connected to the lower electrode and the upper electrode through the second interlayer insulating layer. 11. The method of claim 10,
and the second interlayer insulating layer includes a side surface having an inclination angle of 10 degrees to 60 degrees with respect to a surface of the upper electrode. 11. The method of claim 10,
The second interlayer insulating layer has a thickness of 2000 Å to 20000 Å for the backlight unit. The method according to claim 1,
The light emitting cells each have a via hole exposing a portion of the first semiconductor layer, and the upper electrodes are connected to the first semiconductor layer of the corresponding light emitting cell through the via hole. The method according to claim 1 or 2,
The upper electrode occupies an area of 30% or more and less than 100% of the total area of the MJT LED. The method according to claim 1 or 2,
The upper electrode is a backlight unit having a plate or sheet shape in which a ratio of width to width is in a range of 1:3 to 3:1. The method according to claim 1 or 2,
At least one of the upper electrodes has a width or a width greater than that of a corresponding light emitting cell. The method according to claim 1 or 2,
The first light emitting cell and the second light emitting cell are separated by a mesa etch region exposing the growth substrate, and side surfaces of the layers exposed by the mesa etch region have an inclination angle of 10 to 60 degrees with respect to the substrate. unit. The method according to claim 1 or 2,
the backlight control module provides a driving voltage to the plurality of MJT LEDs in the backlight module;
The backlight control module is a backlight unit that independently controls driving of each of the plurality of MJT LEDs. 19. The method of claim 18,
The backlight control module,
A backlight unit further comprising a driving power generator. 20. The method of claim 19,
The driving power generator independently provides the driving voltage to each of the plurality of MJT LEDs in the backlight module,
The driving control unit performs the dimming control of the at least one MJT LED by performing PWM control according to the dimming signal of the backlight control module. 21. The method of claim 20,
The driving control unit generates a dimming control signal of which a pulse width is modulated or a duty ratio is modulated. 20. The method of claim 19,
The driving control unit is configured to independently detect and control the driving current of each of the plurality of MJT LEDs in the backlight module. 23. The method of claim 22,
The driving control unit controls the dimming control of the at least one MJT LED by controlling a driving current of the at least one MJT LED among the plurality of MJT LEDs according to a dimming signal. 21. The method of claim 20,
The first pad of the MJT LED is connected to the driving power generator,
The second pad of the MJT LED is a backlight unit connected to a driving control unit. 19. The method of claim 18,
The backlight unit further comprising an optical member disposed on the MJT LED or the substrate to correspond to the plurality of MJT LEDs. 26. The method of claim 25,
Each of the plurality of blocks is a backlight unit including the one optical member. 19. The method of claim 18,
The plurality of blocks are M×N,
The plurality of blocks constitute an M×N matrix arrangement of a backlight unit. 19. The method of claim 18,
At least one block among the plurality of blocks includes a plurality of MJT LEDs. The method according to claim 1 or 2,
Further comprising a plurality of FETs electrically connected to the plurality of MJT LEDs and a FET controller for controlling on and off of the FETs,
The number of the plurality of FETs is the same as the number of the plurality of MJT LEDs. 30. The method of claim 29,
and the FET controller includes at least one of the plurality of FETs. 31. The method of claim 30,
The number of FETs not included in the FET controller among the plurality of FETs is less than the number of the plurality of MJT LEDs. 31. The method of claim 30,
The FET controller is a backlight unit including all of the plurality of FETs.

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