KR20130030279A - Light emitting device having semiconductor layers spaced apart from each other and method of fabricating the same - Google Patents

Abstract

PURPOSE: A light emitting device with separated semiconductor layers and a manufacturing method thereof are provided to prevent metal byproducts due to an etching process by adopting an etch stop layer when light emitting cells are separated. CONSTITUTION: A plurality of light emitting cells(LS1,LS2) are separately located on the upper side of a substrate. The light emitting cells include a first conductive top semiconductor layer(125a), an active layer, and a second conductive bottom semiconductor layer(129a). Electrodes are located between the substrate and the light emitting cells and include each extension part which is extended to the adjacent light emitting cell. An etch stop layer(131) is located between the electrodes and the light emitting cells. One side of a wire is connected to a top semiconductor layer and the other side thereof is connected to the electrode via the etch stop layer.

Description

LIGHT EMITTING DEVICE HAVING SEMICONDUCTOR LAYERS SPACED APART FROM EACH OTHER AND METHOD OF FABRICATING THE SAME}

The present invention relates to a light emitting device and a method of manufacturing the same, and more particularly to a light emitting device having a semiconductor layer spaced apart from each other and a method of manufacturing the same.

Gallium nitride-based light emitting diodes are widely used as display devices and backlights. In addition, the light emitting diode consumes less power and has a longer lifespan than existing light bulbs or fluorescent lamps, thereby replacing its incandescent lamps and fluorescent lamps, thereby expanding its use area for general lighting.

Recently, light emitting diodes that emit light by directly connecting the light emitting diodes to a high voltage DC power source or a high voltage AC power source have been commercialized. Light emitting diodes that can be used in connection with high voltage direct current or alternating current power sources are described, for example, in WO 2004/023568 (Al), "Light-Emitting Devices with Light-Emitting Components." LIGHT-EMITTING DEVICE HAVING LIGHT-EMITTING ELEMENTS Entitled SAKAI et. Al.

According to WO 2004/023568 (Al), a series LED array is formed in which LEDs are two-dimensionally connected on an insulating substrate such as a sapphire substrate. These series LED arrays can be driven under high voltage direct current power supplies. In addition, such LED arrays are connected in anti-parallel on the sapphire substrate to provide a single chip light emitting device that can be driven by a high voltage AC power supply.

Since the light emitting device forms light emitting cells on a substrate used as a growth substrate, for example, a sapphire substrate, there is a limitation in the structure of the light emitting cells and there is a limit in improving light extraction efficiency. In order to solve such a problem, a method of manufacturing a light emitting device having a plurality of light emitting cells by applying a substrate separation process is referred to as Korean Patent Publication No. 10-0599012 entitled "Light emitting diode having a thermally conductive substrate and a method of manufacturing the same". Has been disclosed.

1 to 4 are cross-sectional views illustrating a method of manufacturing a light emitting device according to the prior art.

Referring to FIG. 1, semiconductor layers including a buffer layer 23, an N-type semiconductor layer 25, an active layer 27, and a P-type semiconductor layer 29 are formed on a sacrificial substrate 21. The first metal layer 31 is formed on the field, and the second metal layer 53 is formed on the substrate 51 separate from the sacrificial substrate 21. The first metal layer 31 may include a reflective metal layer. The second metal layer 53 is bonded to the first metal layer 31 so that the substrate 51 is bonded over the semiconductor layers.

Referring to FIG. 2, after the substrate 51 is bonded, the sacrificial substrate 21 is separated by using a laser lift-off process. In addition, after the substrate 21 is separated, the remaining buffer layer 23 is removed, and the surface of the N-type semiconductor layer 25 is exposed.

Referring to FIG. 3, the semiconductor layers 25, 27, 29 and the metal layers 31, 53 are patterned and spaced apart from each other by using a photo and etching technique, and the metal patterns 40. Light emitting cells 30 are formed on a partial region of the substrate. The light emitting cells 30 include a patterned P-type semiconductor layer 29a, an active layer 27a, and an N-type semiconductor layer 25a.

Referring to FIG. 4, metal wires 57 are formed to electrically connect the upper surfaces of the light emitting cells 30 and the metal patterns 40 adjacent thereto. The metal wires 57 connect the light emitting cells 30 to form a series array of light emitting cells. In order to connect the metal wires 57, an electrode pad 55 may be formed on the N-type semiconductor layer 25a, and an electrode pad may also be formed on the metal patterns 40. Two or more such arrays may be formed, and there is provided a light emitting diode in which these arrays are connected in parallel and driven under an AC power source.

According to the conventional technology, since the substrate 51 can be variously selected, the heat dissipation performance of the light emitting diode can be improved, and the light extraction efficiency can be improved by treating the surface of the N-type semiconductor layer 25a. In addition, since the first metal layer 31a reflects the light traveling from the light emitting cells 30 to the substrate 51 side including the reflective metal layer, the luminous efficiency may be further improved.

However, according to the related art, during the patterning of the semiconductor layers 25, 27, 29 and the metal layers 31, 53, an etch by-product of a metal material adheres to the sidewall of the light emitting cell 30, thereby forming an N-type semiconductor layer ( An electrical short may be caused between 25a) and the P-type semiconductor layer 29a. In addition, the surface of the first metal layer 31a exposed during the etching of the semiconductor layers 25, 27, and 29 may be easily damaged by plasma. This etching damage is further exacerbated when the first metal layer 31a includes a reflective metal layer such as Ag or Al. Damage to the surface of the metal layer 31a by the plasma degrades the adhesion of the wirings 57 or the electrode pads formed thereon, resulting in device defects.

Meanwhile, according to the related art, the first metal layer 31 may include a reflective metal layer, and thus reflects light traveling from the light emitting cells 30 toward the substrate. However, the reflective metal layer exposed to the space between the light emitting cells 30 is etched and is easily oxidized as it is exposed to the outside. In particular, the oxidation of the exposed reflective metal layer is not limited to the exposed portion, but proceeds to the area under the light emitting cells 30 to lower the reflectance of the reflective metal layer.

Patent Document 1: International Publication No. WO 2004/023568 Patent Document 2: Korean Registered Publication No. 10-0599012

It is an object of the present invention to provide a light emitting device capable of preventing an electrical short circuit in a light emitting cell by metal etching by-products and a method of manufacturing the same.

Another object of the present invention is to provide a light emitting device capable of preventing deformation of the reflective metal layer by etching or oxidation, and a method of manufacturing the same.

The present invention provides a light emitting device having a plurality of light emitting cells and a method of manufacturing the same. A light emitting device according to one aspect of the present invention, a substrate; A plurality of light emitting cells spaced apart from each other on the substrate, each of the plurality of light emitting cells including an upper semiconductor layer of a first conductivity type, an active layer, and a lower semiconductor layer of a second conductivity type; Electrodes spaced apart from each other and positioned between the substrate and the light emitting cells, each electrode electrically connected to a corresponding lower semiconductor layer of the second conductivity type, the electrodes having extensions extending toward neighboring light emitting cells; An etch stop layer disposed between the regions of the light emitting cells and the electrodes, the etching preventing layer having at least a portion extending below edges of neighboring light emitting cells and having an opening exposing an extension of the electrode; Side insulating layers covering side surfaces of the light emitting cells; Wiring lines electrically connected to the light emitting cells spaced apart from side surfaces of the light emitting cells by the side insulating layer, each end of which is electrically connected to an upper semiconductor layer of one light emitting cell, and the other end of the opening of the etch stop layer. Wires electrically connected to electrodes electrically connected to lower semiconductor layers of neighboring light emitting cells. By adopting the etch stop layer, it is possible to prevent the electrodes are exposed during the etching of the light emitting cells to prevent the generation of metal etching by-products.

Meanwhile, an interlayer insulating layer may be interposed between the substrate and the electrodes. The interlayer insulating layer prevents the electrodes from being electrically shorted by the bonding metal.

In addition, the electrodes may include a reflective layer and a protective metal layer, respectively. The reflective layer may be formed of a reflective metal, but the present invention is not limited thereto, and a reflective layer in the form of a multilayer film in which layers having different refractive indices are stacked may be formed.

In addition, the reflective layer may be defined in a lower region of the lower semiconductor layer, and the protective metal layer may cover side surfaces and a lower surface of the reflective layer. Accordingly, the reflective layer may be prevented from being exposed to the outside to prevent oxidation of the reflective layer.

Meanwhile, the upper semiconductor layers may have roughened surfaces, respectively. The light extraction efficiency is increased by the roughened surface.

The substrate may be a sapphire substrate. Generally, when using a substrate separation process, sapphire and other thermally conductive substrates are adopted as the bonding substrate, but the present invention is not particularly limited to the bonding substrate, but rather, the sapphire substrate is adopted as the preferred substrate. Thus, by using the same substrate as the growth substrate of the semiconductor layers as the bonding substrate, the substrate separation process and subsequent patterning processes can be performed more safely.

According to another aspect of the present invention, there is provided a light emitting device having a plurality of light emitting cells, forming a compound semiconductor layer on a sacrificial substrate, and forming an etch stop layer having openings exposing the compound semiconductor layers on the compound semiconductor layers. And forming electrodes which fill the openings and partially extend over the etch stop layer. Thereafter, the sacrificial substrate is removed, and the compound semiconductor layers are patterned to separate the light emitting cells. In this case, the electrodes may be prevented from being exposed by the etch stop layer, thus preventing the occurrence of metal etch byproducts.

Specifically, the light emitting device manufacturing method, a compound semiconductor layer comprising a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer interposed between the first and second conductive semiconductor layers on a sacrificial substrate. The first conductive semiconductor layer is disposed close to the sacrificial substrate; Forming an etch stop layer on the compound semiconductor layers, the etch stop layer having openings exposing a second conductivity type semiconductor layer; Forming electrodes having an extension filling the openings of the etch stop layer and extending over the etch stop layer, the electrodes being spaced apart from each other; Forming an interlayer insulating layer on the electrodes; Bonding a substrate on the interlayer insulating layer; Removing the sacrificial substrate to expose the first conductivity type semiconductor layer; Patterning the compound semiconductor layers to expose the etch stop layer to form a plurality of light emitting cells spaced apart from each other; Forming openings covering the light emitting cells, the side insulating layers exposing at least a portion of an upper surface of the first conductive semiconductor layer, and patterning the etch stop layer to expose the electrodes; And forming interconnections connecting the first conductive semiconductor layer to the exposed electrodes.

According to the manufacturing method, when the compound semiconductor layers are patterned to form a plurality of light emitting cells, the etch stop layer prevents the electrodes from being exposed. Therefore, it is possible to prevent the metal etching by-products from sticking to the side walls of the light emitting cells. The etch stop layer is formed of an insulating layer such as a silicon oxide film or a silicon nitride film.

Further, forming the electrodes may include forming a reflective layer in the openings of the etch stop layer and forming a protective metal layer covering the reflective layer. Thus, the reflective layer can be prevented from being exposed to the outside.

In addition, a roughened surface may be formed on the exposed upper surface of the first conductivity-type semiconductor layer.

The present invention also provides a light emitting device having semiconductor layers spaced from each other. The light emitting device, the substrate; At least two lower conductive semiconductor layers disposed on the substrate and spaced apart from each other; An active layer positioned on each of the lower semiconductor layers and an upper semiconductor layer of a first conductivity type; Electrodes positioned between the substrate and the lower semiconductor layer, each of which is electrically connected to corresponding lower semiconductor layers of the second conductivity type, each having an extension extending toward a neighboring lower conductive layer; Electrodes; An etching having a region between the lower semiconductor layer region of the second conductivity type and the electrodes, at least a portion of which extends below edges of the neighboring second conductivity type lower semiconductor layers and has an opening exposing an extension of the electrode; Barrier layer; A side insulating layer covering side surfaces of the second conductive lower semiconductor layer, the active layer, and the first conductive upper semiconductor layer; A wiring formed on the side insulating layer to electrically connect the first and second conductive semiconductor layers, one end of which is electrically connected to the upper semiconductor layer of the first conductive type, and the other end of which is the etch stop layer And wires electrically connected to electrodes electrically connected to the lower semiconductor layers of the second conductivity type adjacent to each other through the openings of the second conductive type.

According to the present invention, it is possible to provide a light emitting device capable of preventing an electrical short circuit in a light emitting cell by preventing the generation of metal etching by-products, and can further provide a light emitting device having a plurality of light emitting cells and a method of manufacturing the same. . Further, according to the present invention, since the reflective layer is not exposed to the etching process and is not exposed to the outside, deformation due to etching or oxidation is prevented.

1 to 4 are cross-sectional views illustrating a method of manufacturing a light emitting device having a plurality of light emitting cells according to the prior art.
5 is a cross-sectional view illustrating a light emitting device having a plurality of light emitting cells according to an embodiment of the present invention.
6 to 15 are cross-sectional views illustrating a method of manufacturing a light emitting device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the width, length, thickness, and the like of the components may be exaggerated for convenience. Like numbers refer to like elements throughout.

5 is a cross-sectional view illustrating a light emitting device having a plurality of light emitting cells according to an embodiment of the present invention.

Referring to FIG. 5, the light emitting device includes a substrate 151, a plurality of light emitting cells LS1 and LS2, wires 155, electrodes E1 and E2, an etch stop layer 131, and a side insulating layer ( 153, and an interlayer insulating layer 137 and bonding metals 141 and 143.

The substrate 151 is separated from the growth substrate for growing the compound semiconductor layers and is a bonding substrate bonded to the compound semiconductor layers that have been grown. The bonding substrate 151 may be a sapphire substrate, but is not limited thereto, and may be another kind of insulating or conductive substrate. In particular, the use of a sapphire substrate as the growth substrate is preferable because it has the same coefficient of thermal expansion as the growth substrate.

The plurality of light emitting cells LS1 and LS2 are spaced apart from each other on the substrate 151, and the upper semiconductor layer 125a of the first conductivity type, the active layer 127a, and the lower semiconductor layer of the second conductivity type, respectively. 129a. The active layer 127a is interposed between the upper and lower semiconductor layers 125a and 129a. The lower semiconductor layer 129a and the upper semiconductor layer 125a may have the same area.

The active layer 127a and the upper and lower semiconductor layers 125a and 129a may be formed of III-N-based compound semiconductors such as (Al, Ga, In) N semiconductors. The upper and lower semiconductor layers 125a and 129a may be a single layer or multiple layers, respectively. For example, the upper and / or lower semiconductor layers 125a and 129a may include a contact layer and a cladding layer, and may also include a superlattice layer. In addition, the active layer 127a may have a single quantum well structure or a multiple quantum well structure. Preferably, the first conductivity type is n-type, and the second conductivity type is p-type. The upper semiconductor layers 125a may be formed of an n-type semiconductor layer having a relatively low resistance, and thus the thicknesses of the upper semiconductor layers 125a may be relatively thick. Therefore, it is easy to form the rough surface R on the upper surface of the upper semiconductor layer 125a, and the rough surface R improves the extraction efficiency of light generated in the active layer 127a.

The electrodes E1 and E2 are spaced apart from each other between the substrate 151 and the light emitting cells LS1 and LS2. The electrode E1 is electrically connected to the lower semiconductor layer 129a of the light emitting cell LS1, and the electrode E2 is electrically connected to the lower semiconductor layer 129a of the light emitting cell LS2. On the other hand, the electrodes E1 and E2 each have an extension extending to the neighboring light emitting cell side. That is, the electrode E1 has an extension extending to the light emitting cell (not shown) adjacent thereto and the electrode E2 has an extension extending toward the light emitting cell LS1.

The electrodes E1 and E2 may have reflective layers 133a and 133b and protective metal layers 135a and 135b. The reflective layers 133a and 133b may be formed of a metal material having high reflectance such as silver (Ag) or aluminum (Al), or an alloy thereof. In addition, the reflective layers 133a and 133b may be formed in a multilayer structure of layers having different refractive indices. In this case, the reflective layer may have through holes, and a protective metal layer may be connected to the light emitting cells through the through holes. The reflective layers 133a and 133b may be directly contacted with the lower semiconductor layers 129a of the light emitting cells LS1 and LS2, but another ohmic contact layer may be interposed between the reflective layer and the lower semiconductor layer. The protective metal layers 135a and 135b cover the reflective layer to prevent the reflective layer from being exposed to the outside. The protective metal layer may be formed of a single layer or multiple layers, for example, Ni, Ti, Ta, Pt, W, Cr, Pd and the like. As shown, the protective metal layers 135a and 135b may extend to form an extension.

The etch stop layer 131 is positioned between the regions between the light emitting cells LS1 and LS2 and the electrodes E1 and E2. That is, the etch stop layer 131 is located at the bottom of the spaces generated as the light emitting cells LS1 and LS2 are separated. The etch stop layer 131 prevents the extension portions of the electrodes E1 and E2 from being exposed in the separated region. The etch stop layer 131 extends below edges of at least some of the neighboring light emitting cells LS1 and LS2. The etch stop layer 131 may be located below the bottom surface of the light emitting cells LS1 and LS2, but a part thereof may protrude into a region between the light emitting cells. The etch stop layer 131 is formed of an insulating layer, such as a silicon oxide film or a silicon nitride film.

The extensions of the electrodes extend below the etch stop layer 131, and the etch stop layer 131 has openings that expose the extensions of the electrodes E1 and E2. These openings provide a passage through which the wirings 155 can be electrically connected to the electrodes E1, E2.

Meanwhile, the side insulating layer 153 covers side surfaces of the light emitting cells LS1 and LS2 to prevent the wires 155 from shorting the upper semiconductor layer and the lower semiconductor layer of the light emitting cells. The side insulating layer 153 may also cover a portion of the upper surface of the light emitting cells and may extend over the etch stop layer 131. In this case, the side insulating layer 153 has openings exposing openings of the etch stop layer.

The wirings 155 electrically connect the light emitting cells LS1 and LS2 to form a series array. Each of the wirings 155 is electrically connected to an electrode of which one end is electrically connected to the upper semiconductor layer 125a of one light emitting cell, and the other end thereof is electrically connected to the lower semiconductor layer 129a of the light emitting cell neighboring thereto. Connected. For example, one end of the wiring 155 is electrically connected to the upper semiconductor layer 125a of the light emitting cell LS1, and the other end thereof is electrically connected to the electrode E2 through an opening of the etch stop layer 131. Meanwhile, pads (not shown) may be formed on the upper semiconductor layers 125a and the electrodes E1 and E2 to electrically connect the wires 155. The wirings 155 are insulated from side surfaces of the light emitting cells LS1 and LS2 by the side insulating layer 153.

A series array of light emitting cells is formed on the substrate 151 by the wirings 155. Accordingly, the series array may be connected to a high voltage DC power supply for driving. Meanwhile, at least two series arrays may be formed on the substrate 151 by the wires 155, and the arrays may be connected in reverse parallel to each other and driven by an AC power source. Alternatively, a series array may be formed by wirings on a substrate, and the series array may be driven by an AC power supply by being connected to a bridge rectifier formed on the substrate. The bridge rectifier may also be formed by connecting the light emitting cells by wirings.

Meanwhile, an interlayer insulating layer 137 may be interposed between the electrodes E1 and E2 and the substrate 151, and bonding metals 141 and 143 may be interposed between the interlayer insulating layer 137 and the substrate 151. This may be intervened. The interlayer insulating layer 137 prevents the electrodes E1 and E2 from being shorted to each other by the substrate 151 or the bonding metals 141 and 143.

The bonding metals 141 and 143 improve adhesion between the interlayer insulating layer 137 and the bonding substrate 151 to prevent the bonding substrate 151 from being separated from the interlayer insulating layer 137.

6 to 11 are cross-sectional views illustrating a method of manufacturing a light emitting device according to an embodiment of the present invention.

Referring to FIG. 6, compound semiconductor layers are formed on the sacrificial substrate 121. The sacrificial substrate 121 may be a sapphire substrate, but is not limited thereto, and may be another hetero substrate. Meanwhile, the compound semiconductor layers include the first conductive semiconductor layer 125 and the second conductive semiconductor layer 129 and an active layer 129 interposed therebetween. The first conductivity type semiconductor layer 125 is located close to the sacrificial substrate 121. The first and second conductivity-type semiconductor layers 125 and 129 may be formed in a single layer or multiple layers, respectively. In addition, the active layer 127 may be formed in a single quantum well structure or a multiple quantum well structure.

The compound semiconductor layers may be formed of a III-N-based compound semiconductor, and may be grown on the sacrificial substrate 121 by a process such as metal organic chemical vapor deposition (MOCVD) or molecular beam deposition (MBE). Can be.

Meanwhile, before forming the compound semiconductor layers, a buffer layer (not shown) may be formed. The buffer layer is adopted to mitigate lattice mismatch between the sacrificial substrate 121 and the compound semiconductor layers, and may be a gallium nitride-based material layer such as gallium nitride or aluminum nitride.

Referring to FIG. 7, an etch stop layer 131 is formed on the compound semiconductor layers, for example, the second conductivity type semiconductor layer 129. The etch stop layer 131 has openings that expose the second conductive semiconductor layer 129. The openings are formed on the light emitting cell regions corresponding to the light emitting cell regions, and are formed to have a smaller area than the light emitting cell regions.

The etch stop layer 131 is formed by forming an insulating layer such as a silicon oxide film or a silicon nitride film on the second conductive semiconductor layer 129 and patterning the same by using a photolithography and an etching process.

Reflective layers 133a and 133b are formed in the openings. The reflective layers 133a and 133b may be formed of a metal material having a high reflectance such as Ag, Al, or an alloy thereof, and may be formed by stacking layers having different refractive indices. When the reflective layer 131 is formed of a metal layer, the reflective layer 131 may be formed using a plating or deposition technique, for example, using a lift off process. Meanwhile, an ohmic contact layer (not shown) may be formed on the second conductive semiconductor layer 129 before forming the reflective layers. In addition, the reflective layers may be formed first, and the etch stop layer 131 may be formed thereafter.

Referring to FIG. 8, protective metal layers 135a and 135b covering the reflective layers 133a and 133b are formed. The protective metal layers 135a and 135b respectively fill the openings of the etch stop layer 131 and extend to the top surface of the etch stop layer 131. The protective metal layers 135a and 135b are formed to be spaced apart from each other. The protective metal layers 135a and 135b may be formed of a single layer or multiple layers, for example, Ni, Ti, Ta, Pt, W, Cr, Pd, or the like.

In the present embodiment, the reflective layers 133a and 133b and the protective metal layers 135a and 135b constitute the electrodes E1 and E2. However, the electrodes E1 and E2 are not limited to this and may be formed of a single metal layer. For example, the formation of the reflective layers may be omitted, and the electrode may be formed of only the protective metal layers 135a and 135b.

Referring to FIG. 9, an interlayer insulating layer 137 is formed on the electrodes E1 and E2. The interlayer insulating layer 137 may cover the electrodes E1 and E2 and fill gaps between the electrodes E1 and E2. The material of the interlayer insulating layer is not particularly limited, and may be formed of a silicon oxide film or a silicon nitride film.

Referring to FIG. 10, a bonding metal 141 is formed on the interlayer insulating layer 137, and a bonding metal 143 is formed on a separate substrate 151. The bonding metal 141 may be formed of, for example, AuSn (80 / 20wt%). The substrate 151 is not particularly limited, but may be a substrate having the same thermal expansion coefficient as the sacrificial substrate 121, for example, a sapphire substrate.

Referring to FIG. 11, a substrate 151 is bonded on the interlayer insulating layer 137 by bonding the bonding metals 141 and 143 to face each other. Subsequently, the sacrificial substrate 121 is removed and the first conductivity type semiconductor layer 125 is exposed. The sacrificial substrate 121 may be separated by laser lift off (LLO) technology or other mechanical or chemical methods. At this time, the buffer layer is also removed to expose the first conductivity-type semiconductor layer 125. 12 is a diagram illustrating the first conductive semiconductor layer 125 facing upward after the sacrificial substrate 121 is removed.

Referring to FIG. 13, the compound semiconductor layers are patterned to form a plurality of light emitting cells LS1 and LS2. Each of the light emitting cells LS1 and LS2 includes a patterned first conductive semiconductor layer 125a, a patterned active layer 127a, and a patterned second conductive semiconductor layer 129a. The compound semiconductor layers may be patterned using photolithography and etching processes, which are generally known as mesa etching processes. In this case, the compound semiconductor layers between the light emitting cells are removed by the etching process, and the etch stop layer 131 is exposed. The etch stop layer 131 prevents the electrodes E1 and E2 below it from being exposed during the etching process. To this end, etching is performed in a limited area on the etch stop layer 131.

Referring to FIG. 14, side insulating layers 153 covering side surfaces of the light emitting cells LS1 and LS2 are formed. The side insulating layer 153 may be formed by forming an insulating layer covering the light emitting cells, and then patterning the insulating layer 153 using a photolithography and an etching process. The side insulating layer may be formed of, for example, SiO ₂ , SiN, MgO, TaO, TiO ₂ , or a polymer. The side insulating layer 153 covers the first conductivity type semiconductor layer 125a, the active layer 127a, and the second conductivity type semiconductor layer 129a exposed on the side surfaces of the light emitting cells. The side insulating layer 153 may also cover a portion of the top surface of the light emitting cells LS1 and LS2, as shown. In addition, the side insulating layer 153 may extend over the etch stop layer 131. Openings 131a for exposing the extensions of the electrodes E1 and E2 are formed in the etch stop layer 131 during or after the side insulating layer 153 is formed.

Referring to FIG. 15, wires 155 are formed to electrically connect the light emitting cells LS1 and LS2. The wires 155 electrically connect the electrode E2 electrically connected to the first conductive semiconductor layer 125a of the light emitting cell LS1 and the second conductive semiconductor layer 129a of the light emitting cell LS2. do. That is, one end of the wiring 155 is electrically connected to the first conductivity type semiconductor layer 125a of the light emitting cell LS1, and the other end thereof is connected to the second conductivity type semiconductor layer 129a of the light emitting cell LS2. It is electrically connected to the electrically connected electrode E2.

Prior to forming the interconnections 155, pads (not shown) may be used to form first conductive semiconductor layers 125a and / or electrodes E1 and E2 to improve adhesion or ohmic contact characteristics of the interconnections. It can be formed on.

Meanwhile, a roughened surface R may be formed on the first conductivity-type semiconductor layers 125a on the light emitting cells by PEC (photoelectric chemical) etching or the like. The roughened surface R may be performed before forming the wirings. Thereby, the light emitting element of FIG. 5 is completed.

Although the embodiments of the present invention have been described above by way of example, the present invention is not limited to the above-described embodiments and may be variously modified and changed by those skilled in the art without departing from the spirit of the present invention. . Such modifications and variations are included in the scope of the present invention as defined in the following claims.

Claims (8)

Board;
At least two lower conductive semiconductor layers disposed on the substrate and spaced apart from each other;
An active layer positioned on each of the lower semiconductor layers and an upper semiconductor layer of a first conductivity type;
Electrodes positioned between the substrate and the lower semiconductor layer, each of which is electrically connected to corresponding lower semiconductor layers of the second conductivity type, each having an extension extending toward a neighboring lower conductive layer; Electrodes;
An etching having a region between the lower semiconductor layer region of the second conductivity type and the electrodes, at least a portion of which extends below edges of the neighboring second conductivity type lower semiconductor layers and has an opening exposing an extension of the electrode; Barrier layer;
A side insulating layer covering side surfaces of the second conductive lower semiconductor layer, the active layer, and the first conductive upper semiconductor layer;
A wiring formed on the side insulating layer to electrically connect the first and second conductive semiconductor layers, one end of which is electrically connected to the upper semiconductor layer of the first conductive type, and the other end of which is the etch stop layer And a wire electrically connected to an electrode electrically connected to an adjacent lower semiconductor layer of a second conductivity type through an opening of the second conductive type. The light emitting device of claim 1, wherein the electrodes each include a reflective layer and a protective metal layer. The light emitting device of claim 2, wherein the reflective layer is defined in a lower region of the lower semiconductor layer, and the protective metal layer covers side surfaces and a lower surface of the reflective layer. The light emitting device of claim 3, wherein the upper semiconductor layer of the first conductivity type has a roughened surface. The light emitting device of claim 4, further comprising an interlayer insulating layer interposed between the substrate and the electrodes. The light emitting device according to any one of claims 1 to 5, wherein the lower semiconductor layer is a p-type semiconductor layer, and the upper semiconductor layer is an n-type semiconductor layer. The light emitting device of claim 6, wherein the light emitting device is driven regardless of the polarity direction of the power source. The light emitting device of claim 7, wherein the side insulating layer is formed of at least one of SiO 2, SiN, MgO, TaO, TiO ₂ , and a polymer.

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