CN114188455A - Preparation method of flip mini light-emitting diode chip - Google Patents
Preparation method of flip mini light-emitting diode chip Download PDFInfo
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- CN114188455A CN114188455A CN202111528404.4A CN202111528404A CN114188455A CN 114188455 A CN114188455 A CN 114188455A CN 202111528404 A CN202111528404 A CN 202111528404A CN 114188455 A CN114188455 A CN 114188455A
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/382—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
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Abstract
The invention discloses a preparation method of a flip mini light-emitting diode chip, which is characterized in that a binding bonding layer is directly electrically connected with a conductive step and a current expansion layer, a traditional PAD conductive layer is not arranged in the middle, and the binding bonding layer can play a role in bonding and also can play a role in electric conduction, so that the traditional PAD conductive layer can be cancelled.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a preparation method of an inverted mini light-emitting diode chip.
Background
In recent years, the light emitting diode gradually occupies two fields of backlight display and direct display by virtue of the advantages of energy conservation, high brightness, high durability, long service life, lightness and the like;
along with the rising of the small-distance display, the LED display chip gradually approaches to the mini LED, the mini LED chip formally enters a stable mass production stage, and then the problems of the improvement of the performance and the reliability of the mini LED chip and the reduction of the cost are faced; referring to fig. 1 and 2, a PAD conductive layer is required to be disposed in a conventional mini flip-chip mini led chip, and the PAD conductive layer assists the indirect electrical connection between the bonding layer and the conductive step; in the manufacturing method, a PAD conducting layer is needed to be evaporated on the current expansion layer, then a reflecting layer is deposited on the conducting layer, a bonding layer is arranged on the reflecting layer, and the bonding layer can be electrically connected with the current expansion layer through the PAD conducting layer, so that the wire resistance is increased, and the luminous efficiency is reduced.
Therefore, how to reduce the wire resistance and improve the light emitting efficiency becomes a technical problem that needs to be improved in the existing flip mini light emitting diode chip technology.
Disclosure of Invention
The application aims to provide a preparation method of a flip mini light-emitting diode chip, and aims to solve the problems of large wire resistance and low luminous efficiency of the traditional mini flip mini light-emitting diode chip.
The scheme adopted by the application to solve the technical problems is as follows:
in a first aspect, the present application provides a flip-chip mini LED chip comprising
A substrate;
the epitaxial layer comprises a first semiconductor layer and a second semiconductor layer which are arranged at intervals, and a conductive step is arranged on the first semiconductor layer;
a current spreading layer sputtered on the second semiconductor layer;
and one end of the binding bonding layer is contacted with the conductive step and is directly and electrically connected, and the other end of the binding bonding layer is contacted with the current expansion layer and is directly and electrically connected.
In some embodiments of the present application, a bottom metal layer is disposed on a side of the N-type bonding layer close to the conductive step, and the bottom metal layer may directly form ohmic contact with the conductive step.
In some embodiments of the present application, the epitaxial layer includes a buffer layer, a first semiconductor layer, an active layer, and a second semiconductor layer, which are sequentially grown; an etching groove is formed in the epitaxial layer, the bottom of the etching groove is formed in the first semiconductor layer, and a conductive step is formed in the first semiconductor layer.
In some embodiments of the present application, the bonding layer further includes a bragg reflection layer, the bragg reflection layer is evaporated on the epitaxial layer and the current extension layer, and coats the outer surfaces of the epitaxial layer and the current extension layer, the binding bonding layer is disposed on the bragg reflection layer, and the bragg reflection layer is provided with a conductive through hole for the binding bonding layer to pass through.
In some embodiments of the present application, the bonding layer includes an N-type bonding layer and a P-type bonding layer, the conductive via includes an N-type conductive via and a P-type conductive via, the N-type bonding layer passes through the N-type conductive via and the conductive step contact and directly electrically connect, and the P-type bonding layer passes through the P-type conductive via and the current spreading layer contact and electrically connect.
In some embodiments of the present application, an isolation trench is disposed at the edge of the epitaxial layer, the isolation trench is formed by removing the epitaxial layer through etching, and the bragg reflection layer is filled in the isolation trench.
In some embodiments of the present application, an etching portion is disposed on an upper edge of the current spreading layer, and a bottom of the etching portion is the second semiconductor layer.
In a second aspect, a method for manufacturing a flip mini led chip is also provided, which includes the following steps:
providing a substrate;
preparing an epitaxial layer on the substrate, wherein the epitaxial layer comprises a first semiconductor layer and a second semiconductor layer which are arranged at intervals, and a conductive step is etched on the first semiconductor layer;
sputtering a current spreading layer on the second semiconductor layer;
and preparing a binding bonding layer, wherein one end of the binding bonding layer is in contact with the conductive step and is directly and electrically connected, and the other end of the binding bonding layer is in contact with the current expansion layer and is directly and electrically connected.
In some embodiments of the application, after the sputtering of the current spreading layer on the second semiconductor layer, performing gas surface treatment on the ITO surface of the current spreading layer, so that the ITO surface can directly form ohmic contact with the bottom metal layer bound to the bonding layer, and etching to form a pattern and then corroding the current spreading layer with an ITO corrosion solution.
In some embodiments of the present application, the epitaxial layer includes a buffer layer, a first semiconductor layer, an active layer, and a second semiconductor layer that are sequentially grown on the substrate, the surface of the epitaxial layer is patterned, and the first semiconductor layer is etched on the surface of the epitaxial layer by ICP, so as to form a conductive step on the first semiconductor layer.
In some embodiments of the present application, before the bonding layer is prepared, an evaporation bragg reflection layer is further included to coat the epitaxial layer and the current extension layer, and a conductive through hole for the bonding layer to pass through is etched on the bragg reflection layer.
In some embodiments of the present application, the etched conductive via includes an N-type conductive via and a P-type conductive via, the bonding layer prepared on the bragg reflector includes an N-type bonding layer and a P-type bonding layer, the N-type bonding layer passes through the N-type conductive via and the conductive step contact and direct electrical connection, the P-type bonding layer passes through the P-type conductive via and the current spreading layer contact and electrical connection.
In some embodiments of the present application, the ICP etching the epitaxial layer further includes patterning by a photolithography process, removing a portion of the second semiconductor layer, the active layer, and the first semiconductor layer by ICP etching, and forming a conductive step on the first semiconductor layer.
In some embodiments of the present application, before sputtering the current spreading layer on the second semiconductor layer, ISO etching is performed on an edge of the epitaxial layer, and the substrate is exposed to form an isolation trench between chips.
In some embodiments of the present application, after the patterning the current spreading layer, etching an upper edge of the current spreading layer to expose the second semiconductor layer.
In some embodiments of the present application, a Lift-Off process is used to form an N-type bonding layer and a P-type bonding layer disposed over the bragg reflector layer.
The application provides a preparation method of flip mini emitting diode chip, through binding bonding layer directness and electrically conductive step, electric current extension layer electric connection, the centre does not set up traditional PAD conducting layer, bind the bonding layer, both can play the bonding effect, can play the electrically conductive effect again, just can cancel traditional PAD conducting layer, reduce into individual layer metal electrically conductive heat conduction by traditional two-layer metal electrically conductive heat conduction, can reduce the line resistance among the electric current conduction process, and then promote the luminous efficacy of chip, the heat spreading ability and the reliability of chip have further been strengthened, the technology step has been reduced simultaneously, raw materials and human cost have been reduced by a wide margin.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a top view structural diagram of a conventional flip-chip mini LED chip in the prior art;
FIG. 2 is a longitudinal cross-sectional view of FIG. 1;
FIG. 3 is a top view structural diagram of the flip-chip mini LED chip of the present invention;
FIG. 4 is a longitudinal cross-sectional view of FIG. 3 of the present invention;
FIG. 5 is a flow chart of the process for manufacturing the flip-chip mini LED chip of the present invention.
Description of the element symbols:
11-substrate, 12-epitaxial layer, 13-conductive step, 14-current spreading layer, 15-bragg reflecting layer, 16-binding bonding layer, 17-PAD conductive layer, 121-buffer layer, 122-first semiconductor layer, 123-active layer, 124-second semiconductor layer, 151-N type conductive via, 152-P type conductive via, 161-N type bonding layer, 162-P type bonding layer.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments, not all embodiments, of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and for simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be considered as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or including indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present application, the word "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment described herein as exemplary is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is presented to enable any person skilled in the art to make and use the invention. In the following description, details are set forth for the purpose of explanation. It will be apparent to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and processes are not shown in detail to avoid obscuring the description of the invention with unnecessary detail. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles disclosed herein.
The Bonding layer can also be called Bonding layer, the current spreading layer can also be called TCL current spreading layer, and the Bragg reflection layer can also be called DBR Bragg reflection layer. The traditional mini inverted mini light-emitting diode chip manufacturing steps are as follows: an epitaxial layer is manufactured, namely a buffer layer grows on a substrate, then a first semiconductor layer, an active layer and a second semiconductor layer grow in sequence, then a chip is manufactured, firstly, the surface of the epitaxial layer is subjected to patterning treatment by utilizing a photoetching technology, then ICP (inductively coupled plasma) etching is carried out to the first semiconductor layer, then, a current expansion layer is deposited by utilizing a magnetron sputtering technology, patterning treatment is carried out, then, a PAD conducting layer is evaporated, an N-type PAD conducting layer and a P-type PAD conducting layer are formed by utilizing a Lift-Off technology, then, a Bragg reflecting layer is deposited by utilizing an evaporation technology, then, after a pattern is formed by photoetching, ICP etching is carried out, an N-type DBR through hole and a P-type DBR through hole are formed, then, a bonding layer is evaporated, an N-type binding bonding layer and a P-type binding bonding layer are formed by utilizing a Lift-Off technology, wherein the N-type binding bonding layer is electrically connected with the N-type PAD conducting layer through the N-type DBR through hole, the P-type binding bonding layer is electrically connected with the P-type PAD conducting layer through the P-type DBR through hole.
Referring to fig. 5, the main body of the present embodiment is a method for manufacturing a flip-chip mini led chip, including the following steps: providing a substrate 11; preparing an epitaxial layer 12 on the substrate 11, wherein the epitaxial layer 12 comprises a buffer layer 121, a first semiconductor layer 122, an active layer 123 and a second semiconductor layer 124 which are grown in sequence; patterning the surface of the epitaxial layer 12, etching the surface of the epitaxial layer 12 to the first semiconductor layer 122 through ICP (inductively coupled plasma), and forming a conductive step 13 on the first semiconductor layer 122; sputtering the current spreading layer 14 on the second semiconductor layer 124, and performing patterning processing on the current spreading layer 14; evaporating a Bragg reflection layer on the substrate 11, the first semiconductor layer 122, the second semiconductor layer 124 and the current expansion layer 14, and performing ICP (inductively coupled plasma) etching on the Bragg reflection layer 15 to prepare an N-type conductive through hole 151 and a P-type conductive through hole 152, wherein the N-type conductive through hole 151 is communicated with the conductive step 13, and the P-type conductive through hole 152 is communicated with the current expansion layer 14; preparing an N-type bonding layer 161 and a P-type bonding layer 162 on the Bragg reflection layer 15, wherein the N-type bonding layer 161 is arranged in the N-type conductive through hole 151 and electrically connected with the conductive step 13, and the P-type bonding layer 162 is arranged in the P-type conductive through hole 152 and electrically connected with the current expansion layer 14. The bonding layer 16 can be used as a conductive layer, so that the traditional PAD conductive layer 17 can be eliminated, the line resistance in the current conduction process is reduced, and the luminous efficiency of the chip is improved.
Referring to fig. 1 to 4, fig. 1 is a top view structural diagram of a conventional flip-chip mini led chip, and fig. 2 is a longitudinal sectional view of the conventional flip-chip mini led chip; FIG. 3 is a top view structural diagram of the flip-chip mini LED chip of the present application; FIG. 4 is a longitudinal cross-sectional view of a flip-chip mini LED chip of the present application; in the application, the N-type bonding layer 161 and the P-type bonding layer 162 can be replaced by bonding layers, the metal at the bottom layer of the conventional mini LED chip bonding layer 16 is Al, and since Al cannot directly form ohmic contact with the current expansion layer 14, the PAD conductive layer 17 is required to be used as an intermediate metal for transition; in the application, Cr can be directly adopted as the bottom metal of the binding bonding layer 16, and the bottom metal Cr is directly electroplated on the bottom metal Al of the traditional bonding layer, so that the bottom metal Cr of the binding bonding layer 16 is directly electrically connected with the current expansion layer 14 in ohmic contact, and the purposes that the original binding bonding layer 16 can be used as a bonding layer and a conducting layer, and the traditional PAD conducting layer 17 of the inverted mini light-emitting diode chip is cancelled are achieved; or still adopt Al as binding bonding layer 16 bottom metal, after current extension layer 14 sputtering is accomplished, handle current extension layer 14 surface with special gas for the bottom metal Al that binds bonding layer 16 directly forms ohmic contact's electric connection with current extension layer 14, thereby reaches original binding bonding layer 16, can do the bonding layer, can do the conducting layer again, cancels the purpose of traditional flip mini emitting diode chip PAD conducting layer 17.
No matter the metal at the bottom layer of the binding bonding layer 16 is changed into Cr or the surface of the current expansion layer 14 is treated by special gas, the binding bonding layer 16 and the current expansion layer 14 can directly form ohmic contact electric connection, namely the binding bonding layer and the current expansion layer are used as a conducting layer, and a PAD conducting layer 17 of a traditional flip mini light-emitting diode chip can be eliminated; the original two-layer metal electric conduction and heat conduction of the flip mini light-emitting diode chip is directly reduced to single-layer metal electric conduction and heat conduction, so that the wire resistance in the current conduction process can be reduced, and the light-emitting efficiency of the chip is improved; meanwhile, the heat diffusion capability of the chip can be increased, and the reliability of the chip is improved; but also reduces the process steps and greatly reduces the cost of raw materials and manpower.
In some embodiments of the present application, after sputtering the current spreading layer 14 on the second semiconductor layer, performing a gas surface treatment on the ITO surface of the current spreading layer 14, so that the ITO surface can directly form an ohmic contact with the underlying metal layer, and then etching the current spreading layer 14 with an ITO etching solution. The current spreading layer 14 is an indium tin oxide layer, i.e., an ITO (indium tin oxide) -TCL structure, and the ITO structure is subjected to surface treatment in a vacuum environment by a gas containing fluorine ions, so that the ITO structure can directly form ohmic contact with metal Al of the bottom metal layer, i.e., the current spreading layer 14 can be directly electrically connected with the binding bonding layer 16. Wherein TCL is short for transparent conductive layer, and is a transparent conductive film layer.
In some embodiments of the present application, after the etching of the conductive step, a gas surface treatment is further performed on the surface of the conductive step, so that the surface of the conductive step can directly form an ohmic contact with the underlying metal layer. The bottom metal layer is usually Al, and after the surface of the conductive step is treated by gas containing silicon ions, the bottom metal layer can be directly in ohmic contact with the conductive step, so that the traditional mode of arranging the PAD conductive layer is replaced.
In some embodiments of the present application, etching the epitaxial layer 12 by ICP further includes patterning by a photolithography process, removing a portion of the second semiconductor layer 124, the active layer 123 and the first semiconductor layer 122 by ICP etching, and forming the conductive step 13 on the first semiconductor layer 122. In a traditional inverted mini light emitting diode chip, one end of a PAD conducting layer 17 is in ohmic contact with a conducting step 13, and the other end of the PAD conducting layer is in ohmic contact with a binding bonding layer 16. In the present application, ICP (inductively coupled plasma) etching is used to selectively remove a portion of the second semiconductor layer 124, the active layer 123 and the first semiconductor layer 122, and expose the conductive step 13. And the surface of the conductive step 13 is processed to make the conductive step 13 and the binding bonding layer 16 directly form ohmic contact.
In some embodiments of the present application, before sputtering the current spreading layer 14 on the second semiconductor layer 124, ISO etching is performed on the edge of the epitaxial layer 12 and exposes the substrate 11 to form an isolation trench between chips. ISO etching, i.e. patterning in a photolithographic process, followed by ICP (inductively coupled plasma) etching selectively removes portions of the epitaxial layer 12. Next, ISO etching is performed, i.e., a pattern is formed by a photolithography process, and then ICP (inductively coupled plasma) etching selectively removes a portion of the epitaxial layer 12 to expose the substrate 11, thereby forming an isolation trench between chips.
In some embodiments of the present application, the patterning of the current spreading layer 14 further includes etching the upper edge of the current spreading layer 14 to expose the second semiconductor layer 124. The current spreading layer 14 is partially removed by patterning by photolithography and then by using an ITO (indium tin oxide) etchant.
In some embodiments of the present application, after the bragg reflector is fabricated, O2 plasma bombardment is performed on the surface of the bragg reflector for 5min with a power of 100W, then the surface of the bragg reflector is washed by water with a throwing barrel, then purged with hot nitrogen and dried, and then baked in an oven for 30min at a temperature of 80 ℃, so as to completely clean the surface of the bragg reflector and increase the adhesion between Cr and the bragg reflector.
In some embodiments of the present application, a Lift-Off process is used to form the N-type bonding layer 161 and the P-type bonding layer 162 disposed over the bragg reflector layer 15.
Example 1: referring to fig. 3 to 5, in some embodiments of the present application, the flip-chip mini led chip is prepared by the following method, S1: firstly, providing a substrate 11; s2: then, growing a buffer layer 121, a first semiconductor layer 122, an active layer 123 and a second semiconductor layer 124 on the substrate 11 in sequence; s3: then, Mesa etching is performed, i.e., a pattern is formed by a photolithography process, and then ICP (inductively coupled plasma) etching selectively removes a portion of the second semiconductor layer 124, the active layer 123, and the first semiconductor layer 122 to expose the conductive step 13; s4: then, performing ISO etching, namely forming a pattern by using a photoetching process, and then selectively removing part of the epitaxial layer 12 by using ICP (inductively coupled plasma) etching to expose the substrate 11 and form an isolation groove between chips; s5: next, sputtering a current spreading layer 14 on the second semiconductor layer, forming a pattern by a photolithography process, and removing a part of the current spreading layer 14 by using an ITO (indium tin oxide) etchant; s6: then evaporating a Bragg reflection layer 15, forming a pattern by a photoetching process, and then selectively removing part of the Bragg reflection layer 15 by ICP (inductively coupled plasma) etching to form an N-type conductive through hole 151 and a P-type conductive through hole 152; s7: then, a binding bonding layer 16 is manufactured, a graph is formed through a photoetching process, then the binding bonding layer 16 is evaporated, an N-type binding bonding layer 16 and a P-type binding bonding layer 16 are formed on the Bragg reflection layer 15 through a Lift-Off process, the N-type binding bonding layer 16 is electrically connected with the Mesa through an N-type DBR conductive through hole, and the P-type binding bonding layer 16 is electrically connected with the current expansion layer 14 through a P-type DBR conductive through hole.
Example 2: referring to fig. 3 and 4, in some embodiments of the present application, a flip-chip mini led chip may be further fabricated by first providing a substrate 11, and then sequentially growing a buffer layer 121, a first semiconductor layer 122, an active layer 123, and a second semiconductor layer 124 on the substrate 11; then, Mesa etching is performed, i.e., a pattern is formed by a photolithography process, and then ICP (inductively coupled plasma) etching selectively removes a portion of the second semiconductor layer 124, the active layer 123, and the first semiconductor layer 122 to expose the conductive step 13; then, performing ISO etching, namely forming a pattern by using a photoetching process, and then selectively removing part of the epitaxial layer 12 by using ICP (inductively coupled plasma) etching to expose the substrate 11 and form an isolation groove between chips; then, sputtering a current spreading layer 14 on the second semiconductor layer, then processing the ITO surface by using special gas to enable ITO and metal Al to directly form ohmic contact, then forming a pattern by a photoetching process, and then removing part of the current spreading layer 14 by using ITO (indium tin oxide) corrosive liquid; then evaporating a Bragg reflection layer 15, forming a pattern by a photoetching process, and then selectively removing part of the Bragg reflection layer 15 by ICP (inductively coupled plasma) etching to form an N-type conductive through hole 151 and a P-type conductive through hole 152; and then, manufacturing a binding bonding layer 16, forming a pattern by using a photoetching process, evaporating the binding bonding layer 16, forming an N-type binding bonding layer 16 and a P-type binding bonding layer 16 which are arranged on the Bragg reflection layer 15 by using a Lift-Off process, wherein the N-type binding bonding layer 16 is electrically connected with the conductive step 13 through an N-type DBR conductive through hole, and the P-type binding bonding layer 16 is electrically connected with the current expansion layer 14 through a P-type DBR conductive through hole.
The bottom metal suitable for the binding bonding layer 16 in the preparation method of embodiment 1 is Gr, and may also be Ag, and the bottom metal suitable for the binding bonding layer 16 in the preparation method of embodiment 2 includes, but is not limited to, Cr, Al, Ag, Ti, Pt, and Ni. In embodiment 2, the ITO surface is treated with a special gas, so that the ITO and the metal Al can directly form an ohmic contact, and the method of either embodiment 1 or embodiment 2 can make the bonding layer directly electrically connected to the current spreading layer 14, thereby achieving the effect of eliminating the PAD conductive layer 17; the prepared mini LED chip has small volume and meets the requirement of small size.
In some embodiments of the present application, a flip-chip mini led chip is further provided, which is manufactured by the above manufacturing method, please refer to fig. 3 and 4, and includes a substrate 11; an epitaxial layer 12, wherein the epitaxial layer 12 comprises a buffer layer 121, a first semiconductor layer 122, an active layer 123 and a second semiconductor layer 124 which are grown in sequence; an etching groove is formed in the surface of the epitaxial layer 12, the bottom of the etching groove is formed in the first semiconductor layer 122, and a conductive step 13 is formed on the first semiconductor layer 122; a current spreading layer 14, said current spreading layer 14 being sputtered on the second semiconductor layer 124; a bragg reflector evaporated on the substrate 11, the first semiconductor layer 122, the second semiconductor layer 124 and the current spreading layer 14, wherein the bragg reflector 15 is provided with an N-type conductive through hole 151 and a P-type conductive through hole 152, the N-type conductive through hole 151 is communicated with the conductive step 13, and the P-type conductive through hole 152 is communicated with the current spreading layer 14; an N-type bonding layer 161, wherein the N-type bonding layer 161 is disposed on the bragg reflector 15, and the N-type bonding layer 161 is disposed in the N-type conductive via 151 and electrically connected to the conductive step 13; and the P-type bonding layer 162 is arranged on the Bragg reflection layer 15, and the P-type bonding layer 162 is embedded into the P-type conductive through hole 152 and is electrically connected with the current expansion layer 14.
In some embodiments of the present application, isolation trenches are provided at the edges of the epitaxial layer 12, and the isolation trenches are formed by etching away the epitaxial layer 12. In some embodiments of the present application, the underlying metals of the N-type bonding layer 161 and the P-type bonding layer 162 include at least one of Cr, Al, Ag, Ti, Pt, and Ni. In some embodiments of the present application, an etched portion is disposed on an upper edge of the current spreading layer 14, and the bottom of the etched portion is the second semiconductor layer 124.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and parts that are not described in detail in a certain embodiment may refer to the above detailed descriptions of other embodiments, and are not described herein again.
Having thus described the basic concept, it will be apparent to those skilled in the art that the foregoing detailed disclosure is to be considered merely illustrative and not restrictive of the broad application. Various modifications, improvements and adaptations to the present application may occur to those skilled in the art, although not explicitly described herein. Such modifications, improvements and adaptations are proposed in the present application and thus fall within the spirit and scope of the exemplary embodiments of the present application.
Also, this application uses specific language to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.
Similarly, it should be noted that in the preceding description of embodiments of the application, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the embodiments. This method of disclosure, however, is not intended to require more features than are expressly recited in the claims. Indeed, the embodiments may be characterized as having less than all of the features of a single embodiment disclosed above.
Numerals describing the number of components, attributes, etc. are used in some embodiments, it being understood that such numerals used in the description of the embodiments are modified in some instances by the use of the modifier "about", "approximately" or "substantially". Unless otherwise indicated, "about", "approximately" or "substantially" indicates that the number allows a variation of ± 20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximations that may vary depending upon the desired properties of the individual embodiments. In some embodiments, the numerical parameter should take into account the specified significant digits and employ a general digit preserving approach. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the range are approximations, in the specific examples, such numerical values are set forth as precisely as possible within the scope of the application.
For each patent, patent application publication, and other material cited in this application, such as articles, books, specifications, publications, documents, and the like, the entire contents of which are hereby incorporated by reference into this application, except for application history documents that are inconsistent with or conflict with the contents of this application, and except for documents that are currently or later become incorporated into this application as though fully set forth in the claims below. It is noted that the descriptions, definitions and/or use of terms in this application shall control if they are inconsistent or contrary to the present disclosure.
The above method for manufacturing a flip-chip mini led chip provided in the embodiments of the present application is described in detail, and a specific example is applied in the description to explain the principle and the implementation of the present invention, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for those skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A preparation method of an inverted mini light-emitting diode chip is characterized by comprising the following steps:
providing a substrate;
preparing an epitaxial layer on the substrate, wherein the epitaxial layer comprises a first semiconductor layer and a second semiconductor layer which are arranged at intervals, and a conductive step is etched on the first semiconductor layer;
sputtering a current spreading layer on the second semiconductor layer;
and preparing a binding bonding layer, wherein one end of the binding bonding layer is in contact with the conductive step and is directly and electrically connected, and the other end of the binding bonding layer is in contact with the current expansion layer and is directly and electrically connected.
2. The method for preparing the flip-chip mini light emitting diode chip as claimed in claim 1, further comprising, after sputtering the current spreading layer on the second semiconductor layer, performing surface treatment on the ITO surface of the current spreading layer by using a gas containing fluorine ions, so that the ITO surface can directly form ohmic contact with the bottom metal layer bound to the bonding layer, and etching the current spreading layer by using an ITO etching solution after forming a pattern by photolithography.
3. The method for preparing the flip mini light emitting diode chip as claimed in claim 1, wherein the epitaxial layer comprises a buffer layer, a first semiconductor layer, an active layer and a second semiconductor layer which are sequentially grown on the substrate, the surface of the epitaxial layer is subjected to patterning treatment, the surface of the epitaxial layer is etched to the first semiconductor layer through ICP, and a conductive step is formed on the first semiconductor layer.
4. The method for preparing the flip mini light emitting diode chip as claimed in claim 1, further comprising coating the epitaxial layer and the current spreading layer with a deposition Bragg reflection layer before preparing the bonding layer, and etching a conductive through hole for the bonding layer to pass through on the Bragg reflection layer.
5. The method for preparing the flip-chip mini LED chip as claimed in claim 4, wherein the etched conductive vias include N-type conductive vias and P-type conductive vias, the bonding layer prepared on the Bragg reflector includes an N-type bonding layer and a P-type bonding layer, the N-type bonding layer contacts and is directly electrically connected to the conductive step through the N-type conductive vias, and the P-type bonding layer contacts and is electrically connected to the current spreading layer through the P-type conductive vias.
6. The flip-chip mini light emitting diode of claim 4The preparation method of the chip is characterized by further comprising the step of carrying out O treatment on the Bragg reflection layer after the Bragg reflection layer is evaporated2And (4) bombarding the surface of the Bragg reflecting layer by using plasma, and cleaning the surface of the Bragg reflecting layer by washing, hot nitrogen blowing and drying and baking.
7. The method for preparing the flip-chip mini LED chip as claimed in claim 3, further comprising processing the surface of the conductive step with a gas containing silicon ions after the conductive step is etched, so that the surface of the conductive step can directly form ohmic contact with the underlying metal layer.
8. The method for preparing the flip mini light emitting diode chip as claimed in claim 1, wherein the prepared flip mini light emitting diode chip comprises
A substrate;
the epitaxial layer comprises a first semiconductor layer and a second semiconductor layer which are arranged at intervals, and a conductive step is arranged on the first semiconductor layer;
a current spreading layer sputtered on the second semiconductor layer;
and one end of the binding bonding layer is contacted with the conductive step and is directly and electrically connected, and the other end of the binding bonding layer is contacted with the current expansion layer and is directly and electrically connected.
9. The method for preparing the flip-chip mini light emitting diode chip as claimed in claim 8, wherein a bottom metal layer is disposed on one side of the bonding layer close to the conductive step, and the bottom metal layer directly forms ohmic contact with the conductive step.
10. The method for manufacturing the flip-chip mini led chip as claimed in claim 9, wherein the bottom metal layer is made of Cr or Al metal.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20110297914A1 (en) * | 2010-06-07 | 2011-12-08 | Xiamen Sanan Optoelectronics Technology Co., Ltd. | Gallium nitride-based flip-chip light-emitting diode with double reflective layers on its side and fabrication method thereof |
| CN106169531A (en) * | 2016-07-15 | 2016-11-30 | 厦门乾照光电股份有限公司 | The inverted light-emitting diode (LED) of a kind of ODR structure and preparation method, upside-down mounting high-voltage LED |
| CN110010733A (en) * | 2019-03-25 | 2019-07-12 | 大连德豪光电科技有限公司 | The preparation method and light-emitting diode chip for backlight unit of light-emitting diode chip for backlight unit |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110297914A1 (en) * | 2010-06-07 | 2011-12-08 | Xiamen Sanan Optoelectronics Technology Co., Ltd. | Gallium nitride-based flip-chip light-emitting diode with double reflective layers on its side and fabrication method thereof |
| CN106169531A (en) * | 2016-07-15 | 2016-11-30 | 厦门乾照光电股份有限公司 | The inverted light-emitting diode (LED) of a kind of ODR structure and preparation method, upside-down mounting high-voltage LED |
| CN110010733A (en) * | 2019-03-25 | 2019-07-12 | 大连德豪光电科技有限公司 | The preparation method and light-emitting diode chip for backlight unit of light-emitting diode chip for backlight unit |
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