CN116722087A - Flip light-emitting diode chip and preparation method thereof - Google Patents
Flip light-emitting diode chip and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 239000004065 semiconductor Substances 0.000 claims description 51
- 229920002120 photoresistant polymer Polymers 0.000 claims description 39
- 230000000903 blocking effect Effects 0.000 claims description 36
- 238000003892 spreading Methods 0.000 claims description 23
- 230000007480 spreading Effects 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 21
- 239000011248 coating agent Substances 0.000 claims description 17
- 238000000576 coating method Methods 0.000 claims description 17
- 238000011161 development Methods 0.000 claims description 17
- 238000000151 deposition Methods 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 14
- 238000000059 patterning Methods 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 238000001039 wet etching Methods 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 7
- 238000001704 evaporation Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000007747 plating Methods 0.000 claims description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 229910010413 TiO 2 Inorganic materials 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 230000008569 process Effects 0.000 description 12
- 238000009616 inductively coupled plasma Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 3
- 238000000313 electron-beam-induced deposition Methods 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
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- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The application provides a flip-chip light-emitting diode chip and a preparation method thereof, wherein the chip comprises a substrate, an epitaxial layer, an electrode layer and a Bragg reflection layer which are sequentially arranged on the substrate, the chip further comprises a flat support layer arranged on the epitaxial layer, an opening is arranged on the flat support layer, the electrode layer is embedded in the opening, and one side of the flat support layer, which is away from the epitaxial layer, and one side of the electrode layer, which is away from the epitaxial layer, are positioned on the same plane. Through setting up above-mentioned flat layer of propping on the epitaxial layer to set up the opening on flat layer of propping, make the electrode layer inlay in the opening, control electrode layer and flat layer thickness the same and be in same plane, thoroughly solve the problem that the Bragg reflection layer that is located on the electrode layer breaks at electrode corner easily, after solving the problem that Bragg reflection layer breaks simultaneously, can further reduce the angle of electrode cross section corner, promote flip-chip luminous efficacy of emitting diode chip.
Description
Technical Field
The application relates to the technical field of light-emitting diode chips, in particular to a flip light-emitting diode chip and a preparation method thereof.
Background
The flip LED chip has the advantages of high light efficiency, energy saving, capability of being used under high current, long service life and the like, and is widely applied to the fields of special illumination, television backlight, plant illumination and the like because light is emitted from the substrate surface, and the conventional flip LED chip structure is generally provided with an electrode layer 03 on an epitaxial layer 02, then a Bragg reflection layer 04 is continuously arranged, and then a bonding pad layer 05 is arranged as shown in fig. 1.
As can be seen from fig. 1, the bragg reflection layer 04 completely encapsulates the electrode layer 03, and the bragg reflection layer 04 is made of a brittle material, and may be broken at the corners of the electrode layer 03, and once the bragg reflection layer 04 is broken, the bragg reflection layer 04 firstly causes a decrease in reflection effect, and secondly reduces the reliability of the light emitting diode chip, and the conventional method for solving the problem that the bragg reflection layer 04 is broken at the corners of the electrode layer 03 is to increase the angle of the corners of the electrode layer 03 as much as possible, reduce the risk of the bragg reflection layer 04 being broken, but increase the angle of the corners of the electrode layer 03 causes an increase in electrode width, thereby reducing the brightness of the light emitting diode chip.
Disclosure of Invention
Aiming at the defects of the prior art, the application aims to provide a flip-chip light-emitting diode chip and a preparation method thereof, and aims to solve the technical problem that the Bragg reflection layer is easy to crack and the luminous efficiency of the light-emitting diode chip is affected in the prior art.
In order to achieve the above object, the present application is achieved by the following technical scheme: the flip-chip light-emitting diode chip comprises a substrate, an epitaxial layer, an electrode layer and a Bragg reflection layer, wherein the epitaxial layer, the electrode layer and the Bragg reflection layer are sequentially arranged on the substrate, the chip further comprises a flat supporting layer arranged on the epitaxial layer, an opening is formed in the flat supporting layer, the electrode layer is arranged in the opening in an embedded mode, one side, deviating from the epitaxial layer, of the flat supporting layer is located on the same plane with one side, deviating from the epitaxial layer, of the electrode layer.
Compared with the prior art, the application has the beneficial effects that: through setting up above-mentioned flat layer of propping on the epitaxial layer to set up the opening on flat layer of propping, make the electrode layer inlay in the opening, control electrode layer and flat layer thickness the same and be in same plane, thoroughly solve the problem that the Bragg reflection layer that is located on the electrode layer breaks at electrode corner easily, after solving the problem that Bragg reflection layer breaks simultaneously, can further reduce the angle of electrode cross section corner, promote flip-chip luminous efficacy of emitting diode chip.
According to an aspect of the above technical solution, the angle α at the cross-sectional corner of the electrode layer satisfies: alpha is more than or equal to 85 degrees and less than or equal to 95 degrees.
According to an aspect of the foregoing technical solution, the opening includes a first opening portion disposed near one side of the epitaxial layer, and a second opening portion disposed far from one side of the epitaxial layer, and a cross-sectional width x of the first opening portion satisfies: x is more than or equal to 3um and less than or equal to 30um; the cross-sectional width y of the second opening portion satisfies: y is more than or equal to 3um and less than or equal to 30um.
According to an aspect of the above technical solution, the preparation material of the flat supporting layer is SiO 2 、SiN、TiO 2 、Al 2 O 3 One of GaN and GaN.
According to an aspect of the above technical solution, the thickness z of the flat supporting layer satisfies: z is more than or equal to 0.3um and less than or equal to 2um.
According to an aspect of the above technical solution, the flip-chip light emitting diode chip further includes a current blocking layer and a current expansion layer, the current expansion layer is disposed between the epitaxial layer and the flat supporting layer, and the current blocking layer is disposed between the current expansion layer and the epitaxial layer.
According to an aspect of the foregoing technical solution, the flip-chip light emitting diode chip further includes a pad layer, where the pad layer is disposed on the bragg reflection layer.
On the other hand, the application also provides a preparation method of the flip LED chip, which comprises the following steps:
providing a substrate;
growing an epitaxial layer on the substrate;
depositing an initial flat supporting layer on the surface of the epitaxial layer, coating a layer of photoresist on the initial flat supporting layer, and then patterning the initial flat supporting layer sequentially through exposure, development and wet etching or dry etching to form a flat supporting layer with an opening on the epitaxial layer;
evaporating conductive metal on the flat support layer to form an initial electrode layer, and stripping the conductive metal outside the opening to enable one side of the flat support layer, which is away from the epitaxial layer, and one side of the flat support layer, which is away from the epitaxial layer, to be positioned on the same plane as one side of the electrode layer, which is away from the epitaxial layer, so as to form an electrode layer with the same thickness as the flat support layer;
and vapor plating the Bragg reflection layer on the electrode layer and the flat supporting layer to prepare the flip LED chip.
According to an aspect of the above technical solution, the flip-chip light emitting diode chip further includes a current blocking layer and a current expansion layer, where the current expansion layer is disposed between the epitaxial layer and the flat supporting layer, and the current blocking layer is disposed between the current expansion layer and the epitaxial layer;
after the step of growing an epitaxial layer on the substrate, the method further comprises:
depositing an initial current blocking layer on the surface of the epitaxial layer, coating a layer of photoresist on the initial current blocking layer, and then patterning the initial current blocking layer through exposure, development and wet etching in sequence to form a current blocking layer on the epitaxial layer;
depositing an initial current expansion layer on the surfaces of the epitaxial layer and the current blocking layer, coating a photoresist layer on the initial current expansion layer, and then patterning the initial current expansion layer through exposure, development and wet etching in sequence to form the current expansion layer on the current blocking layer and the epitaxial layer.
According to an aspect of the above technical solution, the epitaxial layer includes an N-type semiconductor layer, an active light emitting layer, and a P-type semiconductor layer sequentially disposed on the substrate;
the step of depositing an initial flat supporting layer on the surface of the epitaxial layer specifically comprises the following steps of;
coating a layer of photoresist on the epitaxial layer and the current expansion layer, exposing and developing sequentially, and patterning the P-type semiconductor layer and the active light-emitting layer by ICP etching to expose part of the N-type semiconductor layer to form an N-type semiconductor step;
coating a layer of photoresist on the N-type semiconductor step, the P-type semiconductor layer and the current expansion layer, exposing and developing in sequence, and patterning the N-type semiconductor step by ICP etching to form an isolation groove;
and depositing and forming an initial flat supporting layer on the isolation groove, the N-type semiconductor step and the current expansion layer.
According to an aspect of the foregoing technical solution, the electrode layer includes a P-type electrode layer and an N-type electrode layer, and the flip-chip light emitting diode chip further includes a pad layer disposed on the bragg reflection layer
After the step of vapor plating the Bragg reflection layer on the electrode layer and the flat supporting layer, the method further comprises the following steps:
coating a layer of photoresist on the Bragg reflection layer, exposing and developing sequentially, and patterning the Bragg reflection layer by ICP etching to form Bragg reflection layer through holes, wherein the Bragg reflection layer through holes comprise P-type Bragg reflection layer through holes which are arranged corresponding to the P-type electrode layer and N-type Bragg reflection layer through holes which are arranged corresponding to the N-type electrode layer;
coating a layer of photoresist on the Bragg reflection layer, sequentially exposing and developing to form a preset pattern groove corresponding to the bonding pad layer, evaporating in the preset pattern groove to form the bonding pad layer, wherein the bonding pad layer comprises an N-type bonding pad layer and a P-type bonding pad layer, the N-type bonding pad layer is electrically connected with the N-type electrode layer through an N-type Bragg reflection layer through hole, the N-type electrode layer is electrically connected with an N-type semiconductor step, the P-type bonding pad layer is electrically connected with the P-type electrode layer through a P-type Bragg reflection layer through hole, the P-type electrode layer is electrically connected with the current expansion layer, and the current expansion layer is electrically connected with the P-type semiconductor layer.
Drawings
The foregoing and/or additional aspects and advantages of the application will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
FIG. 1 is a schematic diagram of a flip LED chip in the prior art;
fig. 2 is a schematic structural diagram of a flip-chip led chip according to a first embodiment of the present application;
fig. 3 is a schematic structural diagram of a flip-chip led chip according to a second embodiment of the present application;
fig. 4 is a schematic structural diagram of a flip-chip led chip according to a third embodiment of the present application;
FIG. 5 is a flowchart of a method for fabricating a flip LED chip according to a sixth embodiment of the present application;
description of main reference numerals:
the semiconductor device comprises a substrate 10, an N-type semiconductor layer 111, an active light emitting layer 112, a P-type semiconductor layer 113, a current blocking layer 12, a current spreading layer 13, a flat supporting layer 14, an N-type semiconductor step 114, an isolation groove 115, a P-type electrode layer 151, an N-type electrode layer 152, a Bragg reflection layer 16, a P-type Bragg reflection layer through hole 161, an N-type Bragg reflection layer through hole 162, a P-type bonding pad layer 171 and an N-type bonding pad layer 172;
the application will be further described in the following detailed description in conjunction with the above-described figures.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Various embodiments of the application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "mounted" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
Example 1
Referring to fig. 2, a flip-chip light emitting diode chip according to a first embodiment of the present application includes a substrate 10, and an epitaxial layer, an electrode layer, and a bragg reflection layer 16 sequentially disposed on the substrate 10;
the chip further comprises a flat supporting layer 14 arranged on the epitaxial layer, an opening is formed in the flat supporting layer 14, the electrode layer is embedded in the opening, one side, deviating from the epitaxial layer, of the flat supporting layer 14 is located on the same plane with one side, deviating from the epitaxial layer, of the electrode layer.
Specifically, in this embodiment, by disposing the flat supporting layer 14 on the epitaxial layer and disposing the opening on the flat supporting layer 14, the electrode layer is inlaid in the opening, the thickness of the control electrode layer is the same as that of the flat supporting layer 14 and is in the same plane, so that the problem that the bragg reflection layer 16 on the electrode layer is easy to crack at the corner of the electrode is thoroughly solved, and meanwhile, after the problem that the bragg reflection layer cracks is solved, the angle at the corner of the section of the electrode can be further reduced, and the light emitting efficiency of the flip-chip light emitting diode chip is improved.
Further, the angle at the corners of the cross section of the electrode layer may be controlled based on the widths of the cross sections of the upper and lower ends of the electrode layer, and when the widths of the cross sections of the upper and lower ends of the electrode layer are the same, the angle α at the corners of the cross section of the electrode layer is 90 °, and in the present application, the angle α at the corners of the cross section of the electrode layer satisfies: 85.ltoreq.α.ltoreq.95℃and in this embodiment 90℃is preferred.
In this embodiment, the opening includes a first opening portion disposed near the epitaxial layer side and a second opening portion disposed far from the epitaxial layer side, the electrode layer can be formed by vapor deposition of metal on the opening after the opening is disposed on the flat support layer 14, and the angle α at the cross-sectional corner of the electrode layer can be controlled according to the cross-sectional width of the first opening portion and the cross-sectional width of the second opening portion, and in the present application, the cross-sectional width x of the first opening portion satisfies: x is more than or equal to 3um and less than or equal to 30um; the cross-sectional width y of the second opening portion satisfies: in this embodiment, the first opening section width x is preferably 10um, and the second opening section width y is preferably 10um.
Specifically, in the present embodiment, the flat supporting layer 14 is made of SiO 2 、SiN、TiO 2 、Al 2 O 3 One of GaN and GaN; the preparation material of the electrode layer consists of one or more of Cr, al, ti, ni, pt, alCu, au, cu, sn, auSn, snAgCu; the Bragg reflection layer 16 is formed of SiO of 20-40 groups 2 And Ti is 3 O 5 A laminated structure. The thickness z of the flat stay layer 14 satisfies: in this embodiment, the thickness f of the electrode layer is equal to the thickness z of the flat support layer 14, that is, the thickness f of the electrode layer is equal to or less than 0.3um and less than 2 um: f is more than or equal to 0.3um and less than or equal to 2um.
Preferably, in this embodiment, the flip-chip light emitting diode chip further includes a current blocking layer 12 and a current spreading layer 13, the current spreading layer 13 is disposed between the epitaxial layer and the flat supporting layer 14, and the current blocking layer 12 is disposed between the current spreading layer 13 and the epitaxial layer.
Preferably, in this embodiment, the flip-chip light emitting diode chip further includes a pad layer, and the pad layer is disposed on the bragg reflection layer 16. The preparation material of the pad layer is composed of one or more of Cr, al, ti, ni, pt, alCu, au, cu, sn, auSn, snAgCu.
In summary, in the flip-chip light emitting diode chip of the present embodiment, the flat supporting layer 14 is disposed on the epitaxial layer, and the opening is disposed on the flat supporting layer 14, so that the electrode layer is inlaid in the opening, the thickness of the control electrode layer is the same as that of the flat supporting layer 14 and is in the same plane, the problem that the bragg reflection layer 16 on the electrode layer is easy to crack at the corner of the electrode is thoroughly solved, and meanwhile, after the problem that the bragg reflection layer 16 cracks is solved, the angle at the corner of the cross section of the electrode can be further reduced, and the light emitting efficiency of the flip-chip light emitting diode chip is improved.
Example two
The flip-chip light-emitting diode chip comprises a substrate 10, an epitaxial layer, an electrode layer, a Bragg reflection layer 16 and a bonding pad layer which are sequentially arranged on the substrate 10, wherein the chip further comprises a flat supporting layer 14 arranged on the epitaxial layer, an opening is formed in the flat supporting layer 14, the electrode layer is inlaid in the opening, one side, deviating from the epitaxial layer, of the flat supporting layer 14 is located on the same plane with one side, deviating from the epitaxial layer, of the electrode layer, and the opening comprises a first opening part which is close to one side of the epitaxial layer and a second opening part which is far away from one side of the epitaxial layer.
As shown in fig. 3, in this embodiment, the cross-sectional width x of the first opening, that is, the cross-sectional width of the electrode layer near one end of the epitaxial layer is 10um, the cross-sectional width y of the first opening, that is, the cross-sectional width of the electrode layer far from one end of the epitaxial layer is 10.5um, and the angle α at the cross-sectional corner of the electrode layer is 85 °.
Example III
The flip-chip light-emitting diode chip comprises a substrate 10, an epitaxial layer, an electrode layer, a Bragg reflection layer 16 and a bonding pad layer which are sequentially arranged on the substrate 10, wherein the chip further comprises a flat supporting layer 14 arranged on the epitaxial layer, an opening is formed in the flat supporting layer 14, the electrode layer is inlaid in the opening, one side, deviating from the epitaxial layer, of the flat supporting layer 14 is located on the same plane with one side, deviating from the epitaxial layer, of the electrode layer, and the opening comprises a first opening part which is close to one side of the epitaxial layer and a second opening part which is far away from one side of the epitaxial layer.
As shown in fig. 4, in this embodiment, the cross-sectional width x of the first opening, that is, the cross-sectional width of the electrode layer near one end of the epitaxial layer is 10.5um, the cross-sectional width y of the first opening, that is, the cross-sectional width of the electrode layer far from one end of the epitaxial layer is 10um, and the angle α at the cross-sectional corner of the electrode layer is 95 °.
Example IV
The flip-chip light-emitting diode chip comprises a substrate 10, an epitaxial layer, an electrode layer, a Bragg reflection layer 16 and a bonding pad layer which are sequentially arranged on the substrate 10, wherein the chip further comprises a flat supporting layer 14 arranged on the epitaxial layer, an opening is formed in the flat supporting layer 14, the electrode layer is inlaid in the opening, one side, deviating from the epitaxial layer, of the flat supporting layer 14 is located on the same plane with one side, deviating from the epitaxial layer, of the electrode layer, and the opening comprises a first opening part which is close to one side of the epitaxial layer and a second opening part which is far away from one side of the epitaxial layer.
In this embodiment, the cross-sectional width x of the first opening, that is, the cross-sectional width of the electrode layer near one end of the epitaxial layer is 3um, the cross-sectional width y of the first opening, that is, the cross-sectional width of the electrode layer far from one end of the epitaxial layer is 3um, and the angle α at the cross-sectional corner of the electrode layer is 90 °.
Example five
The flip-chip light-emitting diode chip comprises a substrate 10, an epitaxial layer, an electrode layer, a Bragg reflection layer 16 and a bonding pad layer which are sequentially arranged on the substrate 10, wherein the chip further comprises a flat supporting layer 14 arranged on the epitaxial layer, an opening is formed in the flat supporting layer 14, the electrode layer is inlaid in the opening, one side, deviating from the epitaxial layer, of the flat supporting layer 14 is located on the same plane with one side, deviating from the epitaxial layer, of the electrode layer, and the opening comprises a first opening part which is close to one side of the epitaxial layer and a second opening part which is far away from one side of the epitaxial layer.
In this embodiment, the cross-sectional width x of the first opening, that is, the cross-sectional width of the electrode layer near one end of the epitaxial layer is 30um, the cross-sectional width y of the first opening, that is, the cross-sectional width of the electrode layer far from one end of the epitaxial layer is 30um, and the angle α at the cross-sectional corner of the electrode layer is 90 °.
Comparative example one
Referring to fig. 1, a flip-chip light emitting diode chip includes a substrate 01, and an epitaxial layer 02, an electrode layer 03, a bragg reflection layer 04 and a bonding pad layer 05 sequentially disposed on the substrate 01, in this comparative example, a cross-sectional width x of one end of the electrode layer 03 near the epitaxial layer 02 is 14um, a cross-sectional width y of one end of the electrode layer 03 far from the epitaxial layer 02 is 10um, and an angle α at a cross-sectional corner of the electrode layer is 135 °.
Brightness comparison tests were performed on examples one, two, three, four, five and comparative example one, with the following results:
。
referring to fig. 5, the sixth embodiment of the present application further provides a method for manufacturing a flip-chip light emitting diode chip, which includes the following steps:
in step S100, a substrate is provided.
And step S200, growing an epitaxial layer on the substrate. Specifically, in this step, the step of growing an epitaxial layer on the substrate 10 specifically includes:
in step S201, an epitaxial layer is grown on the substrate 10 by an MOCVD (metal organic chemical vapor deposition) process, wherein the epitaxial layer includes an N-type semiconductor layer 111, an active light emitting layer 112, and a P-type semiconductor layer 113 in this order from bottom to top.
Preferably, in this embodiment, after the step S200, the method further includes:
step S210, depositing an initial current blocking layer on the surface of the epitaxial layer, coating a layer of photoresist on the initial current blocking layer, and sequentially exposing,The initial current blocking layer is patterned by development and wet etching to form the current blocking layer 12 on the epitaxial layer. Specifically, a layer of SiO is deposited on the surface of the P-type semiconductor layer 113 by PECVD process 2 Forming an initial current blocking layer, coating a layer of photoresist on the initial current blocking layer, sequentially exposing, developing and wet etching to form a photoresist preset pattern on the surface of the initial current blocking layer, removing part of the initial current blocking layer by using a BOE etching solution, retaining part of the initial current blocking layer below the preset pattern, and removing the photoresist to form the current blocking layer 12.
Step S220, depositing an initial current expansion layer on the surface of the epitaxial layer and the current blocking layer 12, coating a photoresist on the initial current expansion layer, and patterning the initial current expansion layer sequentially through exposure, development and wet etching to form the current expansion layer 13 on the current blocking layer 12 and the epitaxial layer. Specifically, an initial current spreading layer is formed by depositing Indium Tin Oxide (ITO) on the surfaces of the P-type semiconductor layer 113 and the current blocking layer 12 by using a measure and control sputtering process, a photoresist layer is coated on the surface of the initial current spreading layer, a photoresist preset pattern is formed on the surface of the initial current spreading layer by once exposure, development and wet etching, a part of the initial current spreading layer is removed by using an ITO etching solution, a part of the initial current spreading layer below the preset pattern is reserved, and then the photoresist layer is removed to form the current spreading layer 13.
Step S300, depositing an initial flat supporting layer on the surface of the epitaxial layer, coating a layer of photoresist on the initial flat supporting layer, and then patterning the initial flat supporting layer sequentially through exposure, development and wet etching or dry etching to form a flat supporting layer 14 with an opening on the epitaxial layer. A photoresist layer is coated on the initial flat supporting layer, then a photoresist preset pattern corresponding to the opening is formed through exposure and development in sequence, a part of the current expansion layer 13 and the initial flat supporting layer on the N-type semiconductor step 114 are exposed, and then the exposed initial flat supporting layer is removed by using a BOE corrosive liquid or an inductively coupled plasma etching process, so that the opening is formed on the flat supporting layer 14.
In one embodiment, in the step S300, the step of depositing an initial spacer layer on the surface of the epitaxial layer specifically includes;
in step S301, a photoresist layer is coated on the epitaxial layer and the current spreading layer 13, and then the P-type semiconductor layer 113 and the active light emitting layer 112 are patterned by ICP etching after exposure and development in order to expose a portion of the N-type semiconductor layer 111 and form an N-type semiconductor step 114. Specifically, a photoresist is coated on the surfaces of the P-type semiconductor layer 113 and the current spreading layer 13, then a part of the photoresist is removed by exposure and development in sequence, a part of the P-type semiconductor layer 113 is exposed, then the exposed P-type semiconductor layer 113 and the active light emitting layer 112 are removed by using an inductively coupled plasma etching process, a part of the N-type semiconductor layer 111 below the exposed P-type semiconductor layer 113 and the active light emitting layer 112 is exposed, and then the photoresist is removed, wherein the exposed part of the N-type semiconductor layer 111, namely the N-type semiconductor step 114 is removed.
In step S302, a photoresist layer is coated on the N-type semiconductor step 114, the P-type semiconductor layer 113 and the current spreading layer 13, and then the N-type semiconductor step 114 is patterned by ICP etching to form the isolation trench 115. Specifically, the isolation trench 115 is formed by coating a photoresist layer on the surfaces of the N-type semiconductor step 114, the P-type semiconductor layer 113 and the current spreading layer 13, sequentially removing a portion of the photoresist layer by exposure and development, exposing a portion of the N-type semiconductor step 114, and removing the exposed N-type semiconductor step 114 by an inductively coupled plasma etching process.
In step S303, an initial flat supporting layer is deposited on the isolation trench 115, the N-type semiconductor step 114, and the current spreading layer 13. Si0 is deposited on the isolation trench 115, the N-type semiconductor step 114 and the current spreading layer 13 by PECVD process 2 An initial flat stay layer is formed.
Step S400, evaporating conductive metal on the flat supporting layer 14 to form an initial electrode layer, and stripping the conductive metal outside the opening, so that one side of the flat supporting layer 14 facing away from the epitaxial layer and one side of the electrode layer facing away from the epitaxial layer are located on the same plane to form an electrode layer with the same thickness as the flat supporting layer 14. Specifically, cr/Al/Ti/Pt/Au/Pt/Ti is sequentially deposited on the flat support layer 14 by an electron beam deposition technique to form an initial electrode layer, then metal outside the opening of the flat support layer 14 is removed by a lift-off process, and then photoresist is removed to form an electrode layer including a P-type electrode layer 151 and an N-type electrode layer 152, the electrode layer located above the current spreading layer 13 is the P-type electrode layer 151, and the electrode layer located above the N-type semiconductor step 114 is the N-type electrode layer 152.
Step S500, vapor plating the bragg reflection layer 16 on the electrode layer and the flat supporting layer 14 to obtain the flip-chip light emitting diode chip. Specifically, 28 groups of SiO are sequentially deposited on the electrode layer and the flat support layer 14 by using an electron beam deposition process 2 And Ti is 3 O 5 A stack of layers is formed to form the bragg reflector layer 16.
In one embodiment, in the step S500, after the step of vapor depositing the bragg reflection layer 16 on the electrode layer and the flat support layer 14, the method further includes:
step S510, preparing a pad layer on the bragg reflection layer 16.
In one embodiment, the step S510 specifically includes:
in step S511, a layer of photoresist is coated on the bragg reflection layer 16, and then the bragg reflection layer 16 is patterned by ICP etching through exposure and development in sequence to form a bragg reflection layer through hole, wherein the bragg reflection layer through hole includes a P-type bragg reflection layer through hole 161 corresponding to the P-type electrode layer 151 and an N-type bragg reflection layer through hole 162 corresponding to the N-type electrode layer 152. Specifically, a layer of photoresist is coated on the bragg reflection layer 16, then a preset photoresist pattern corresponding to the openings of the bragg reflection layer 16 is formed through exposure and development in sequence, the bragg reflection layer 16 on the P-type electrode layer 151 and the N-type electrode layer 152 is exposed, then the exposed bragg reflection layer 16 is removed by using an inductively coupled plasma etching process, and then the photoresist is removed, so that the bragg reflection layer through hole is formed.
In step S512, a photoresist layer is coated on the bragg reflection layer 16, a preset pattern groove corresponding to the pad layer is formed by exposing and developing in sequence, the pad layer is formed in the preset pattern groove by vapor deposition, the pad layer includes an N-type pad layer 172 and a P-type pad layer 171, the N-type pad layer 172 is electrically connected with the N-type electrode layer 152 through the N-type bragg reflection layer through hole 162, the N-type electrode layer 152 is electrically connected with the N-type semiconductor step 114, the P-type pad layer 171 is electrically connected with the P-type electrode layer 151 through the P-type bragg reflection layer through hole 161, the P-type electrode layer 151 is electrically connected with the current expansion layer 13, and the current expansion layer 13 is electrically connected with the P-type semiconductor layer 113. Specifically, photoresist is coated on the surface of the Bragg reflection layer 16, then a photoresist preset pattern corresponding to the pad layer is formed through exposure and development in sequence, then Al/Ti/Pt/Ti/Ni/Au/Sn metal is evaporated in sequence through an electron beam evaporation process, then excessive metal is removed through a stripping process, and then the photoresist is removed, so that the pad layer is formed.
In summary, in the method for manufacturing the flip-chip light emitting diode chip of the present embodiment, the flat supporting layer 14 is disposed on the epitaxial layer, and the opening is disposed on the flat supporting layer 14, so that the electrode layer is inlaid in the opening, the thickness of the control electrode layer is the same as that of the flat supporting layer 14 and is in the same plane, the problem that the bragg reflection layer 16 on the electrode layer is easy to crack at the corner of the electrode is thoroughly solved, and meanwhile, after the problem that the bragg reflection layer 16 cracks is solved, the angle at the corner of the cross section of the electrode can be further reduced, and the light emitting efficiency of the flip-chip light emitting diode chip is improved.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing examples illustrate only a few embodiments of the application and are described in detail herein without thereby limiting the scope of the application. It should be noted that various modifications and improvements can be made by those skilled in the art without departing from the spirit of the application, which falls within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (10)
1. The flip-chip light-emitting diode chip is characterized by comprising a substrate, an epitaxial layer, an electrode layer and a Bragg reflection layer, wherein the epitaxial layer, the electrode layer and the Bragg reflection layer are sequentially arranged on the substrate, the chip further comprises a flat supporting layer arranged on the epitaxial layer, an opening is formed in the flat supporting layer, the electrode layer is inlaid in the opening, one side, deviating from the epitaxial layer, of the flat supporting layer is located on the same plane with one side, deviating from the epitaxial layer, of the electrode layer.
2. The flip-chip light emitting diode chip of claim 1, wherein the angle α at the cross-sectional corners of the electrode layers satisfies: alpha is more than or equal to 85 degrees and less than or equal to 95 degrees.
3. The flip-chip light emitting diode chip of claim 1, wherein the opening comprises a first opening portion disposed near the epitaxial layer side and a second opening portion disposed far from the epitaxial layer side, and a cross-sectional width x of the first opening portion satisfies: x is more than or equal to 3um and less than or equal to 30um; the cross-sectional width y of the second opening portion satisfies: y is more than or equal to 3um and less than or equal to 30um.
4. The pouring according to claim 1The LED chip is characterized in that the preparation material of the flat supporting layer is SiO 2 、SiN、TiO 2 、Al 2 O 3 One of GaN and GaN.
5. The flip-chip light emitting diode chip of claim 1, wherein the thickness z of the flat support layer satisfies: z is more than or equal to 0.3um and less than or equal to 2um.
6. The flip-chip light emitting diode chip of any of claims 1-5, further comprising a current blocking layer and a current spreading layer, the current spreading layer being disposed between the epitaxial layer and the spreader layer, the current blocking layer being disposed between the current spreading layer and the epitaxial layer.
7. The flip-chip light emitting diode chip of claim 6, further comprising a pad layer disposed on the bragg reflector layer.
8. The preparation method of the flip LED chip is characterized by comprising the following steps of:
providing a substrate;
growing an epitaxial layer on the substrate;
depositing an initial flat supporting layer on the surface of the epitaxial layer, coating a layer of photoresist on the initial flat supporting layer, and then patterning the initial flat supporting layer sequentially through exposure, development and wet etching or dry etching to form a flat supporting layer with an opening on the epitaxial layer;
evaporating conductive metal on the flat support layer to form an initial electrode layer, and stripping the conductive metal outside the opening to enable one side of the flat support layer, which is away from the epitaxial layer, and one side of the flat support layer, which is away from the epitaxial layer, to be positioned on the same plane as one side of the electrode layer, which is away from the epitaxial layer, so as to form an electrode layer with the same thickness as the flat support layer;
and vapor plating the Bragg reflection layer on the electrode layer and the flat supporting layer to prepare the flip LED chip.
9. The method of manufacturing a flip-chip light emitting diode chip as claimed in claim 8, further comprising a current blocking layer and a current spreading layer, wherein the current spreading layer is disposed between the epitaxial layer and the spreader layer, and the current blocking layer is disposed between the current spreading layer and the epitaxial layer;
after the step of growing an epitaxial layer on the substrate, the method further comprises:
depositing an initial current blocking layer on the surface of the epitaxial layer, coating a layer of photoresist on the initial current blocking layer, and then patterning the initial current blocking layer through exposure, development and wet etching in sequence to form the current blocking layer on the epitaxial layer;
depositing an initial current expansion layer on the surfaces of the epitaxial layer and the current blocking layer, coating a photoresist layer on the initial current expansion layer, and then patterning the initial current expansion layer through exposure, development and wet etching in sequence to form the current expansion layer on the current blocking layer and the epitaxial layer.
10. The method of manufacturing a flip-chip light emitting diode chip as claimed in claim 9, wherein the epitaxial layer comprises an N-type semiconductor layer, an active light emitting layer and a P-type semiconductor layer sequentially disposed on the substrate;
the step of depositing an initial flat supporting layer on the surface of the epitaxial layer specifically comprises the following steps of;
coating a layer of photoresist on the epitaxial layer and the current expansion layer, exposing and developing sequentially, and patterning the P-type semiconductor layer and the active light-emitting layer by ICP etching to expose part of the N-type semiconductor layer to form an N-type semiconductor step;
coating a layer of photoresist on the N-type semiconductor step, the P-type semiconductor layer and the current expansion layer, exposing and developing in sequence, and patterning the N-type semiconductor step by ICP etching to form an isolation groove;
and depositing and forming an initial flat supporting layer on the isolation groove, the N-type semiconductor step and the current expansion layer.
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