CN114709304A - Flip light-emitting diode chip and preparation method thereof - Google Patents

Flip light-emitting diode chip and preparation method thereof Download PDF

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Publication number
CN114709304A
CN114709304A CN202210212704.XA CN202210212704A CN114709304A CN 114709304 A CN114709304 A CN 114709304A CN 202210212704 A CN202210212704 A CN 202210212704A CN 114709304 A CN114709304 A CN 114709304A
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metal layer
layer
type
reflective
chip
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李文涛
徐吉双
简弘安
张星星
胡加辉
金从龙
顾伟
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Jiangxi Zhao Chi Semiconductor Co Ltd
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Jiangxi Zhao Chi Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/405—Reflective materials

Abstract

The invention discloses a flip-chip light emitting diode chip and a preparation method thereof, wherein the chip comprises: the device comprises a substrate, an epitaxial layer, a current barrier layer, a current expansion layer, a current transmission metal layer, a Bragg reflection layer, a reflection metal layer, an insulating layer and a bonding metal layer; the reflecting metal layer comprises a first reflecting metal layer and a second reflecting metal layer, the insulating layer comprises a first insulating layer and a second insulating layer, the first reflecting metal layer and the second reflecting metal layer are mutually staggered in the stacking height of the chip, one of the first insulating layer and the second insulating layer is arranged between the first reflecting metal layer and the second reflecting metal layer, and the other one of the first insulating layer and the second insulating layer is arranged between the first reflecting metal layer or the second reflecting metal layer and the bonding metal layer. The flip chip aims to solve the problems that an N-type reflecting metal layer and a P-type reflecting metal layer of the existing flip chip are positioned on the same plane, the N-type reflecting metal layer and the P-type reflecting metal layer are easy to be short-circuited, and the chip is rapidly failed after being aged for a long time.

Description

Flip light-emitting diode chip and preparation method thereof
Technical Field
The invention relates to the technical field of chips, in particular to a flip light-emitting diode chip and a preparation method thereof.
Background
The light emitting diode has the advantages of energy conservation, high brightness, high durability, long service life, lightness and the like, and is widely applied to the fields of common illumination, special illumination, landscape illumination, phytone illumination, outdoor display, indoor display, liquid crystal display, vehicle-mounted illumination, vehicle-mounted display and the like. At present, flip-chip LED can be stably used under high-power, has higher outer quantum efficiency, uses gradually ripe, and flip-chip's speculum also becomes the double-deck reflection configuration of Bragg reflector layer plus metal by original Bragg reflector layer to promote the luminance of chip.
However, the N-type reflective metal layer and the P-type reflective metal layer of the conventional flip chip are located on the same plane, and if the brightness of the chip is to be improved, the area of the reflective metal layer needs to be increased, or the distance between the N-type reflective metal layer and the P-type reflective metal layer needs to be shortened, so that the risks of short circuit between the N-type reflective metal layer and the P-type reflective metal layer and failure of the chip after long-time aging are increased, and the brightness and the reliability of the chip are difficult to achieve.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a flip light-emitting diode chip and a preparation method thereof, and aims to solve the problems that an N-type reflecting metal layer and a P-type reflecting metal layer of the conventional flip chip are positioned on the same plane, the N-type reflecting metal layer and the P-type reflecting metal layer are easy to be short-circuited, and the chip is rapidly failed after being aged for a long time.
A first aspect of the present invention provides a flip chip light emitting diode chip, the chip including:
the epitaxial layer comprises a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are sequentially stacked, wherein an MESA step is arranged on the epitaxial layer to expose the N-type semiconductor layer, and an isolation groove is arranged on the MESA step to expose the substrate;
the chip also comprises a current blocking layer, a current expanding layer, a current transmission metal layer, a Bragg reflecting layer, a reflecting metal layer, an insulating layer and a bonding metal layer;
the reflective metal layer comprises a first reflective metal layer and a second reflective metal layer, the insulating layer comprises a first insulating layer and a second insulating layer, the first reflective metal layer and the second reflective metal layer are mutually staggered in the stacking height of the chip, one of the first insulating layer and the second insulating layer is arranged between the first reflective metal layer and the second reflective metal layer and corresponds to the first reflective metal layer, and the other one of the first insulating layer and the second insulating layer is arranged between the first reflective metal layer or the second reflective metal layer and the bonding metal layer.
According to one aspect of the above technical solution, the current transmission metal layer includes an N-type current transmission metal layer and a P-type current transmission metal layer;
the first reflecting metal layer is an N-type reflecting metal layer, the second reflecting metal layer is a P-type reflecting metal layer, the first reflecting metal layer is in contact with the N-type current transmission metal layer, and the second reflecting metal layer is in contact with the P-type current transmission metal layer;
or, the first reflective metal layer is a P-type reflective metal layer, the second reflective metal layer is an N-type reflective metal layer, the first reflective metal layer is in contact with the P-type current transmission metal layer, and the second reflective metal layer is in contact with the N-type current transmission metal layer.
According to an aspect of the foregoing technical solution, when the first reflective metal layer is an N-type reflective metal layer and the second reflective metal layer is a P-type reflective metal layer, the first reflective metal layer contacts the N-type current transmission metal layer through an N-type reflective through hole preset on the bragg reflective layer to form an electrical connection, and the second reflective metal layer contacts the P-type current transmission metal layer through the first insulating layer and a P-type reflective through hole preset on the bragg reflective layer to form an electrical connection.
According to an aspect of the foregoing technical solution, the bonding metal layer includes an N-type bonding metal layer and a P-type bonding metal layer;
the N-type bonding metal layer is in contact with the first reflecting metal layer through the second insulating layer and an insulating layer through hole preset in the first insulating layer to form electrical connection, and the P-type bonding metal layer independently penetrates through the insulating layer through hole preset in the second insulating layer to be in contact with the second reflecting metal layer to form electrical connection.
According to an aspect of the foregoing technical solution, when the first reflective metal layer is a P-type reflective metal layer and the second reflective metal layer is an N-type reflective metal layer, the first reflective metal layer is in contact with the P-type current-transmitting metal layer through the first insulating layer and a P-type reflective through hole preset in the bragg reflective layer to form an electrical connection, and the second reflective metal layer is in contact with the N-type current-transmitting metal layer through the N-type reflective through hole preset in the bragg reflective layer to form an electrical connection.
According to an aspect of the foregoing technical solution, the bonding metal layer includes an N-type bonding metal layer and a P-type bonding metal layer;
the N-type bonding metal layer independently penetrates through a preset insulating layer through hole in the second insulating layer to be in contact with the first reflecting metal layer to form electrical connection, and the P-type bonding metal layer is in contact with the second reflecting metal layer through the second insulating layer and the preset insulating layer through hole in the first insulating layer to form electrical connection.
According to one aspect of the above technical solution, the P-type current transmission metal layers are densely arranged around the periphery of the N-type current transmission metal layer, so as to reduce a lateral current transmission distance between the P-type current transmission metal layer and the N-type current transmission metal layer.
According to one aspect of the above technical solution, the depth of the MESA step is 15% -30% of the thickness of the epitaxial layer.
According to one aspect of the above technical scheme, the angle of the isolation groove is 30-80 degrees.
The second aspect of the present invention further provides a method for manufacturing a flip-chip light emitting diode chip, which is used for manufacturing the flip-chip light emitting diode chip in the above technical solution, and the method for manufacturing includes:
providing a substrate;
manufacturing an epitaxial layer on the substrate, wherein the epitaxial layer comprises a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are sequentially stacked;
manufacturing an MESA step on the epitaxial layer to expose the N-type semiconductor layer;
manufacturing a current blocking layer on the MESA step and the P-type semiconductor layer;
manufacturing a current expansion layer on the P-type semiconductor layer and the current barrier layer;
etching the MESA step, and removing the N-type semiconductor layer and the buffer layer at the MESA step to manufacture an isolation groove;
Respectively manufacturing an N-type current transmission metal layer and a P-type current transmission metal layer on the MESA step and the expansion layer;
manufacturing Bragg reflection layers on the surfaces of the MESA step, the P-type semiconductor layer, the current expansion layer and the current transmission metal layer;
manufacturing a first reflection metal layer on the Bragg reflection metal layer, manufacturing a first insulating layer on the first reflection metal layer, manufacturing a second reflection metal layer on the first insulating layer, manufacturing a second insulating layer on the second reflection metal layer, and manufacturing a bonding metal layer on the second insulating layer;
or, a second reflective metal layer is fabricated on the bragg reflective metal layer, a second insulating layer is fabricated on the second reflective metal layer, a first reflective metal layer is fabricated on the second insulating layer, a first reflective layer is fabricated on the first reflective metal layer, and a bonding metal layer is fabricated on the first reflective layer.
Compared with the prior art, the flip-chip light-emitting diode chip and the preparation method have the advantages that:
through staggering first reflection metal level and second reflection metal level each other on the range upon range of height of chip, layering sets up promptly in space, and increases the insulating layer between first reflection metal level and second reflection metal level to when can thoroughly solve among the prior art N type reflection metal level and P type reflection metal level and be in the coplanar, because the distance between N type reflection metal level and the P type reflection metal level is too short, take place the problem that short circuit and chip are ageing for a long time fast inefficacy easily.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic structural diagram of a flip-chip light emitting diode chip according to a first embodiment of the invention;
fig. 2 is a schematic top view of a flip-chip led chip according to a first embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a flip-chip LED chip according to a second embodiment of the present invention;
fig. 4 is a schematic top view of a flip-chip led chip according to a second embodiment of the present invention;
fig. 5 is a schematic top view of a third embodiment of a flip-chip led chip according to the present invention;
FIG. 6 is a schematic flow chart illustrating a method for fabricating a flip-chip LED chip according to a fourth embodiment of the present invention;
fig. 7 is a schematic flow chart illustrating a method for manufacturing another flip-chip light emitting diode chip according to a fourth embodiment of the invention;
description of reference numerals:
11-substrate, 12-epitaxial layer, 121-buffer layer, 122-N type semiconductor layer, 123-active layer, 124-P type semiconductor layer, 13-MESA step, 14-current blocking layer, 15-current spreading layer, 16-isolation trench, 171-P type current transmission metal layer, 172-N type current transmission metal layer, 18-Bragg reflection layer, 181-N type reflection via hole preset on Bragg reflection layer, 19-first reflection metal layer, 20-first insulation layer, 201-first insulation layer and P type reflection via hole preset on Bragg reflection layer, 21-second reflection metal layer, 22-second insulation layer, 221-insulation layer via hole preset on second insulation layer, 222-second insulation layer and P type reflection via hole preset on first insulation layer, 231-P type bonding metal layer, 232-N type bonding metal layer.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings, in order to make the objects, features and advantages of the invention more comprehensible. Several embodiments of the invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. As used herein, the terms "vertical," "horizontal," "left," "right," "up," "down," and the like are used for descriptive purposes only and not for purposes of indicating or implying that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the invention.
In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "fixed," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Example one
Referring to fig. 1 and fig. 2, a flip-chip light emitting diode chip according to a first embodiment of the present invention includes: a substrate 11 and an epitaxial layer 12 disposed on the substrate 11; the chip further includes a current blocking layer 14, a current spreading layer 15, a current transmitting metal layer, a bragg reflection layer 18, a reflection metal layer, an insulating layer, and a bonding metal layer.
As will be readily understood by those skilled in the art, the epitaxial layer 12 includes a buffer layer 121, an N-type semiconductor layer 122, an active layer 123, and a P-type semiconductor layer 124, which are sequentially stacked; wherein, an MESA step 13 is formed on the epitaxial layer 12 to expose the N-type semiconductor layer 122, and an isolation trench 16 is formed on the MESA step 13 to expose the substrate 11.
The current transmission metal layer includes an N-type current transmission metal layer 172 and a P-type current transmission metal layer 171, and the bonding metal layer includes an N-type bonding metal layer 232 and a P-type bonding metal layer 231.
Further, the reflective metal layer includes a first reflective metal layer 19 and a second reflective metal layer 21, the insulating layer includes a first insulating layer 20 and a second insulating layer 22, the first reflective metal layer 19 and the second reflective metal layer 21 are staggered from each other in the stacking height of the chip, the first insulating layer 20 is disposed between the first reflective metal layer 19 and the second reflective metal layer 21, and correspondingly, the second insulating layer 22 is disposed between the second reflective metal layer 21 and the bonding metal layer.
In this embodiment, the first reflective metal layer 19 is an N-type reflective metal layer, the second reflective metal layer 21 is a P-type reflective metal layer, the first reflective metal layer 19 is lower than the second reflective metal layer 21 in the stacking height of the chip, the first reflective metal layer 19 is in contact with the N-type current transmission metal layer 172, and the second reflective metal layer 21 is in contact with the P-type current transmission metal layer 171.
Specifically, in order to make the first reflective metal layer 19 contact the N-type current transmitting metal layer 172 to form an electrical connection, the first reflective metal layer 19 contacts the N-type current transmitting metal layer 172 through an N-type reflective via 181 preset on the bragg reflector 18 to form an electrical connection. The second reflective metal layer 21 higher than the first reflective metal layer 19 in the stacking height of the chip needs to contact the P-type current transmission metal layer 171 through the P-type reflective via 201 preset on the first insulating layer 20 and the bragg reflective layer 18 to form an electrical connection; that is, the second reflective metal layer 21 needs to pass through not only the bragg reflector layer 18 but also the first insulating layer 20 formed on the first reflective metal layer 19 to be in contact with the P-type current-carrying metal layer 171.
Further, the N-type bonding metal layer 232 is in contact with the first reflective metal layer 19 through the insulating layer via 222 (a via hole formed by two insulating layers communicating with each other) preset on the second insulating layer 22 and the first insulating layer 20 to form an electrical connection; that is, the N-type bonding metal layer 232 needs to penetrate not only the second insulating layer 22 with a higher height, but also the first insulating layer 20 disposed below the second insulating layer 22 to contact the first reflective metal layer 19 for electrical connection. The P-type bonding metal layer 231 individually passes through the insulating layer via 221 (individually disposed via on the second insulating layer 22) pre-disposed on the second insulating layer 22 to contact with the second reflective metal layer 21 to form an electrical connection; that is, the P-type bonding metal layer 231 can be contacted with the second reflective metal layer 21 to form an electrical connection only through the second insulating layer 22.
To sum up, through staggering first reflection metal layer 19 and second reflection metal layer 21 each other on the range upon range of height of chip, layering sets up in space promptly, and increases first insulating layer 20 between first reflection metal layer 19 and second reflection metal layer 21 to can thoroughly solve flip chip's among the prior art N type reflection metal layer and P type reflection metal layer when being in the coplanar, because the distance between N type reflection metal layer and the P type reflection metal layer is too short, take place the short circuit easily and the chip is ageing for a long time fast problem that loses efficacy.
In the present embodiment, the depth of the MESA step 13 is 15 to 30% of the thickness of the epitaxial layer 12, and the angle of the isolation trench 16 is 30 to 80 °.
In the present embodiment, the material for preparing the current-carrying metal layer includes a laminate of one or more of Cr, Al, Ti, Ni, Pt, Au, Ag, and combinations thereof; the total thickness of the Bragg reflection layer 18 is
Figure BDA0003532002910000071
Figure BDA0003532002910000072
(ii) a The material used for preparing the first reflective metal layer 19 and the second reflective metal layer 21 is a lamination of one or more of Cr, Al, Ti, Ni, Pt, Au and Ag; the material used for preparing the first insulating layer 20 and the second insulating layer 22 is SiO2 or SiN with a thickness of
Figure BDA0003532002910000073
(ii) a The material for preparing the bonding metal layer is a lamination layer of one or more of Cr, Al, Ti, Ni, Pt, Au and Ag.
Example two
Referring to fig. 3 and 4, a second embodiment of the invention provides a flip-chip light emitting diode chip, which includes: a substrate 11 and an epitaxial layer 12 disposed on the substrate 11; the chip further includes a current blocking layer 14, a current spreading layer 15, a current transmitting metal layer, a bragg reflection layer 18, a reflection metal layer, an insulating layer, and a bonding metal layer.
As will be readily understood by those skilled in the art, the epitaxial layer 12 includes a buffer layer 121, an N-type semiconductor layer 122, an active layer 123, and a P-type semiconductor layer 124, which are sequentially stacked; wherein, an MESA step 13 is formed on the epitaxial layer 12 to expose the N-type semiconductor layer 122, and an isolation trench 16 is formed on the MESA step 13 to expose the substrate 11.
The current transmission metal layer includes an N-type current transmission metal layer 172 and a P-type current transmission metal layer 171, and the bonding metal layer includes an N-type bonding metal layer 232 and a P-type bonding metal layer 231.
Further, the reflective metal layer includes a first reflective metal layer 19 and a second reflective metal layer 21, the insulating layer includes a first insulating layer 20 and a second insulating layer 22, the first reflective metal layer 19 and the second reflective metal layer 21 are staggered from each other in the stacking height of the chip, the second insulating layer 22 is disposed between the first reflective metal layer 19 and the second reflective metal layer 21, and correspondingly, the first insulating layer 20 is disposed between the first reflective metal layer 19 and the bonding metal layer.
In the present embodiment, the first reflective metal layer 19 is a P-type reflective metal layer, the second reflective metal layer 21 is an N-type reflective metal layer, the first reflective metal layer 19 is higher than the second reflective metal layer 21 in the stacking height of the chip, the first reflective metal layer 19 is in contact with the P-type current-carrying metal layer 172, and the second reflective metal layer 21 is in contact with the N-type current-carrying metal layer 171.
Specifically, in order to make the second reflective metal layer 21 contact the N-type current transmitting metal layer 171 to form an electrical connection, the second reflective metal layer 21 contacts the N-type current transmitting metal layer 171 through an N-type reflective via 181 preset on the bragg reflector layer 18 to form an electrical connection. The first reflective metal layer 19 higher than the second reflective metal layer 21 in the stacking height of the chip needs to be in contact with the P-type current transmission metal layer 172 through the N-type reflective via 201 preset on the first insulating layer 20 and the bragg reflective layer 18 to form an electrical connection; that is, the first reflective metal layer 19 needs to pass through not only the bragg reflector layer 18 but also the first insulating layer 20 disposed on the second reflective metal layer 21 to contact the P-type current-carrying metal layer 172.
Further, the P-type bonding metal layer 231 contacts the second reflective metal layer 21 through the insulating layer via 222 (a via hole formed by two insulating layers communicating with each other) preset on the second insulating layer 22 and the first insulating layer 20 to form an electrical connection; that is, the P-type bonding metal layer 231 needs to penetrate through the second insulating layer 22 with a higher height, and also needs to penetrate through the first insulating layer 20 disposed below the second insulating layer 22 to be in contact with the second reflective metal layer 21 to form an electrical connection. The N-type bonding metal layer 232 individually passes through the insulating layer via 221 (individually disposed via on the second insulating layer 22) preset on the second insulating layer 22 to contact with the first reflective metal layer 19 to form an electrical connection; that is, the N-type bonding metal layer 232 only needs to penetrate the second insulating layer 22 to contact the first reflective metal layer 19 to form an electrical connection.
To sum up, the first reflective metal layer 19 and the second reflective metal layer 21 are staggered with each other on the stacking height of the chip, that is, are layered in space, and the second insulating layer 22 is added between the first reflective metal layer 19 and the second reflective metal layer 21, so that the problems that in the prior art, when the N-type reflective metal layer and the P-type reflective metal layer of the flip chip are in the same plane, short circuit easily occurs and the chip rapidly fails after long-time aging due to too short distance between the N-type reflective metal layer and the P-type reflective metal layer can be thoroughly solved.
In the present embodiment, the depth of the MESA step 13 is 15 to 30% of the thickness of the epitaxial layer 12, and the angle of the isolation trench 16 is 30 to 80 °.
In the present embodiment, the material for preparing the current-carrying metal layer includes a laminate of one or more of Cr, Al, Ti, Ni, Pt, Au, Ag, and combinations thereof; the total thickness of the Bragg reflection layer 18 is
Figure BDA0003532002910000091
Figure BDA0003532002910000092
The material used for preparing the first reflective metal layer 19 and the second reflective metal layer 21 is a lamination of one or more of Cr, Al, Ti, Ni, Pt, Au and Ag; the material used for preparing the first insulating layer 20 and the second insulating layer 22 is SiO2 or SiN with a thickness of
Figure BDA0003532002910000093
The material used for preparing the bonding metal layer is a lamination layer of one or more of Cr, Al, Ti, Ni, Pt, Au and Ag.
EXAMPLE III
Referring to fig. 5, a third embodiment of the invention provides a flip-chip light emitting diode chip, compared to the second embodiment, in this embodiment, P-type current transmission metal layers 171 are densely arranged around the periphery of an N-type current transmission metal layer 172.
With reference to the second embodiment, the first reflective metal layer and the second reflective metal layer are staggered from each other in the stacking height of the chip, and the corresponding P-type current transmission metal layer and the corresponding N-type current transmission metal layer are also staggered from each other in the stacking height of the chip, so that the transverse current transmission distance is effectively reduced, and the working voltage of the chip is reduced.
Example four
Referring to fig. 6, a fourth embodiment of the present invention provides a method for manufacturing a flip-chip light emitting diode chip, for manufacturing the flip-chip light emitting diode chip in the first embodiment, the method including steps S10-S90:
step S10, providing a substrate;
step S20, manufacturing an epitaxial layer on the substrate, wherein the epitaxial layer comprises a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are sequentially stacked;
Step S30, forming a MESA step on the epitaxial layer to expose the N-type semiconductor layer;
step S40, manufacturing a current barrier layer on the MESA step and the P type semiconductor layer;
step S50, manufacturing a current expansion layer on the P-type semiconductor layer and the current barrier layer;
step S60, etching the MESA step, and removing the N-type semiconductor layer and the buffer layer at the MESA step to manufacture an isolation groove;
step S70, manufacturing an N-type current transmission metal layer and a P-type current transmission metal layer on the MESA step and the expanded layer respectively;
step S80, manufacturing Bragg reflection layers on the surfaces of the MESA step, the P-type semiconductor layer, the current expansion layer and the current transmission metal layer;
step S90 is to form a first reflective metal layer on the bragg reflective metal layer, a first insulating layer on the first reflective metal layer, a second reflective metal layer on the first insulating layer, a second insulating layer on the second reflective metal layer, and a bonding metal layer on the second insulating layer.
Specifically, the preparation method comprises the following steps:
firstly, providing a substrate;
then growing an epitaxial layer on the substrate; the epitaxial layer is sequentially provided with a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer 124 from bottom to top;
Then preparing an MESA step; forming a pattern on the surface of the P-type semiconductor layer through a photoetching process, removing part of the P-type semiconductor layer 124, the active layer and the N-type semiconductor layer through an ICP (inductively coupled plasma) etching process to expose an MESA step, and removing photoresist; the depth of the MESA step is 15-30% of the epitaxial layer;
then preparing a current barrier layer; depositing SiO on the P-type semiconductor layer 124 and the MESA step surface by PECVD (physical chemical deposition)2Then patterned by photolithography, and then patterned with SiO2Removing partial SiO by corrosive liquid2Then removing the photoresist; the current barrier layer is made of SiO2 or SiN with a thickness of
Figure BDA0003532002910000101
Figure BDA0003532002910000102
Then preparing a current expansion layer; depositing ITO (indium tin oxide) on the MESA steps, the surface of the P-type semiconductor layer 124 and the surface of the current barrier layer by utilizing a magnetron sputtering process, then photoetching to form a pattern, removing part of the ITO by utilizing an ITO corrosive liquid, and then removing photoresist; the current spreading layer is made of ITO (indium tin oxide) or Ag and has a thickness of
Figure BDA0003532002910000111
Then preparing an isolation groove, exposing a part to be etched on the MESA step through a photoetching process, then removing the N-type semiconductor layer and the buffer layer at the part of the MESA step by utilizing ICP etching, exposing the substrate and forming the isolation groove; the angle of the isolation groove is 30-80 degrees;
Then preparing a current transmission metal layer; firstly, photoetching to form a pattern, then evaporating metal, removing part of the metal layer by using a blue film stripping technology, and then removing photoresist; the metal layer material is a lamination of one or more of Cr, Al, Ti, Ni, Pt, Au and Ag; the current transmission metal layer is divided into an N-type current transmission metal layer and a P-type current transmission metal layer;
then preparing a Bragg reflection layer; depositing SiO on the surfaces of the MESA step, the P-type semiconductor layer 124, the current expansion layer and the current output metal layer by using an evaporation technology2With Ti3O5Laminating, and photoetching to form a pattern; removing part of the Bragg reflection layer by utilizing an ICP (inductively coupled plasma) etching process to form a Bragg reflection layer through hole, and then removing the photoresist; total thickness of Bragg reflection layer
Figure BDA0003532002910000112
Preparing a first reflection metal layer, photoetching to form a pattern, evaporating metal, removing part of the metal layer by using a blue film stripping technology, and removing photoresist; the first reflective metal layer is made of a laminated layer of one or more of Cr, Al, Ti, Ni, Pt, Au and Ag;
then preparing a first insulating layer, and depositing SiO on the surfaces of the Bragg reflection layer and the first reflection metal layer by using a PECVD (physical chemical deposition) process 2Then photoetching to form a pattern, and removing partial SiO by ICP etching process2And SiO2A Bragg reflection layer below the first insulation layer and forming a through hole of the Bragg reflection layer; the first insulating layer is made of SiO2Or SiN of thickness
Figure BDA0003532002910000113
Preparing a second reflective metal layer, photoetching to form a pattern, evaporating metal, removing part of the metal layer by using a blue film stripping technology, and removing photoresist; the second reflective metal layer is made of a laminated layer of one or more of Cr, Al, Ti, Ni, Pt, Au and Ag;
then preparing a second insulating layer, and depositing SiO on the surfaces of the first insulating layer and the second reflective metal layer by using a PECVD (physical chemical deposition) process2Then photoetching to form a pattern, and removing partial SiO by utilizing an ICP etching process2Forming a second insulating layer, a first insulating layer through hole and an independent second insulating layer through hole, and then removing the photoresist; the second insulating layer is made of SiO2Or SiN of thickness
Figure BDA0003532002910000114
Then preparing a bonding metal layer; photoetching to form a pattern, evaporating metal, removing part of the metal layer by using a blue film stripping technology, and removing photoresist; the bonding metal layer is made of a laminated layer of one or more of Cr, Al, Ti, Ni, Pt, Au and Ag; the bonding metal layer is divided into an N-type bonding metal layer and a P-type bonding metal layer;
The first reflecting metal layer is an N-type reflecting metal layer, the second reflecting metal layer is a P-type reflecting metal layer, the N-type reflecting metal layer is electrically connected with the N-type current transmission metal layer through a Bragg reflecting layer through hole, the P-type reflecting metal layer is electrically connected with the P-type current transmission metal layer through a first insulating layer and a Bragg reflecting layer through hole, the N-type bonding metal layer is electrically connected with the N-type reflecting metal layer through a second insulating layer and a first insulating layer through hole, and the P-type bonding metal layer is electrically connected with the P-type reflecting metal layer through a single second insulating layer through hole.
Referring to fig. 7, in another embodiment, the manufacturing method is used to manufacture the flip-chip light emitting diode chip in the second embodiment, and the manufacturing method goes through step S80 to step S91:
step S91, a second reflective metal layer is formed on the bragg reflective metal layer, a second insulating layer is formed on the second reflective metal layer, a first reflective metal layer is formed on the second insulating layer, a first insulating layer is formed on the first reflective metal layer, and a bonding metal layer is formed on the first insulating layer.
The first reflecting metal layer is a P-type reflecting metal layer, the second reflecting metal layer is an N-type reflecting metal layer, the P-type reflecting metal layer is electrically connected with the P-type current transmission metal layer through a Bragg reflecting layer through hole, the N-type reflecting metal layer is electrically connected with the N-type current transmission metal layer through a first insulating layer and a Bragg reflecting layer through hole, the P-type bonding metal layer is electrically connected with the P-type reflecting metal layer through a second insulating layer and a first insulating layer through hole, and the N-type bonding metal layer is electrically connected with the N-type reflecting metal layer through a single second insulating layer through hole.
In the description of the specification, reference to the description of "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above examples only show several embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present patent should be subject to the appended claims.

Claims (10)

1. A flip-chip light emitting diode chip, the chip comprising:
The epitaxial layer comprises a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are sequentially stacked, wherein an MESA step is arranged on the epitaxial layer to expose the N-type semiconductor layer, and an isolation groove is arranged on the MESA step to expose the substrate;
the chip also comprises a current blocking layer, a current expanding layer, a current transmission metal layer, a Bragg reflecting layer, a reflecting metal layer, an insulating layer and a bonding metal layer;
the reflective metal layer comprises a first reflective metal layer and a second reflective metal layer, the insulating layer comprises a first insulating layer and a second insulating layer, the first reflective metal layer and the second reflective metal layer are mutually staggered in the stacking height of the chip, one of the first insulating layer and the second insulating layer is arranged between the first reflective metal layer and the second reflective metal layer and corresponds to the first reflective metal layer, and the other one of the first insulating layer and the second insulating layer is arranged between the first reflective metal layer or the second reflective metal layer and the bonding metal layer.
2. The flip-chip light emitting diode chip of claim 1, wherein the current-carrying metal layers comprise an N-type current-carrying metal layer and a P-type current-carrying metal layer;
The first reflecting metal layer is an N-type reflecting metal layer, the second reflecting metal layer is a P-type reflecting metal layer, the first reflecting metal layer is in contact with the N-type current transmission metal layer, and the second reflecting metal layer is in contact with the P-type current transmission metal layer;
or, the first reflective metal layer is a P-type reflective metal layer, the second reflective metal layer is an N-type reflective metal layer, the first reflective metal layer is in contact with the P-type current transmission metal layer, and the second reflective metal layer is in contact with the N-type current transmission metal layer.
3. The flip-chip led chip of claim 2, wherein when the first reflective metal layer is an N-type reflective metal layer and the second reflective metal layer is a P-type reflective metal layer, the first reflective metal layer contacts the N-type current transmitting metal layer through the N-type reflective via hole formed on the bragg reflective layer to form an electrical connection, and the second reflective metal layer contacts the P-type current transmitting metal layer through the first insulating layer and the P-type reflective via hole formed on the bragg reflective layer to form an electrical connection.
4. The flip-chip light emitting diode chip of claim 3, wherein the bonding metal layers comprise an N-type bonding metal layer and a P-type bonding metal layer;
The N-type bonding metal layer is in contact with the first reflecting metal layer through the second insulating layer and an insulating layer through hole preset in the first insulating layer to form electrical connection, and the P-type bonding metal layer independently penetrates through the insulating layer through hole preset in the second insulating layer to be in contact with the second reflecting metal layer to form electrical connection.
5. The flip-chip led chip of claim 2, wherein when the first reflective metal layer is a P-type reflective metal layer and the second reflective metal layer is an N-type reflective metal layer, the first reflective metal layer contacts the P-type current transmitting metal layer through the first insulating layer and the P-type reflective via hole formed on the bragg reflective layer to form an electrical connection, and the second reflective metal layer contacts the N-type current transmitting metal layer through the N-type reflective via hole formed on the bragg reflective layer to form an electrical connection.
6. The flip-chip light emitting diode chip of claim 5, wherein the bonding metal layers comprise an N-type bonding metal layer and a P-type bonding metal layer;
the N-type bonding metal layer independently penetrates through a preset insulating layer through hole in the second insulating layer to be in contact with the first reflecting metal layer to form electrical connection, and the P-type bonding metal layer is in contact with the second reflecting metal layer through the second insulating layer and the preset insulating layer through hole in the first insulating layer to form electrical connection.
7. The flip-chip light emitting diode chip of claim 6, wherein the P-type current transport metal layers are densely arranged around the periphery of the N-type current transport metal layer to reduce a lateral current transport distance between the P-type current transport metal layers and the N-type current transport metal layers.
8. The flip-chip light emitting diode chip of any one of claims 1 to 7, wherein the depth of the MESA step is 15% to 30% of the thickness of the epitaxial layer.
9. The flip led chip of claim 8, wherein the angle of the isolation trench is between 30 ° and 80 °.
10. A method for producing a flip-chip light-emitting diode chip, for producing the flip-chip light-emitting diode chip as claimed in any one of claims 1 to 9, the method comprising:
providing a substrate;
manufacturing an epitaxial layer on the substrate, wherein the epitaxial layer comprises a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are sequentially stacked;
manufacturing an MESA step on the epitaxial layer to expose the N-type semiconductor layer;
manufacturing a current blocking layer on the MESA step and the P-type semiconductor layer;
Manufacturing a current expansion layer on the P-type semiconductor layer and the current barrier layer;
etching the MESA step, and removing the N-type semiconductor layer and the buffer layer at the MESA step to manufacture an isolation groove;
respectively manufacturing an N-type current transmission metal layer and a P-type current transmission metal layer on the MESA step and the expansion layer;
manufacturing Bragg reflection layers on the surfaces of the MESA step, the P-type semiconductor layer, the current expansion layer and the current transmission metal layer;
manufacturing a first reflection metal layer on the Bragg reflection metal layer, manufacturing a first insulating layer on the first reflection metal layer, manufacturing a second reflection metal layer on the first insulating layer, manufacturing a second insulating layer on the second reflection metal layer, and manufacturing a bonding metal layer on the second insulating layer;
or, a second reflective metal layer is fabricated on the bragg reflective metal layer, a second insulating layer is fabricated on the second reflective metal layer, a first reflective metal layer is fabricated on the second insulating layer, a first reflective layer is fabricated on the first reflective metal layer, and a bonding metal layer is fabricated on the first reflective layer.
CN202210212704.XA 2022-03-04 2022-03-04 Flip light-emitting diode chip and preparation method thereof Pending CN114709304A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115050878A (en) * 2022-07-27 2022-09-13 淮安澳洋顺昌光电技术有限公司 Flip LED chip and preparation method thereof
CN115579438A (en) * 2022-12-09 2023-01-06 江西兆驰半导体有限公司 LED chip with inverted silver mirror and preparation method thereof
CN115863514A (en) * 2023-03-03 2023-03-28 江西兆驰半导体有限公司 Vertical LED chip and preparation method thereof
CN116014046A (en) * 2022-12-29 2023-04-25 淮安澳洋顺昌光电技术有限公司 Light-emitting diode chip
CN117712245A (en) * 2024-02-05 2024-03-15 江西兆驰半导体有限公司 Flip LED chip and preparation method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115050878A (en) * 2022-07-27 2022-09-13 淮安澳洋顺昌光电技术有限公司 Flip LED chip and preparation method thereof
CN115579438A (en) * 2022-12-09 2023-01-06 江西兆驰半导体有限公司 LED chip with inverted silver mirror and preparation method thereof
CN116014046A (en) * 2022-12-29 2023-04-25 淮安澳洋顺昌光电技术有限公司 Light-emitting diode chip
CN115863514A (en) * 2023-03-03 2023-03-28 江西兆驰半导体有限公司 Vertical LED chip and preparation method thereof
CN117712245A (en) * 2024-02-05 2024-03-15 江西兆驰半导体有限公司 Flip LED chip and preparation method thereof

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