CN113690349B - Anti-fracture light-emitting diode chip and manufacturing method thereof - Google Patents
Anti-fracture light-emitting diode chip and manufacturing method thereof Download PDFInfo
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- CN113690349B CN113690349B CN202110735484.4A CN202110735484A CN113690349B CN 113690349 B CN113690349 B CN 113690349B CN 202110735484 A CN202110735484 A CN 202110735484A CN 113690349 B CN113690349 B CN 113690349B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
Abstract
The disclosure provides an anti-fracture light-emitting diode chip and a manufacturing method thereof, and belongs to the technical field of semiconductors. The anti-fracture light emitting diode chip comprises a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, a P-type electrode, an insulating layer and a protective layer; the P-type semiconductor layer is provided with a groove extending to the N-type semiconductor layer, the N-type electrode is arranged on the N-type semiconductor layer in the groove, and the P-type electrode is arranged on the P-type semiconductor layer; the insulating layer is paved in the groove and on the N-type electrode, the P-type semiconductor layer and the P-type electrode, and the protective layer is paved on the insulating layer; the fracture-preventing light-emitting diode chip further comprises a connecting part positioned in the groove, the connecting part is connected with the bottom of the groove and the side wall of the groove, and the orthographic projection of the connecting part on the N-type semiconductor layer is not overlapped with the orthographic projection of the N-type electrode on the N-type semiconductor layer. The LED chip can improve the fracture problem of the chip after laser stripping and improve the yield in the process of transferring the chip in large quantity.
Description
Technical Field
The disclosure relates to the field of semiconductor technology, and in particular, to an anti-fracture light emitting diode chip and a manufacturing method thereof.
Background
A light emitting diode (english: light Emitting Diode, abbreviated as LED) is a semiconductor device capable of emitting light. By adopting different semiconductor materials and structures, LEDs capable of covering a full color range from ultraviolet to infrared have been widely used in economic life such as display, decoration, communication, and the like.
The chip is a core device of the LED, and in the related art, the LED chip comprises a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, an N-type electrode, a P-type electrode, an insulating layer and a protective layer; an N-type semiconductor layer, an active layer and a P-type semiconductor layer are sequentially laminated on the first surface of the substrate; the P-type semiconductor layer is provided with a groove extending to the N-type semiconductor layer, so that a step is formed in the N-type semiconductor layer. The N-type electrode is arranged on the N-type semiconductor layer in the groove, and the P-type electrode is arranged on the P-type semiconductor layer; the insulating layer is laid in the groove and on the N-type electrode, the P-type semiconductor layer and the P-type electrode, and the protective layer is laid on the insulating layer.
After the substrate of the LED chip is peeled by the laser peeling technology, only a part of the N-type semiconductor layer with a relatively thin thickness (about 3.5 μm) remains under the N-type electrode. Under the influence of stress, the step in the N-type semiconductor layer is easily broken. Since the step in the N-type semiconductor layer is just the center of the chip, the step is preferentially broken, so that the yield of the chip in the mass transfer process is low.
Disclosure of Invention
The embodiment of the disclosure provides an anti-fracture light-emitting diode chip and a manufacturing method thereof, which can improve the problem that the chip is easy to fracture after laser stripping, thereby improving the yield in the process of transferring a large amount of chips. The technical scheme is as follows:
in one aspect, an anti-fracture light emitting diode chip is provided, the anti-fracture light emitting diode chip comprises a substrate, an epitaxial layer, an N-type electrode, a P-type electrode, an insulating layer and a protective layer; the epitaxial layer comprises an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are sequentially laminated on the substrate; the P-type semiconductor layer is provided with a groove extending to the N-type semiconductor layer, the N-type electrode is arranged on the N-type semiconductor layer in the groove, and the P-type electrode is arranged on the P-type semiconductor layer; the insulating layer is laid in the groove and on the N-type electrode, the P-type semiconductor layer and the P-type electrode, the protective layer is laid on the insulating layer,
the anti-fracture light emitting diode chip further comprises a connecting part positioned in the groove, the connecting part is connected with the bottom of the groove and the side wall of the groove, and the orthographic projection of the connecting part on the N-type semiconductor layer is not overlapped with the orthographic projection of the N-type electrode on the N-type semiconductor layer.
Optionally, the material of the connection portion is the same as the material of at least one of the epitaxial layers.
Optionally, the connecting portion is a right-angle triangular prism structure, two prismatic surfaces of the right-angle triangular prism are respectively connected with the bottom and the side wall of the groove, another prismatic surface of the right-angle triangular prism is an arc supporting surface of an inward groove, and the arc supporting surface is connected with the bottom and the side wall of the groove.
Optionally, the connection portion and the epitaxial layer are of a unitary structure.
Optionally, the fracture-preventing light emitting diode chip further includes a reinforcing layer, the reinforcing layer is located at an edge of the N-type semiconductor layer in the groove, the reinforcing layer connects a bottom of the groove and a side wall of the groove, and orthographic projection of the reinforcing layer on the N-type semiconductor layer is located at two sides of orthographic projection of the N-type electrode and the connecting portion on the N-type semiconductor layer.
Optionally, the reinforcement layer and the epitaxial layer are of a unitary structure.
Optionally, the upper surface of the reinforcement layer and the upper surface of the P-type semiconductor layer are located on the same plane.
In another aspect, there is provided a method of manufacturing a breakage-proof light emitting diode chip, the method comprising:
providing a substrate, wherein the substrate comprises a first surface and a second surface which are opposite;
growing an epitaxial layer on the substrate, wherein the epitaxial layer comprises an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are sequentially laminated on the substrate;
forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer, and forming a connecting part in the groove; the connecting part is connected with the bottom of the groove and the side wall of the groove, and the orthographic projection of the connecting part on the N-type semiconductor layer is not overlapped with the orthographic projection of the N-type electrode on the N-type semiconductor layer;
forming a P-type electrode on the P-type semiconductor layer;
forming an N-type electrode on the N-type semiconductor layer in the groove;
forming an insulating layer in the groove and on the N-type electrode, and on the P-type semiconductor layer and the P-type electrode;
forming a protective layer on the insulating layer;
thinning the substrate.
Optionally, forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer, and forming a connection portion in the groove at the same time, including:
forming a first patterned photoresist on the epitaxial layer by adopting a photoetching technology;
performing first etching on the epitaxial layer to etch a first groove extending towards the direction of the N-type semiconductor layer on the epitaxial layer;
forming a second patterned photoresist at the bottom of the first groove by adopting a photoetching technology;
continuing to etch the epitaxial layer for the second time to etch a second groove extending to the N-type semiconductor layer on the epitaxial layer, wherein a step is formed between the first groove and the second groove;
the step is etched, so that the step is changed into the connecting part, wherein the connecting part is of a right-angle triangular prism structure, two prismatic surfaces of the right-angle triangular prism are respectively connected with the bottom and the side wall of the groove, the other prismatic surface of the right-angle triangular prism is an arc-shaped supporting surface of an inward groove, and the arc-shaped supporting surface is connected with the bottom and the side wall of the groove.
Optionally, while forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer, the manufacturing method further includes:
and forming a reinforcing layer in the groove, wherein the reinforcing layer is positioned at the edge of the N-type semiconductor layer in the groove, the reinforcing layer is connected with the bottom of the groove and the side wall of the groove, and the orthographic projection of the reinforcing layer on the N-type semiconductor layer is positioned at two sides of the orthographic projection of the N-type electrode and the connecting part on the N-type semiconductor layer.
The technical scheme provided by the embodiment of the disclosure has the beneficial effects that:
the connecting part for connecting the bottom of the groove and the side wall of the groove is arranged in the groove, so that the connecting strength between the epitaxial layer and the N-type semiconductor layer can be enhanced. After the substrate of the epitaxial wafer is stripped by adopting the laser stripping technology, the connecting part can form a transition at the step part in the N-type semiconductor layer, so that the structural strength of the fracture origin part is enhanced, the epitaxial wafer is prevented from being broken from the step part, and the yield of the chip mass transfer process can be improved. And the orthographic projection of the connecting part on the substrate is not overlapped with the N-type electrode, so that the arrangement of the connecting part does not influence the normal operation of the N-type electrode.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic structural diagram of a light emitting diode chip for enhancing side light intensity according to an embodiment of the present disclosure;
FIG. 2 is a schematic view of a connection portion according to an embodiment of the present disclosure;
FIG. 3 is a partial structural top view of a fracture-resistant light emitting diode chip provided in an embodiment of the present disclosure;
FIG. 4 is a schematic distribution diagram of P-type pads and N-type pads provided by an embodiment of the present disclosure;
FIG. 5 is a flow chart of a method of fabricating a breakage-proof LED chip according to an embodiment of the present disclosure;
fig. 6 is an etching diagram of an epitaxial layer etching groove according to an embodiment of the present disclosure;
fig. 7 is a flowchart of another method for manufacturing a breakage-proof light emitting diode chip according to an embodiment of the present disclosure.
Detailed Description
For the purposes of clarity, technical solutions and advantages of the present disclosure, the following further details the embodiments of the present disclosure with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a light emitting diode chip for enhancing side light intensity according to an embodiment of the present disclosure, and as shown in fig. 1, a light emitting diode chip 100 includes a substrate 1, an epitaxial layer, an N-type electrode 5, a P-type electrode 6, an insulating layer 7, and a protective layer 8. The epitaxial layer includes an N-type semiconductor layer 2, an active layer 3, and a P-type semiconductor layer 4 sequentially stacked on a substrate 1. The P-type semiconductor layer 4 is provided with a recess 100a extending to the N-type semiconductor layer 2. An N-type electrode 5 is provided on the N-type semiconductor layer 2 in the recess 100a, and a P-type electrode 6 is provided on the P-type semiconductor layer 4. An insulating layer 7 is laid in the recess 100a and on the N-type electrode 5, and on the P-type semiconductor layer 4 and the P-type electrode 6, and a protective layer 8 is laid on the insulating layer 7.
The breakage-proof light emitting diode chip further includes a connection portion 91 located in the groove, and the connection portion 91 connects the groove bottom of the groove 100a and the side wall of the groove 100a. The orthographic projection of the connection portion 91 on the N-type semiconductor layer 2 does not coincide with the orthographic projection of the N-type electrode 5 on the N-type semiconductor layer 2.
According to the embodiment of the disclosure, the connecting part for connecting the bottom of the groove and the side wall of the groove is arranged in the groove, so that the connecting strength between the epitaxial layer and the N-type semiconductor layer can be enhanced. After the substrate of the epitaxial wafer is stripped by adopting the laser stripping technology, the connecting part can form a transition at the step part in the N-type semiconductor layer, so that the structural strength of the fracture origin part is enhanced, the epitaxial wafer is prevented from being broken from the step part, and the yield of the chip mass transfer process can be improved. And the orthographic projection of the connecting part on the substrate is not overlapped with the N-type electrode, so that the arrangement of the connecting part does not influence the normal operation of the N-type electrode.
In the embodiment of the present disclosure, the sidewalls of the groove to which the connection portion 91 is connected may include sidewalls of at least one of the N-type semiconductor layer 2, the active layer 3, and the P-type semiconductor layer 4.
Optionally, the material of the connection portion 91 is the same as that of at least one layer of the epitaxial layer, so as to ensure that the arrangement of the connection portion 91 does not affect the normal operation of the layers of the epitaxial layer.
For example, when the connection portion 91 connects the sidewalls of the N-type semiconductor layer 2, the connection portion 91 may be the same material as the N-type semiconductor layer 2. When the connection portion 91 connects the sidewalls of the N-type semiconductor layer 2, the active layer 3, and the P-type semiconductor layer 4, the material of the connection portion 91 may correspond to the materials of the N-type semiconductor layer 2, the active layer 3, and the P-type semiconductor layer 4, respectively, one by one.
Fig. 2 is a schematic structural diagram of a connecting portion provided in an embodiment of the disclosure, as shown in fig. 2, and referring to fig. 1, the connecting portion 91 is a right triangular prism structure, two prismatic surfaces of the right triangular prism are respectively connected with a groove bottom and a side wall of the groove, another prismatic surface of the right triangular prism 91 is an arc supporting surface 91a of an inward groove, and the arc supporting surface 91a connects the groove bottom of the groove 100a and the side wall of the groove 100a.
Through setting up connecting portion 91 as right angle triangular prism structure, can be better laminate with the step department in N type electrode formation region, form a better connection transition. The right-angle triangular prism structure of the structure has good supporting and connecting effects, and can ensure the connecting strength between the epitaxial layer and the N-type semiconductor layer 2.
It should be noted that, in the embodiment of the present disclosure, the maximum height of the connection portion 91 cannot exceed the upper surface of the P-type semiconductor layer 4, so as to prevent the volume of the chip from being excessively large. The height of the connection portion 91 is a height along the stacking direction of the epitaxial wafers.
In the embodiment of the present disclosure, the height of the connection portion 91 may be 0.5 to 1um.
Illustratively, the connection 91 is of unitary construction with the epitaxial layer. The connection portion 91 can be formed while the recess 100a extending to the N-type semiconductor layer 2 is opened in the epitaxial layer. In this way, the connection portion is a part of the epitaxial layer, which has a better effect of enhancing the connection strength of the epitaxial layer, thereby contributing to reduction of the occurrence of breakage.
Fig. 3 is a top view of a portion of a structure of a fracture-preventing light emitting diode chip according to an embodiment of the present disclosure, and as shown in fig. 3, the fracture-preventing light emitting diode chip 100 further includes a reinforcing layer 92 (not shown in fig. 1). The reinforcement layer 92 is located at the edge of the N-type semiconductor layer 2 in the recess 100a, and the reinforcement layer 92 connects the bottom of the recess 100a and the side wall of the recess 100a, and the orthographic projection of the reinforcement layer 92 on the N-type semiconductor layer 2 is located at both sides of the orthographic projection of the N-type electrode 5 and the connection portion 91 on the N-type semiconductor layer 2.
By providing the reinforcing layer 92 at the edge of the N-type semiconductor layer 2 in the recess 100a, the connection strength between the N-type semiconductor layer 2 and the epitaxial layer can be further enhanced, and the contact area between the reinforcing layer 92 and the N-type semiconductor layer 2 is larger, the range is wider, the supporting effect is better, thereby further preventing the chip from breaking from the step in the N-type semiconductor layer 2.
Optionally, the stiffening layer 92 is of unitary construction with the epitaxial layer. I.e., the reinforcement layer 92 can be formed while the recess 100a extending to the N-type semiconductor layer 2 is opened on the epitaxial layer. In this way, the stiffening layer 92 is part of the epitaxial layer, which is more effective in enhancing the bond strength of the epitaxial layer, thereby facilitating reduced fracture generation.
At this time, the material of the reinforcing layer 92 is the same as that of the epitaxial layer, so as to ensure that the arrangement of the reinforcing layer 92 does not affect the normal operation of each layer of the epitaxial layer.
Illustratively, in the stacking direction of the chips, the materials of the reinforcement layer 92 from bottom to top correspond to the materials of the N-type semiconductor layer 2, the active layer 3, and the P-type semiconductor layer 4, respectively.
Optionally, the upper surface of the reinforcement layer 92 is on the same plane as the upper surface of the P-type semiconductor layer 4. At this time, the reinforcing layer 92 performs the best reinforcing effect.
It should be noted that, in the embodiment of the present disclosure, the maximum height of the reinforcement layer 92 cannot exceed the upper surface of the P-type semiconductor layer 4, so as to prevent the volume of the chip from being excessively large. The height of the connection portion 91 is a height along the stacking direction of the epitaxial wafers.
Alternatively, the total thickness of the N-type semiconductor layer is 3.5um to 4um.
The thickness of the N-type semiconductor layer is thickened from original 3um to 3.5 um-4 um, so that the risk of chip breakage after the substrate is stripped can be further reduced.
Alternatively, the substrate 1 may be a patterned sapphire substrate. The patterned sapphire substrate is provided with a plurality of conical bulges which are uniformly distributed at intervals, the bottom diameter of each conical bulge is 1.3-1.7 um, and the height of each conical bulge 12 is 0.8-1.2 um.
Illustratively, the spacing between any two adjacent tapered projections is between 0.3 and 0.5um.
Alternatively, the N-type semiconductor layer 2 is N-type doped GaN, the active layer 3 includes InGaN layers and GaN layers alternately stacked, and the P-type semiconductor layer 4 is P-type doped GaN.
Alternatively, the N-type electrode 5 and the P-type electrode 6 each include a Cr layer, an Al layer, a Cr layer, a Ti layer, and an Al layer, which are sequentially stacked.
Alternatively, the insulating layer 7 includes a passivation layer and a distributed bragg reflection layer laminated in this order.
Wherein the passivation layer is a silicon oxide layer with a thickness of 400-600 nm, such as 500nm. The hardness of the silicon oxide is high, so that the chip can be effectively protected. The distributed Bragg reflection layer includes silicon oxide layers and titanium oxide layers alternately stacked, and the number of the silicon oxide layers and the titanium oxide layers is 30 to 40, such as 36.
It should be noted that, in the embodiment of the present disclosure, the insulating layer 7 is further laid on the connection portion 91 and the reinforcing layer 92 in the groove 100a.
Alternatively, the protective layer 8 may be a silicon oxide layer. The thickness is 400-600 nm, such as 500nm. The epitaxial wafer can be prevented from being corroded by oxygen and water vapor in the air by arranging the protective layer.
Optionally, the light emitting diode chip further includes an N-type pad 10 and a P-type pad 11. The insulating layer 7 is provided with an N-type via hole 7a extending to the N-type electrode 5 and a P-type via hole 7b extending to the P-type electrode 6. The N-type pad 10 is located on the N-type via hole 7a and the insulating layer 7 around the N-type via hole 7a, and the P-type pad 11 is located on the P-type via hole 7b and the insulating layer 7 around the P-type via hole 7b.
Illustratively, the N-type pad 10 and the P-type pad 11 are each a Ti/Al/Ti/Al/Ti/Au laminate structure. Wherein the thicknesses of the first Ti layer and the third Ti layer are 20nm, the thicknesses of the second Al layer and the fourth Al layer are 1100nm, the thickness of the fifth Ti layer is 110nm, and the thickness of the sixth Au layer is 300nm. The Ti layer can play an adhesive role, and the Al layer can play a reflecting role so as to reflect light rays emitted to the P-type bonding pad or the N-type bonding pad and increase light rays emitted by the chip from the transparent substrate. The Au layer serves as a solder layer, and the chip can be fixed on the circuit board by solder.
It should be noted that, in the embodiment of the present disclosure, as shown in fig. 1, a portion of the protection layer 8 is further coated on the sidewalls of the N-type pad 10 and the P-type pad 11.
Fig. 4 is a schematic distribution diagram of P-type pads and N-type pads provided in the embodiment of the present disclosure, referring to fig. 4, N-type pads 10 and P-type pads 11 are disposed on an insulating layer 7 at intervals, and the size of the disposed areas of N-type pads 10 and P-type pads 11 on insulating layer 7 is the same, so that stable electrical connection with a circuit board is facilitated.
The embodiment of the disclosure provides a manufacturing method of an anti-fracture light emitting diode chip, which is suitable for manufacturing the anti-fracture light emitting diode chip shown in fig. 1. Fig. 5 is a flowchart of a manufacturing method of a breakage-proof light emitting diode chip according to an embodiment of the present disclosure, referring to fig. 5, the manufacturing method includes:
step 501, a substrate is provided.
Wherein the substrate includes opposing first and second surfaces. The substrate may be a sapphire substrate.
Step 502, growing an epitaxial layer on a substrate.
The epitaxial layer comprises an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are sequentially stacked on the substrate.
Optionally, the step 502 may include:
an N-type semiconductor layer, an active layer and a P-type semiconductor layer are sequentially grown on a substrate by adopting a Metal organic chemical vapor deposition (English: metal-organic Chemical Vapor Deposition, MOCVD for short) technology.
Step 503, forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer, and forming a connection portion in the groove.
Optionally, the step 503 may include:
first, a first patterned photoresist is formed on an epitaxial layer of an N-type semiconductor layer by using a photolithography technique.
And secondly, performing first etching on the N-type semiconductor layer epitaxial layer to etch a first groove extending towards the N-type semiconductor layer of the N-type semiconductor layer on the N-type semiconductor layer epitaxial layer.
In the embodiment of the disclosure, the etching can be performed by adopting an inductively coupled plasma etching (English: inductively Coupled Plasma, abbreviated as ICP) technology.
And thirdly, removing the first patterned photoresist, and forming a second patterned photoresist at the bottom of the first groove of the N-type semiconductor layer by adopting a photoetching technology.
And fourthly, baking the second patterned photoresist at a high temperature to enable partial areas of the second patterned photoresist to be concave.
Wherein, the temperature of the high-temperature baking can be 150 ℃ and the time can be 30 minutes.
By baking the photoresist at a high temperature to recess a partial region of the second patterned photoresist, the subsequent etching may be facilitated to obtain the connection portion 91 having the arc-shaped supporting surface 91 a.
And fifthly, continuing to etch the N-type semiconductor layer epitaxial layer for the second time so as to etch a second groove extending to the N-type semiconductor layer of the N-type semiconductor layer on the N-type semiconductor layer epitaxial layer, wherein a connecting part is formed between the first groove of the N-type semiconductor layer and the second groove of the N-type semiconductor layer.
Illustratively, the etching rate of the second etching is gradually slowed, for example, from 5nm/s to 1nm/s, so as to prevent the etching rate from being too fast and damage to the surface of the N-type semiconductor layer in the later stage of etching.
Fig. 6 is an etching diagram of an epitaxial layer etching groove provided in an embodiment of the present disclosure, as shown in fig. 6, an I area in fig. 6 is a first etched area, an II area in fig. 6 is a second etched area, and 91 indicates a finally formed connection portion.
The connection portion 91 is a right-angle triangular prism structure, and the specific structure of the connection portion 91 may be described with reference to fig. 1 and 2, which are not described herein.
And sixthly, removing the second patterned photoresist.
Step 504, a P-type electrode is formed on the P-type semiconductor layer.
Optionally, the step 504 may include:
forming negative photoresist on the P-type semiconductor layer by adopting a photoetching technology;
forming an electrode material on the negative photoresist and the P-type semiconductor layer by adopting an evaporation technology;
and removing the negative photoresist and the electrode material on the negative photoresist, and forming the P-type electrode by the electrode material on the P-type semiconductor layer.
The P-type electrode comprises a Cr layer, an Al layer, a Cr layer, a Ti layer and an Al layer which are sequentially laminated.
Step 505, forming an N-type electrode on the N-type semiconductor layer in the recess.
Optionally, the step 505 may include:
forming negative photoresist on the N-type semiconductor layer in the groove by adopting a photoetching technology;
forming an electrode material on the N-type semiconductor layer in the negative photoresist and the groove by adopting an evaporation technology;
and removing the negative photoresist and electrode materials on the negative photoresist, and forming an N-type electrode by the electrode materials on the N-type semiconductor layer in the groove.
The N-type electrode comprises a Cr layer, an Al layer, a Cr layer, a Ti layer and an Al layer which are sequentially laminated.
And 506, forming an insulating layer in the groove and on the N-type electrode, and on the P-type semiconductor layer and the P-type electrode.
In an embodiment of the present disclosure, the insulating layer includes a passivation layer and a distributed bragg reflection layer that are sequentially stacked.
For example, the passivation layer may be formed using a PECVD (Plasma Enhanced Chemical Vapor Deposition ) method.
And 507, forming a protective layer on the insulating layer.
Wherein the protective layer is a silicon oxide layer with a thickness of 400-600 nm, such as 500nm.
Illustratively, the protective layer may be formed using a PECVD (Plasma Enhanced Chemical Vapor Deposition ) method.
According to the embodiment of the disclosure, the connecting part for connecting the bottom of the groove and the side wall of the groove is arranged in the groove, so that the connecting strength between the epitaxial layer and the N-type semiconductor layer can be enhanced. After the substrate of the epitaxial wafer is stripped by adopting the laser stripping technology, the connecting part can form a transition at the step part in the N-type semiconductor layer, so that the structural strength of the fracture origin part is enhanced, the epitaxial wafer is prevented from being broken from the step part, and the yield of the chip mass transfer process can be improved. And the orthographic projection of the connecting part on the substrate is not overlapped with the N-type electrode, so that the arrangement of the connecting part does not influence the normal operation of the N-type electrode.
Fig. 7 is a flowchart of another manufacturing method of a breakage-proof light emitting diode chip according to an embodiment of the present disclosure, referring to fig. 7, the manufacturing method includes:
step 701, providing a substrate.
Wherein the substrate includes opposing first and second surfaces. The substrate may be a sapphire substrate.
Step 702, patterning a substrate.
The first surface of the patterned sapphire substrate is provided with a plurality of conical protrusions which are uniformly distributed at intervals, the bottom diameter of each conical protrusion is 1.3-1.7 um, and the height of each conical protrusion is 0.8-1.2 um.
Step 703, growing an epitaxial layer on the substrate.
The epitaxial layer comprises an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are sequentially stacked on the substrate.
Alternatively, this step 703 may be the same as step 502 and will not be described in detail herein.
Step 704, forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer, and forming a connection portion and a reinforcement layer in the groove.
Optionally, step 704 may include:
first, a third patterned photoresist is formed on the epitaxial layer of the N-type semiconductor layer by using a photolithography technique.
And secondly, performing first etching on the N-type semiconductor layer epitaxial layer to etch a third groove extending towards the N-type semiconductor layer of the N-type semiconductor layer on the N-type semiconductor layer epitaxial layer, wherein a part of reinforcing layer is formed at the edge of the N-type semiconductor layer.
In the embodiment of the disclosure, the etching can be performed by adopting an inductively coupled plasma etching (English: inductively Coupled Plasma, abbreviated as ICP) technology.
And thirdly, removing the third patterned photoresist, and forming a fourth patterned photoresist at the bottom of the first groove of the N-type semiconductor layer by adopting a photoetching technology.
And fourthly, baking the second patterned photoresist at a high temperature to enable partial areas of the second patterned photoresist to be concave.
Wherein, the temperature of the high-temperature baking can be 150 ℃ and the time can be 30 minutes.
By baking the photoresist at a high temperature to recess a partial region of the second patterned photoresist, the subsequent etching may be facilitated to obtain the connection portion 91 having the arc-shaped supporting surface 91 a.
And fifthly, continuing to etch the N-type semiconductor layer epitaxial layer for the second time so as to etch a second groove extending to the N-type semiconductor layer of the N-type semiconductor layer on the N-type semiconductor layer epitaxial layer, wherein a connecting part is formed between the first groove of the N-type semiconductor layer and the second groove of the N-type semiconductor layer, and a reinforcing layer is formed at the edge of the N-type semiconductor layer.
The connection portion 91 is a right-angle triangular prism structure, and the specific structure of the connection portion 91 may be described with reference to fig. 1 and 2, which are not described herein.
In the embodiment of the disclosure, the reinforcing layer is located at the edge of the N-type semiconductor layer in the groove, and the reinforcing layer is connected with the groove bottom of the groove and the side wall of the groove, and the orthographic projection of the reinforcing layer on the N-type semiconductor layer is located at two sides of the orthographic projection of the N-type electrode and the connecting part on the N-type semiconductor layer 2. The specific structure of the reinforcing layer may be referred to in fig. 3 and the related description, and the embodiments of the present disclosure will not be repeated here.
Illustratively, the etching rate of the second etching is gradually slowed, for example, from 5nm/s to 1nm/s, so as to prevent the etching rate from being too fast and damage to the surface of the N-type semiconductor layer in the later stage of etching.
And sixthly, removing the second patterned photoresist.
Optionally, the manufacturing method may further include:
depositing Indium Tin Oxide (ITO) transparent conductive material on the surface of the epitaxial layer;
forming patterned photoresist on the transparent conductive material by adopting a photoetching technology;
wet etching the transparent conductive material to form a transparent conductive layer;
the patterned photoresist is removed.
Among them, hydrochloric acid solution can be used as the etching solution.
Step 705, forming a P-type electrode on the P-type semiconductor layer.
Alternatively, this step 705 may be the same as step 504 and will not be described in detail herein.
Step 706, forming an N-type electrode on the N-type semiconductor layer in the recess.
Alternatively, this step 706 may be the same as step 505 and will not be described in detail herein.
Step 707, forming an insulating layer in the recess and on the N-type electrode, and on the P-type semiconductor layer and the P-type electrode.
Alternatively, this step 707 may be the same as step 506 and will not be described in detail herein.
Step 708, an N-type via hole extending to the N-type electrode and a P-type via hole extending to the P-type electrode are formed in the insulating layer.
Optionally, step 708 may include:
forming patterned photoresist on the insulating layer by adopting a photoetching technology;
an N-type communication hole extending to the N-type electrode and a P-type communication hole extending to the P-type electrode are formed in the insulating layer by adopting a dry etching technology;
the patterned photoresist is removed.
Step 709, forming a P-type bonding pad on the insulating layer around the P-type communication hole in the P-type communication hole, and forming an N-type bonding pad on the insulating layer around the N-type communication hole and in the N-type communication hole.
Illustratively, the N-type pad and the P-type pad are each a Ti/Al/Ti/Al/Ti/Au laminate structure. Wherein the thicknesses of the first Ti layer and the third Ti layer are 20nm, the thicknesses of the second Al layer and the fourth Al layer are 1000nm, the thickness of the fifth Ti layer is 100nm, and the thickness of the sixth Au layer is 300nm.
Illustratively, step 709 may include:
forming negative photoresist on the insulating layer by adopting a photoetching technology;
forming a bonding pad material in the N-type communication hole, the P-type communication hole and the negative photoresist by adopting an evaporation technology;
and removing the negative photoresist and the bonding pad material of the negative photoresist, wherein the bonding pad material in the N-type communication hole and on the insulating layer around the N-type communication hole forms an N-type bonding pad, and the bonding pad material in the N-type communication hole and on the insulating layer around the N-type communication hole forms a P-type bonding pad.
Step 710, forming a protective layer on the insulating layer.
Alternatively, this step 710 may be the same as step 507 and will not be described in detail herein.
Step 711, thinning the substrate.
In the disclosed embodiment, the final thickness of the thinned substrate is about 60-120 um, e.g., 80um. The loss of light in the substrate is reduced while the support strength is ensured.
Optionally, the manufacturing method may further include:
and (5) invisible cutting and scribing are carried out on the substrate.
In practical application, the cutting can be performed by firstly utilizing the invisible cutting technology and then splitting, thereby being beneficial to improving the brightness. During invisible cutting, laser photons can be emitted from the back surface of the chip, and the laser wavelength can be 1024nm.
According to the embodiment of the disclosure, the connecting part for connecting the bottom of the groove and the side wall of the groove is arranged in the groove, so that the connecting strength between the epitaxial layer and the N-type semiconductor layer can be enhanced. After the substrate of the epitaxial wafer is stripped by adopting the laser stripping technology, the connecting part can form a transition at the step part in the N-type semiconductor layer, so that the structural strength of the fracture origin part is enhanced, the epitaxial wafer is prevented from being broken from the step part, and the yield of the chip mass transfer process can be improved. And the orthographic projection of the connecting part on the substrate is not overlapped with the N-type electrode, so that the arrangement of the connecting part does not influence the normal operation of the N-type electrode.
The foregoing description of the preferred embodiments of the present disclosure is provided for the purpose of illustration only, and is not intended to limit the disclosure to the particular embodiments disclosed, but on the contrary, the intention is to cover all modifications, equivalents, alternatives, and alternatives falling within the spirit and principles of the disclosure.
Claims (8)
1. The anti-fracture light-emitting diode chip comprises a substrate, an epitaxial layer, an N-type electrode, a P-type electrode, an insulating layer and a protective layer; the epitaxial layer comprises an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are sequentially laminated on the substrate; the P-type semiconductor layer is provided with a groove extending to the N-type semiconductor layer, the N-type electrode is arranged on the N-type semiconductor layer in the groove, and the P-type electrode is arranged on the P-type semiconductor layer; the insulating layer is paved in the groove and on the N-type electrode, the P-type semiconductor layer and on the P-type electrode, and the protective layer is paved on the insulating layer, and the insulating layer is characterized in that:
the anti-fracture light emitting diode chip further comprises a connecting part located in the groove, the connecting part is connected with the bottom of the groove and the side wall of the groove, the orthographic projection of the connecting part on the N-type semiconductor layer is not overlapped with the orthographic projection of the N-type electrode on the N-type semiconductor layer, the material of the connecting part is the same as that of the N-type semiconductor layer, the connecting part is of a right-angle triangular prism structure, two prismatic surfaces of the right-angle triangular prism are respectively connected with the bottom and the side wall of the groove, the bottom and the side wall of the groove are vertical, the other prismatic surface of the right-angle triangular prism is an arc supporting surface of the inward groove, the arc supporting surface is connected with the bottom of the groove and the side wall of the groove, and the maximum height of the connecting part is lower than the lower surface of the active layer.
2. The breakage preventing light emitting diode chip of claim 1, wherein the connection portion and the epitaxial layer are of unitary construction.
3. The breakage-proof light-emitting diode chip as claimed in claim 1 or 2, further comprising a reinforcing layer located at an edge of the N-type semiconductor layer within the groove, and connecting a bottom of the groove and a side wall of the groove, an orthographic projection of the reinforcing layer on the N-type semiconductor layer being located at both sides of an orthographic projection of the N-type electrode and the connecting portion on the N-type semiconductor layer.
4. The fracture-resistant light emitting diode chip of claim 3, wherein the stiffening layer is of unitary construction with the epitaxial layer.
5. The fracture-resistant light emitting diode chip of claim 3, wherein the upper surface of the stiffening layer is on the same plane as the upper surface of the P-type semiconductor layer.
6. A method of manufacturing a fracture-resistant light emitting diode chip, the method comprising:
providing a substrate, wherein the substrate comprises a first surface and a second surface which are opposite;
growing an epitaxial layer on the substrate, wherein the epitaxial layer comprises an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are sequentially laminated on the substrate;
forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer, and forming a connecting part in the groove; the connecting part is connected with the bottom of the groove and the side wall of the groove, the orthographic projection of the connecting part on the N-type semiconductor layer is not overlapped with the orthographic projection of the N-type electrode on the N-type semiconductor layer, the material of the connecting part is the same as that of the N-type semiconductor layer, the connecting part is of a right-angle triangular prism structure, two prismatic surfaces of the right-angle triangular prism are respectively connected with the bottom and the side wall of the groove, the bottom and the side wall of the groove are vertical, the other prismatic surface of the right-angle triangular prism is an arc supporting surface of an inward groove, the arc supporting surface is connected with the bottom and the side wall of the groove, and the maximum height of the connecting part is lower than the lower surface of the active layer;
forming a P-type electrode on the P-type semiconductor layer;
forming an N-type electrode on the N-type semiconductor layer in the groove;
forming an insulating layer in the groove and on the N-type electrode, and on the P-type semiconductor layer and the P-type electrode;
and forming a protective layer on the insulating layer.
7. The method of manufacturing according to claim 6, wherein forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer while forming a connection portion in the groove, comprises:
forming a first patterned photoresist on the epitaxial layer by adopting a photoetching technology;
performing first etching on the epitaxial layer to etch a first groove extending towards the direction of the N-type semiconductor layer on the epitaxial layer;
removing the first patterned photoresist, and forming a second patterned photoresist at the bottom of the first groove by adopting a photoetching technology;
baking the second patterned photoresist at a high temperature to enable a partial region of the second patterned photoresist to be concave;
continuing to etch the epitaxial layer for the second time to etch a second groove extending to the N-type semiconductor layer on the epitaxial layer, wherein a connecting part is formed between the first groove and the second groove, the connecting part is of a right-angle triangular prism structure, two prismatic surfaces of the right-angle triangular prism are respectively connected with the bottom and the side wall of the groove, the other prismatic surface of the right-angle triangular prism is an arc supporting surface of an inward groove, and the arc supporting surface is connected with the bottom and the side wall of the groove;
and removing the second patterned photoresist.
8. The method of manufacturing according to claim 6, wherein the method further comprises, while forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer:
and forming a reinforcing layer in the groove, wherein the reinforcing layer is positioned at the edge of the N-type semiconductor layer in the groove, the reinforcing layer is connected with the bottom of the groove and the side wall of the groove, and the orthographic projection of the reinforcing layer on the N-type semiconductor layer is positioned at two sides of the orthographic projection of the N-type electrode and the connecting part on the N-type semiconductor layer.
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