CN114093997B - Large-opening-angle light-emitting diode chip and manufacturing method thereof - Google Patents

Large-opening-angle light-emitting diode chip and manufacturing method thereof Download PDF

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CN114093997B
CN114093997B CN202111111348.4A CN202111111348A CN114093997B CN 114093997 B CN114093997 B CN 114093997B CN 202111111348 A CN202111111348 A CN 202111111348A CN 114093997 B CN114093997 B CN 114093997B
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layer
type semiconductor
semiconductor layer
light
grooves
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CN114093997A (en
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兰叶
王江波
朱广敏
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HC Semitek Zhejiang Co Ltd
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HC Semitek Zhejiang Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0025—Processes relating to coatings

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Abstract

The present disclosure provides a large-aperture light emitting diode chip and a manufacturing method thereof, which belong to the technical field of semiconductors. The insulating layer of the large-aperture LED chip comprises a passivation layer and a distributed Bragg reflection layer which are sequentially laminated, wherein the passivation layer is a silicon oxide layer, and the distributed Bragg reflection layer comprises a silicon oxide layer and a titanium oxide layer which are alternately laminated; the passivation layer is provided with a plurality of grooves on one surface contacted with the distributed Bragg reflection layer, the bottom surface of each groove is an inclined surface, and the inclined angle of the inclined surface is alpha which is more than or equal to 20 degrees and less than or equal to 40 degrees. The large-opening-angle light-emitting diode chip can improve the proportion of lateral light, increase the opening angle of the LED chip and obtain good light shape.

Description

Large-opening-angle light-emitting diode chip and manufacturing method thereof
Technical Field
The disclosure relates to the field of semiconductor technology, and in particular to a large-aperture light emitting diode chip and a manufacturing method thereof.
Background
A light emitting diode (english: light Emitting Diode, abbreviated as LED) is a semiconductor device capable of emitting light. By adopting different semiconductor materials and structures, LEDs capable of covering a full color range from ultraviolet to infrared have been widely used in economic life such as display, decoration, communication, and the like.
The chip is a core device of the LED, and in the related art, the LED chip comprises a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, an N-type electrode, a P-type electrode, an insulating layer and a protective layer; an N-type semiconductor layer, an active layer and a P-type semiconductor layer are sequentially laminated on the first surface of the substrate; the P-type semiconductor layer is provided with a groove extending to the N-type semiconductor layer, the N-type electrode is arranged on the N-type semiconductor layer in the groove, and the P-type electrode is arranged on the P-type semiconductor layer; the insulating layer is laid in the groove and on the N-type electrode, the P-type semiconductor layer and the P-type electrode, and the protective layer is laid on the insulating layer. Wherein the insulating layer includes a passivation layer and a distributed bragg reflection (Distributed Bragg Reflection, DBR) layer laminated in this order. Electrons provided by the N-type semiconductor layer and holes provided by the P-type semiconductor layer perform radiation recombination luminescence in the active layer. A portion of light emitted from the active layer may be emitted from the P-type semiconductor layer, and the DBR layer may reflect the portion of light back to the active layer so that the portion of light is finally emitted from the substrate direction, thereby improving the light emitting efficiency of the LED.
However, the existing LED chip structure has the problem of strong axial light, that is, the LED chip has strong luminous intensity in the vertical direction, and when the LED chip is far away from the vertical direction, the luminous intensity is obviously reduced, and the light emission of the LED side is weaker, so that the viewing angle of the display screen becomes limited.
Disclosure of Invention
The embodiment of the disclosure provides a large-opening-angle light-emitting diode chip and a manufacturing method thereof, which can improve the proportion of lateral light, increase the opening angle of the LED chip and obtain good light shape. The technical scheme is as follows:
in one aspect, a large-aperture-angle light-emitting diode chip is provided, which comprises a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, an N-type electrode, a P-type electrode, an insulating layer and a protective layer; the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially laminated on the first surface of the substrate; the P-type semiconductor layer is provided with a groove extending to the N-type semiconductor layer, the N-type electrode is arranged on the N-type semiconductor layer in the groove, and the P-type electrode is arranged on the P-type semiconductor layer; the insulating layer is laid in the groove and on the N-type electrode, the P-type semiconductor layer and the P-type electrode, the protective layer is laid on the insulating layer,
the insulation layer comprises a passivation layer and a distributed Bragg reflection layer which are sequentially laminated, wherein the passivation layer is a silicon oxide layer, and the distributed Bragg reflection layer comprises a silicon oxide layer and a titanium oxide layer which are alternately laminated; the passivation layer is provided with a plurality of light reflection grooves on one surface contacted with the distributed Bragg reflection layer, the bottom of each light reflection groove is an inclined surface, the inclined angle of the inclined surface is alpha, alpha is more than or equal to 20 degrees and less than or equal to 40 degrees, and the distributed Bragg reflection layer is positioned on the surface of the passivation layer and in the plurality of light reflection grooves.
Optionally, the inclination angle of the inclined plane gradually decreases from the middle of the passivation layer to the edge of the passivation layer.
Alternatively, the bottom surfaces of the plurality of light reflection grooves have inclination angles α1, α2, and α3, respectively, α1=20°, α2=30°, and α3=40°.
Optionally, the plurality of light reflection grooves are arranged at intervals, and the minimum interval between two adjacent light reflection grooves is 2-3 um.
Optionally, the orthographic projection of each light reflection groove on the passivation layer is round or elliptical.
Optionally, the length of each light reflection groove is 2-3 um, and the width is 1-2 um.
Optionally, the depth of each light reflection groove is 0.5-2.5 um.
In another aspect, there is provided a method of manufacturing a large-aperture light emitting diode chip, the method comprising:
providing a substrate, wherein the substrate comprises a first surface and a second surface which are opposite;
sequentially growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the first surface of the substrate;
forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer;
forming a P-type electrode on the P-type semiconductor layer;
forming an N-type electrode on the N-type semiconductor layer in the groove;
forming an insulating layer in the groove, on the N-type electrode, the P-type semiconductor layer and the P-type electrode, wherein the insulating layer comprises a passivation layer and a distributed Bragg reflection layer which are sequentially laminated, the passivation layer is a silicon oxide layer, and the distributed Bragg reflection layer comprises a silicon oxide layer and a titanium oxide layer which are alternately laminated; the passivation layer is provided with a plurality of light reflection grooves on one surface contacted with the distributed Bragg reflection layer, the groove bottom of each light reflection groove is an inclined surface, the inclined angle of the inclined surface is alpha, alpha is more than or equal to 20 degrees and less than or equal to 40 degrees, and the distributed Bragg reflection layer is positioned on the surface of the passivation layer and in the plurality of light reflection grooves;
and forming a protective layer on the insulating layer.
Optionally, forming an insulating layer in the groove and on the N-type electrode, and on the P-type semiconductor layer and the P-type electrode, includes:
forming the passivation layer in the groove and on the N-type electrode, and on the P-type semiconductor layer and the P-type electrode;
forming a plurality of light reflection grooves on the surface of the passivation layer by adopting a photoetching technology;
and forming the distributed Bragg reflection layer on one surface of the passivation layer where the plurality of light reflection grooves are formed and in the plurality of light reflection grooves.
Optionally, the forming the plurality of light reflection grooves on the surface of the passivation layer by using a photolithography technique includes:
coating a layer of photoresist on the surface of the passivation layer;
providing a mask plate with uneven thickness, so that the transmittance of the mask plate is different;
paving the mask plate on the passivation layer with the surface coated with the photoresist;
carrying out photoetching treatment on the passivation layer to ensure that the photoresist on the surface of the passivation layer has uneven thickness;
and removing the photoresist to form a plurality of light reflection grooves with inclined grooves bottoms on the surface of the passivation layer.
The technical scheme provided by the embodiment of the disclosure has the beneficial effects that:
the surface of the passivation layer is provided with the grooves, the bottoms of the grooves are inclined planes, and the inclined planes are equivalent to the reflection structures with the micro-scale. After the active layer performs compound luminescence, part of axial light is reflected by the inclined plane at the bottom of the groove on the surface of the passivation layer to become lateral light, so that the proportion of the axial light can be reduced, the proportion of the lateral light is improved, the axial light of the middle area occupies more space, the oblique angle is larger, the opening angle of the chip can be increased, good light shape can be obtained, and meanwhile, the brightness loss can not be caused.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic structural diagram of a large-aperture led chip according to an embodiment of the present disclosure;
FIG. 2 is a schematic view of a light reflection groove according to an embodiment of the present disclosure;
FIG. 3 is a top view of a passivation layer provided by an embodiment of the present disclosure;
FIG. 4 is a schematic distribution diagram of P-type pads and N-type pads provided by an embodiment of the present disclosure;
fig. 5 is a flowchart of a method for manufacturing a large-aperture led chip according to an embodiment of the present disclosure;
fig. 6 is a flowchart of another method for manufacturing a large-aperture led chip according to an embodiment of the present disclosure.
Detailed Description
For the purposes of clarity, technical solutions and advantages of the present disclosure, the following further details the embodiments of the present disclosure with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a large-aperture led chip according to an embodiment of the present disclosure, as shown in fig. 1, the large-aperture led chip includes a substrate 1, an N-type semiconductor layer 2, an active layer 3, a P-type semiconductor layer 4, an N-type electrode 5, a P-type electrode 6, an insulating layer 7, and a protective layer 8. An N-type semiconductor layer 2, an active layer 3, and a P-type semiconductor layer 4 are sequentially stacked on the first surface 1a of the substrate 1. The P-type semiconductor layer 4 is provided with a groove extending to the N-type semiconductor layer 2, the N-type electrode 5 is arranged on the N-type semiconductor layer 2 in the groove, and the P-type electrode 5 is arranged on the P-type semiconductor layer 4. An insulating layer 7 is laid in the recess and on the N-type electrode 5, and on the P-type semiconductor layer 4 and the P-type electrode 6, a protective layer 8 is laid on the insulating layer 7.
The insulating layer 7 includes a passivation layer 71 and a DBR layer 72, which are sequentially stacked. The passivation layer 71 is a silicon oxide layer, and the DBR layer 72 includes silicon oxide layers and titanium oxide layers alternately stacked.
Fig. 2 is a schematic structural diagram of a light reflection groove provided in an embodiment of the present disclosure, as shown in fig. 2, and in combination with fig. 1, a passivation layer 71 has a plurality of light reflection grooves 71a on a surface contacting with a DBR layer 72, and a groove bottom of each light reflection groove 71a is an inclined surface, and an inclination angle of the inclined surface is α, and α is 20 ° and α is less than or equal to 40 °. The DBR layer 72 is located on the surface of the passivation layer 71 and within the plurality of light reflection grooves 71a.
According to the embodiment of the disclosure, the plurality of grooves are formed in the surface of the passivation layer, the bottoms of the grooves are inclined planes, and the inclined planes are equivalent to the reflection structures with the micro structures. After the active layer performs compound luminescence, part of axial light is reflected by the inclined plane at the bottom of the groove on the surface of the passivation layer to become lateral light, so that the proportion of the axial light can be reduced, the proportion of the lateral light is improved, the axial light of the middle area occupies more space, the oblique angle is larger, the opening angle of the chip can be increased, good light shape can be obtained, and meanwhile, the brightness loss can not be caused.
As shown in fig. 2, in the embodiment of the present disclosure, the inclination angle of the groove bottom slope of the light reflection groove 71a is an acute included angle between the groove bottom of the light reflection groove 71a and the horizontal plane (the plane parallel to the surface of the passivation layer 71).
Alternatively, the inclination angle of the groove bottom slope of the light reflection groove 71a gradually decreases from the middle of the passivation layer 71 to the edge of the passivation layer 71.
Since the axial light in the middle of the chip is stronger, the inclination angle of the groove bottom inclined plane of the light reflection groove 71a located in the middle of the passivation layer 71 is set to be the largest, and the larger the corresponding reflection angle is, the more axial light is favorably reflected to the side of the chip, so that the opening angle of the chip can be increased. And the proportion of the axial light is gradually reduced from the middle part of the chip to the edge of the chip, so that the inclination angle of the inclined plane is correspondingly set to be gradually reduced, the light-emitting intensity of the lateral light can be further ensured, and a good light-emitting light shape is obtained.
Alternatively, the bottom surfaces of the plurality of light reflection grooves 71a are inclined at angles α1, α2, and α3, α1=20°, α2=30°, and α3=40°, respectively. Thus being beneficial to improving the light emitting uniformity of the LED chip. If the inclination angle is too large, the manufacturing cost and the manufacturing difficulty are increased.
Illustratively, in the embodiment of the present disclosure, the light reflection grooves 71a on the surface of the passivation layer 71 may be classified into three types, and the inclination angles of the bottom surfaces of the plurality of light reflection grooves gradually decrease from the middle of the passivation layer 71 to the edge of the passivation layer, 40 °, 30 °, and 20 °, respectively.
Fig. 3 is a top view of a passivation layer according to an embodiment of the present disclosure, as shown in fig. 3, a plurality of light reflection grooves 71a are arranged at intervals, and an interval d between two adjacent light reflection grooves 71a is 2-3 um.
If the interval d between two adjacent light reflection grooves 71a is too large, the angle increasing effect is not obvious; if the interval between two adjacent light reflection grooves 71a is too small, the processing difficulty increases.
Alternatively, the orthographic projection of each light reflection groove 71a on the passivation layer 71 is circular or elliptical.
In the embodiment of the present disclosure, the light reflection groove 71a may be formed on the passivation layer 71 using a photolithography technique, and the light reflection groove 71a orthographically projected in a circular shape or an elliptical shape may be easily formed during photolithography.
In other implementations of the embodiments of the present disclosure, the orthographic projection of each light reflection groove 71a on the passivation layer 71 may also be rectangular, polygonal, or the like. The embodiments of the present disclosure are not limited in this regard.
Alternatively, each light reflection groove 71a has a length L of 2 to 3um and a width D of 1 to 2um.
If the length or width of each light reflection groove 71a is too large, the area occupied by each light reflection groove 71a is too large, which may result in insignificant angle increasing effect; if the length or width of each light reflection groove 71a is too small, the area occupied by each light reflection groove 71a is too small, which increases the difficulty of manufacturing.
Alternatively, referring to fig. 3, the depth H of each light reflection groove 71a is 0.5 to 2.5um.
If the depth H of each light reflection groove 71a is too deep, the film layer is too thick and the stress is too large; if the depth H of each light reflection groove 71a is too shallow, a complete reflection cell cannot be formed.
Alternatively, the passivation layer 71 is a silicon oxide layer having a thickness of 3000 to 4000nm, such as 3500nm. The hardness of the silicon oxide is high, so that the chip can be effectively protected.
The number of the silicon oxide layers and the titanium oxide layers in the DBR layer 72 may be 30 to 40, such as 36. The reflection wavelength may be set at 465 nm.
Alternatively, the substrate 1 is a patterned sapphire substrate. The surface of the patterned sapphire substrate is provided with a plurality of conical bulges which are uniformly distributed at intervals, the bottom diameter of each conical bulge is 1.3-1.7 um, and the height of each conical bulge 12 is 0.8-1.2 um. The small-size graph can improve the diffuse reflection effect of light, further improve the angle of light emission, and therefore improve the light emitting efficiency of the chip.
Illustratively, the spacing between any two adjacent tapered projections is between 0.3 and 0.5um.
Alternatively, the N-type semiconductor layer 2 is N-type doped GaN, the active layer 3 includes InGaN layers and GaN layers alternately stacked, and the P-type semiconductor layer 4 is P-type doped GaN.
Alternatively, the N-type electrode 5 and the P-type electrode 6 each include a Cr layer, an Al layer, a Cr layer, a Ti layer, and an Al layer, which are sequentially stacked.
Alternatively, the protective layer 8 may be a silicon oxide layer. The thickness is 400-600 nm, such as 500nm. The epitaxial wafer can be prevented from being corroded by oxygen and water vapor in the air by arranging the protective layer.
Optionally, the light emitting diode chip further comprises an N-type pad 9 and a P-type pad 10. The insulating layer 7 is provided with an N-type via hole 7a extending to the N-type electrode 5 and a P-type via hole 7b extending to the P-type electrode 6. The N-type pad 9 is located on the N-type via hole 7a and the insulating layer 7 around the N-type via hole 7a, and the P-type pad 10 is located on the P-type via hole 7b and the insulating layer 7 around the P-type via hole 7b.
Illustratively, the N-type pad 9 and the P-type pad 10 are each a Ti/Al/Ti/Al/Ti/Au laminate structure. Wherein the thicknesses of the first Ti layer and the third Ti layer are 20nm, the thicknesses of the second Al layer and the fourth Al layer are 1000nm, the thickness of the fifth Ti layer is 100nm, and the thickness of the sixth Au layer is 300nm. The Ti layer can play an adhesive role, and the Al layer can play a reflecting role so as to reflect light rays emitted to the P-type bonding pad or the N-type bonding pad and increase light rays emitted by the chip from the transparent substrate. The Au layer serves as a solder layer, and the chip can be fixed on the circuit board by solder.
It should be noted that, in the embodiment of the present disclosure, as shown in fig. 1, a part of the protection layer 8 is further coated on the sidewalls of the N-type pad 9 and the P-type pad 10.
Fig. 4 is a schematic distribution diagram of P-type pads and N-type pads provided in the embodiment of the present disclosure, referring to fig. 4, N-type pads 9 and P-type pads 10 are disposed on an insulating layer 7 at intervals, and the size of the disposed areas of N-type pads 9 and P-type pads 10 on insulating layer 7 is the same, so that stable electrical connection with a circuit board is facilitated.
The embodiment of the disclosure provides a manufacturing method of a large-aperture-angle light-emitting diode chip, which is suitable for manufacturing the large-aperture-angle light-emitting diode chip shown in fig. 1. Fig. 5 is a flowchart of a method for manufacturing a large-aperture led chip according to an embodiment of the present disclosure, and referring to fig. 5, the method includes:
step 501, a substrate is provided.
Wherein the substrate may be a sapphire substrate.
Step 502, an N-type semiconductor layer, an active layer and a P-type semiconductor layer are sequentially grown on a substrate.
Optionally, the step 502 may include:
an N-type semiconductor layer, an active layer and a P-type semiconductor layer are sequentially grown on a substrate by adopting a Metal organic chemical vapor deposition (English: metal-organic Chemical Vapor Deposition, MOCVD for short) technology.
Step 503, forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer.
Optionally, the step 503 may include:
forming patterned photoresist on the P-type semiconductor layer by adopting a photoetching technology;
forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer by adopting an inductively coupled plasma etching (English: inductively Coupled Plasma, abbreviated as ICP) technology; wherein the etching depth may be 5um.
Step 504, a P-type electrode is formed on the P-type semiconductor layer.
Optionally, the step 504 may include:
forming negative photoresist on the P-type semiconductor layer by adopting a photoetching technology;
forming an electrode material on the negative photoresist and the P-type semiconductor layer by adopting an evaporation technology;
and removing the negative photoresist and the electrode material on the negative photoresist, and forming the P-type electrode by the electrode material on the P-type semiconductor layer.
The P-type electrode comprises a Cr layer, an Al layer, a Cr layer, a Ti layer and an Al layer which are sequentially laminated.
Step 505, forming an N-type electrode on the N-type semiconductor layer in the recess.
Optionally, the step 505 may include:
forming negative photoresist on the N-type semiconductor layer in the groove by adopting a photoetching technology;
forming an electrode material on the N-type semiconductor layer in the negative photoresist and the groove by adopting an evaporation technology;
and removing the negative photoresist and electrode materials on the negative photoresist, and forming an N-type electrode by the electrode materials on the N-type semiconductor layer in the groove.
The N-type electrode comprises a Cr layer, an Al layer, a Cr layer, a Ti layer and an Al layer which are sequentially laminated.
And 506, forming an insulating layer in the groove and on the N-type electrode, and on the P-type semiconductor layer and the P-type electrode.
In an embodiment of the present disclosure, the insulating layer includes a passivation layer and a DBR layer sequentially stacked. The passivation layer is a silicon oxide layer, and the DBR layer comprises silicon oxide layers and titanium oxide layers which are alternately laminated; the passivation layer is provided with a plurality of light reflection grooves on one surface contacted with the distributed Bragg reflection layer, the groove bottom of each light reflection groove is an inclined surface, the inclined angle of the inclined surface is alpha, alpha is more than or equal to 20 degrees and less than or equal to 40 degrees, and the distributed Bragg reflection layer is positioned on the surface of the passivation layer and in the plurality of light reflection grooves. The specific structure of the light reflection groove can be described with reference to the above embodiments, and the embodiments of the disclosure are not repeated here.
Alternatively, the passivation layer is a silicon oxide layer having a thickness of 3000 to 4000nm, such as 3500nm. The hardness of the silicon oxide is high, so that the chip can be effectively protected.
The number of the silicon oxide layer and the titanium oxide layer in the DBR layer may be 30 to 40, such as 36. The reflection wavelength may be set at 465 nm.
Illustratively, step 506 may include:
forming a passivation layer in the groove and on the N-type electrode, the P-type semiconductor layer and the P-type electrode;
and secondly, forming a plurality of light reflection grooves on the surface of the passivation layer by adopting a photoetching technology.
Illustratively, the second step may comprise:
forming patterned photoresist on the surface of the passivation layer by adopting a photoetching technology, wherein the patterned photoresist has uneven thickness;
forming a plurality of light reflection grooves with inclined grooves bottom on the surface of the passivation layer by adopting a dry etching technology;
the patterned photoresist is removed.
In the embodiment of the disclosure, a mask plate with a light blocking layer with uneven thickness can be arranged on the surface of the photoresist to form patterned photoresist with uneven thickness. The thinner the light blocking layer of the mask is, the higher the light transmittance is, and the thinner the corresponding photoresist is. And the thinner the photoresist, the shallower the depth of the finally formed light reflection groove.
And thirdly, forming a distributed Bragg reflection layer on one surface of the passivation layer where the plurality of light reflection grooves are formed and in the plurality of light reflection grooves.
For example, the passivation layer and the DBR layer may be formed using a PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma-enhanced chemical vapor deposition) method.
And 507, forming a protective layer on the insulating layer.
Wherein the protective layer is a silicon oxide layer with a thickness of 400-600 nm, such as 500nm.
Illustratively, the protective layer may be formed using a PECVD process.
According to the embodiment of the disclosure, the plurality of grooves are formed in the surface of the passivation layer, the bottoms of the grooves are inclined planes, and the inclined planes are equivalent to the reflection structures with the micro structures. After the active layer performs compound luminescence, part of axial light is reflected by the inclined plane at the bottom of the groove on the surface of the passivation layer to become lateral light, so that the proportion of the axial light can be reduced, the proportion of the lateral light is improved, the axial light of the middle area occupies more space, the oblique angle is larger, the opening angle of the chip can be increased, good light shape can be obtained, and meanwhile, the brightness loss can not be caused.
The embodiment of the disclosure provides another manufacturing method of a large-aperture-angle light-emitting diode chip, which is suitable for manufacturing the large-aperture-angle light-emitting diode chip shown in fig. 1. Fig. 6 is a flowchart of another manufacturing method of a large-aperture led chip according to an embodiment of the present disclosure, referring to fig. 6, the manufacturing method includes:
step 601, a substrate is provided.
Wherein the substrate may be a sapphire substrate.
Step 602, patterning a substrate.
The surface of the patterned sapphire substrate is provided with a plurality of conical protrusions which are uniformly distributed at intervals, the bottom diameter of each conical protrusion is 1.3-1.7 um, and the height of each conical protrusion is 0.8-1.2 um.
And 603, growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the substrate in sequence.
Alternatively, this step 603 may be the same as step 502 and will not be described in detail herein.
Step 604, forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer.
Alternatively, this step 604 may be the same as step 503 and will not be described in detail herein.
Optionally, the manufacturing method further comprises:
depositing an Indium Tin Oxide (ITO) transparent conductive material on the epitaxial layer;
forming patterned photoresist on the transparent conductive material by adopting a photoetching technology;
wet etching the transparent conductive material to form a transparent conductive layer;
the patterned photoresist is removed.
Among them, hydrochloric acid solution can be used as the etching solution.
Step 605, forming a P-type electrode on the P-type semiconductor layer.
Alternatively, this step 605 may be the same as step 504 and will not be described in detail herein.
Step 606, an N-type electrode is formed on the N-type semiconductor layer in the recess.
Alternatively, this step 606 may be the same as step 505 and will not be described in detail herein.
In step 607, an insulating layer is formed in the recess and on the N-type electrode, and on the P-type semiconductor layer and the P-type electrode.
Alternatively, this step 607 may be the same as step 506 and will not be described in detail herein.
Step 608, an N-type via hole extending to the N-type electrode and a P-type via hole extending to the P-type electrode are formed in the insulating layer.
Optionally, step 608 may include:
forming patterned photoresist on the insulating layer by adopting a photoetching technology;
an N-type communication hole extending to the N-type electrode and a P-type communication hole extending to the P-type electrode are formed in the insulating layer by adopting a dry etching technology;
the patterned photoresist is removed.
Step 609, forming a P-type bonding pad on the insulating layer around the P-type communication hole in the P-type communication hole, and forming an N-type bonding pad on the insulating layer around the N-type communication hole and in the N-type communication hole.
Illustratively, the N-type pad and the P-type pad are each a Ti/Al/Ti/Al/Ti/Au laminate structure. Wherein the thicknesses of the first Ti layer and the third Ti layer are 20nm, the thicknesses of the second Al layer and the fourth Al layer are 1000nm, the thickness of the fifth Ti layer is 100nm, and the thickness of the sixth Au layer is 300nm.
Illustratively, step 609 may include:
forming negative photoresist on the insulating layer by adopting a photoetching technology;
forming a bonding pad material in the N-type communication hole, the P-type communication hole and the negative photoresist by adopting an evaporation technology;
and removing the negative photoresist and the bonding pad material of the negative photoresist, wherein the bonding pad material in the N-type communication hole and on the insulating layer around the N-type communication hole forms an N-type bonding pad, and the bonding pad material in the N-type communication hole and on the insulating layer around the N-type communication hole forms a P-type bonding pad.
Step 610, a protective layer is formed on the insulating layer.
Alternatively, this step 610 may be the same as step 507 and will not be described in detail herein.
Step 611, thinning the substrate.
In the disclosed embodiment, the final thickness of the thinned substrate is about 60-120 um, for example 100um. The loss of light in the substrate is reduced while the support strength is ensured.
And 612, performing invisible cutting and scribing on the substrate.
In the embodiment of the disclosure, 5 scratches can be cut in a half depth close to the surface of the substrate by using a stealth cutting machine, and then the side surface of the chip is roughened. Then using ultraviolet surface dicing saw to cut the depth of about 40um, finally splitting and testing to obtain the chip. This is advantageous for further improving the overall opening angle of the chip.
According to the embodiment of the disclosure, the plurality of grooves are formed in the surface of the passivation layer, the bottoms of the grooves are inclined planes, and the inclined planes are equivalent to the reflection structures with the micro structures. After the active layer performs compound luminescence, part of axial light is reflected by the inclined plane at the bottom of the groove on the surface of the passivation layer to become lateral light, so that the proportion of the axial light can be reduced, the proportion of the lateral light is improved, the axial light of the middle area occupies more space, the oblique angle is larger, the opening angle of the chip can be increased, good light shape can be obtained, and meanwhile, the brightness loss can not be caused.
The foregoing description of the preferred embodiments of the present disclosure is provided for the purpose of illustration only, and is not intended to limit the disclosure to the particular embodiments disclosed, but on the contrary, the intention is to cover all modifications, equivalents, alternatives, and alternatives falling within the spirit and principles of the disclosure.

Claims (10)

1. The large-aperture-angle light-emitting diode chip comprises a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, an N-type electrode, a P-type electrode, an insulating layer and a protective layer; the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially laminated on the first surface of the substrate; the P-type semiconductor layer is provided with a groove extending to the N-type semiconductor layer, the N-type electrode is arranged on the N-type semiconductor layer in the groove, and the P-type electrode is arranged on the P-type semiconductor layer; the insulating layer is paved in the groove and on the N-type electrode, the P-type semiconductor layer and on the P-type electrode, and the protective layer is paved on the insulating layer, and the insulating layer is characterized in that:
the insulation layer comprises a passivation layer and a distributed Bragg reflection layer which are sequentially laminated, wherein the passivation layer is a silicon oxide layer, and the distributed Bragg reflection layer comprises a silicon oxide layer and a titanium oxide layer which are alternately laminated; the passivation layer is provided with a plurality of light reflection grooves on one surface contacted with the distributed Bragg reflection layer, the bottom of each light reflection groove is an inclined surface, the inclined angle of the inclined surface is alpha, alpha is more than or equal to 20 degrees and less than or equal to 40 degrees, and the distributed Bragg reflection layer is positioned on the surface of the passivation layer and in the plurality of light reflection grooves.
2. The large angle light emitting diode chip of claim 1, wherein the slope angle of the bevel decreases gradually from a middle portion of the passivation layer to an edge of the passivation layer.
3. The large-aperture led chip of claim 2, wherein the bottom surfaces of the plurality of light reflecting grooves have inclination angles α1, α2, and α3, α1=20°, α2=30°, and α3=40°, respectively.
4. The large aperture led chip of claim 1 wherein said plurality of light reflecting grooves are spaced apart, and wherein the spacing between two adjacent light reflecting grooves is 2-3 um.
5. The large angle led chip of claim 4, wherein each of said light reflecting grooves has a circular or oval shape in orthographic projection on said passivation layer.
6. The led chip of claim 5, wherein each of said light reflecting grooves has a length of 2-3 um and a width of 1-2 um.
7. The large aperture led chip of claim 5, wherein each of said light reflecting grooves has a depth of 0.5-2.5 um.
8. A method of manufacturing a large opening angle light emitting diode chip, the method comprising:
providing a substrate;
sequentially growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the substrate;
forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer;
forming a P-type electrode on the P-type semiconductor layer;
forming an N-type electrode on the N-type semiconductor layer in the groove;
forming an insulating layer in the groove, on the N-type electrode, the P-type semiconductor layer and the P-type electrode, wherein the insulating layer comprises a passivation layer and a distributed Bragg reflection layer which are sequentially laminated, the passivation layer is a silicon oxide layer, and the distributed Bragg reflection layer comprises a silicon oxide layer and a titanium oxide layer which are alternately laminated; the passivation layer is provided with a plurality of light reflection grooves on one surface contacted with the distributed Bragg reflection layer, the groove bottom of each light reflection groove is an inclined surface, the inclined angle of the inclined surface is alpha, alpha is more than or equal to 20 degrees and less than or equal to 40 degrees, and the distributed Bragg reflection layer is positioned on the surface of the passivation layer and in the plurality of light reflection grooves;
and forming a protective layer on the insulating layer.
9. The method of manufacturing according to claim 8, wherein forming an insulating layer in the recess and on the N-type electrode, and on the P-type semiconductor layer and the P-type electrode, comprises:
forming the passivation layer in the groove and on the N-type electrode, and on the P-type semiconductor layer and the P-type electrode;
forming a plurality of light reflection grooves on the surface of the passivation layer by adopting a photoetching technology;
and forming the distributed Bragg reflection layer on one surface of the passivation layer where the plurality of light reflection grooves are formed and in the plurality of light reflection grooves.
10. The method of manufacturing according to claim 9, wherein forming the plurality of light reflection grooves on the surface of the passivation layer using a photolithography technique comprises:
forming patterned photoresist on the surface of the passivation layer by adopting a photoetching technology, wherein the patterned photoresist has uneven thickness;
forming a plurality of light reflection grooves with inclined grooves bottom on the surface of the passivation layer by adopting a dry etching technology;
and removing the patterned photoresist.
CN202111111348.4A 2021-09-23 2021-09-23 Large-opening-angle light-emitting diode chip and manufacturing method thereof Active CN114093997B (en)

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