CN114093997B - Large-opening-angle light-emitting diode chip and manufacturing method thereof - Google Patents

Abstract

The present disclosure provides a large-aperture light emitting diode chip and a manufacturing method thereof, which belong to the technical field of semiconductors. The insulating layer of the large-aperture LED chip comprises a passivation layer and a distributed Bragg reflection layer which are sequentially laminated, wherein the passivation layer is a silicon oxide layer, and the distributed Bragg reflection layer comprises a silicon oxide layer and a titanium oxide layer which are alternately laminated; the passivation layer is provided with a plurality of grooves on one surface contacted with the distributed Bragg reflection layer, the bottom surface of each groove is an inclined surface, and the inclined angle of the inclined surface is alpha which is more than or equal to 20 degrees and less than or equal to 40 degrees. The large-opening-angle light-emitting diode chip can improve the proportion of lateral light, increase the opening angle of the LED chip and obtain good light shape.

Description

Large-angle light-emitting diode chip and manufacturing method thereof

technical field

The present disclosure relates to the technical field of semiconductors, in particular to a large-angle light-emitting diode chip and a manufacturing method thereof.

Background technique

A light emitting diode (English: Light Emitting Diode, referred to as: LED) is a semiconductor device that can emit light. By using different semiconductor materials and structures, LEDs can cover a full color range from ultraviolet to infrared, and have been widely used in economic life such as display, decoration, and communication.

The chip is the core device of the LED. In related technologies, the LED chip includes a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, an N-type electrode, a P-type electrode, an insulating layer, and a protective layer; the N-type semiconductor layer, The active layer and the P-type semiconductor layer are sequentially stacked on the first surface of the substrate; the P-type semiconductor layer is provided with a groove extending to the N-type semiconductor layer, and the N-type electrode is arranged on the N-type semiconductor layer in the groove , the P-type electrode is set on the P-type semiconductor layer; the insulating layer is laid on the groove and on the N-type electrode, and on the P-type semiconductor layer and the P-type electrode, and the protective layer is laid on the insulating layer. Wherein, the insulating layer includes a passivation layer and a distributed Bragg reflection (Distributed Bragg Reflection, DBR) layer stacked in sequence. The electrons provided by the N-type semiconductor layer and the holes provided by the P-type semiconductor layer undergo radiative recombination in the active layer to emit light. Part of the light emitted by the active layer will be emitted from the P-type semiconductor layer, and the DBR layer can reflect the part of the light back to the active layer, so that the part of the light is finally emitted from the direction of the substrate, thereby improving the light extraction efficiency of the LED.

However, the existing LED chip structure has the problem of strong axial light, that is, the LED chip has a strong luminous intensity in the vertical direction, and when it is far away from the vertical direction, the luminous intensity decreases significantly, and the luminous intensity of the LED side is weak, resulting in Display viewing angle becomes limited.

Contents of the invention

Embodiments of the present disclosure provide a large-angle light-emitting diode chip and a manufacturing method thereof, which can increase the ratio of side light, increase the aperture angle of the LED chip, and obtain a good light shape. Described technical scheme is as follows:

On the one hand, a large-angle light-emitting diode chip is provided, and the large-angle light-emitting diode chip includes a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, an N-type electrode, a P-type electrode, and an insulating layer. and a protective layer; the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially stacked on the first surface of the substrate; the P-type semiconductor layer is provided with a The groove of the semiconductor layer, the N-type electrode is arranged on the N-type semiconductor layer in the groove, the P-type electrode is arranged on the P-type semiconductor layer; the insulating layer is laid on the groove In the groove and on the N-type electrode, and on the P-type semiconductor layer and the P-type electrode, the protective layer is laid on the insulating layer,

The insulating layer includes a passivation layer and a distributed Bragg reflection layer stacked in sequence, the passivation layer is a silicon oxide layer, and the distributed Bragg reflection layer includes alternately stacked silicon oxide layers and titanium oxide layers; There are a plurality of light reflection grooves on the surface of the layer in contact with the distributed Bragg reflection layer, the groove bottom of each light reflection groove is a slope, and the slope angle of the slope is α, 20°≤α ≤40°, the distributed Bragg reflection layer is located on the surface of the passivation layer and in the plurality of light reflection grooves.

Optionally, from the middle of the passivation layer to the edge of the passivation layer, the inclination angle of the slope decreases gradually.

Optionally, the inclination angles of the bottom surfaces of the plurality of light reflection grooves are α1, α2 and α3 respectively, α1=20°, α2=30°, α3=40°.

Optionally, the plurality of light reflection grooves are arranged at intervals, and the minimum interval between two adjacent light reflection grooves is 2-3 um.

Optionally, the orthographic projection of each of the light reflection grooves on the passivation layer is circular or elliptical.

Optionally, each of the light reflecting grooves has a length of 2-3um and a width of 1-2um.

Optionally, the depth of each light reflection groove is 0.5-2.5um.

In another aspect, a method for manufacturing a large-angle light-emitting diode chip is provided, and the method includes:

providing a substrate comprising opposing first and second surfaces;

growing an N-type semiconductor layer, an active layer, and a P-type semiconductor layer in sequence on the first surface of the substrate;

opening a groove extending to the N-type semiconductor layer on the P-type semiconductor layer;

forming a P-type electrode on the P-type semiconductor layer;

forming an N-type electrode on the N-type semiconductor layer in the groove;

An insulating layer is formed in the groove and on the N-type electrode, and on the P-type semiconductor layer and the P-type electrode, and the insulating layer includes a passivation layer and a distributed Bragg reflection layer stacked in sequence, so The passivation layer is a silicon oxide layer, and the distributed Bragg reflection layer includes alternately stacked silicon oxide layers and titanium oxide layers; the side of the passivation layer in contact with the distributed Bragg reflection layer has a plurality of light rays Reflecting grooves, the groove bottom of each of the light reflecting grooves is a slope, and the slope angle of the slope is α, 20°≤α≤40°, and the distributed Bragg reflection layer is located on the surface of the passivation layer and in the plurality of light reflecting grooves;

A protective layer is formed on the insulating layer.

Optionally, the forming an insulating layer in the groove and on the N-type electrode, and on the P-type semiconductor layer and the P-type electrode includes:

forming the passivation layer in the groove and on the N-type electrode, and on the P-type semiconductor layer and the P-type electrode;

forming the plurality of light reflection grooves on the surface of the passivation layer by photolithography;

The distributed Bragg reflection layer is formed on the side of the passivation layer on which the plurality of light reflection grooves are formed and in the plurality of light reflection grooves.

Optionally, forming the plurality of light reflection grooves on the surface of the passivation layer using photolithography technology includes:

Coating a layer of photoresist on the surface of the passivation layer;

providing a reticle with uneven thickness, so that the light transmittance of the reticle is different;

laying the mask plate on the passivation layer coated with the photoresist;

Carrying out photolithography treatment to the passivation layer, so that the thickness of the photoresist on the surface of the passivation layer is uneven;

The photoresist is removed to form a plurality of light reflection grooves with slope bottoms on the surface of the passivation layer.

The beneficial effects brought by the technical solutions provided by the embodiments of the present disclosure are:

By arranging multiple grooves on the surface of the passivation layer, and the groove bottoms of the multiple grooves are slopes, the multiple slopes are equivalent to forming multiple micro reflection structures. After the electrons and holes recombine and emit light in the active layer, part of the axial light will be reflected by the slope at the bottom of the groove on the surface of the passivation layer and become side light, which can reduce the proportion of axial light and increase the side light. The proportion of axial light in the middle area is more, so the bevel angle is larger, which can increase the opening angle of the chip and obtain a good light shape without causing brightness loss.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.

FIG. 1 is a schematic structural diagram of a large-angle light-emitting diode chip provided by an embodiment of the present disclosure;

Fig. 2 is a schematic structural view of a light reflection groove provided by an embodiment of the present disclosure;

Fig. 3 is a top view of a passivation layer provided by an embodiment of the present disclosure;

4 is a schematic diagram of the distribution of P-type pads and N-type pads provided by an embodiment of the present disclosure;

Fig. 5 is a flow chart of a method for manufacturing a large-angle light-emitting diode chip provided by an embodiment of the present disclosure;

FIG. 6 is a flowchart of another method for manufacturing a large-angle light-emitting diode chip provided by an embodiment of the present disclosure.

Detailed ways

In order to make the purpose, technical solution and advantages of the present disclosure clearer, the implementation manners of the present disclosure will be further described in detail below in conjunction with the accompanying drawings.

Fig. 1 is a schematic structural diagram of a large-angle light-emitting diode chip provided by an embodiment of the present disclosure. As shown in Fig. 1 , the large-angle light-emitting diode chip includes a substrate 1, an N-type semiconductor layer 2, an active layer 3, a P type semiconductor layer 4, N-type electrode 5, P-type electrode 6, insulating layer 7 and protective layer 8. The N-type semiconductor layer 2 , the active layer 3 and the P-type semiconductor layer 4 are sequentially stacked on the first surface 1 a of the substrate 1 . The P-type semiconductor layer 4 is provided with a groove extending to the N-type semiconductor layer 2 , the N-type electrode 5 is arranged on the N-type semiconductor layer 2 in the groove, and the P-type electrode 5 is arranged on the P-type semiconductor layer 4 . The insulating layer 7 is laid in the groove and on the N-type electrode 5 , and on the P-type semiconductor layer 4 and the P-type electrode 6 , and the protective layer 8 is laid on the insulating layer 7 .

The insulating layer 7 includes a passivation layer 71 and a DBR layer 72 stacked in sequence. The passivation layer 71 is a silicon oxide layer, and the DBR layer 72 includes alternately stacked silicon oxide layers and titanium oxide layers.

FIG. 2 is a schematic structural view of a light reflection groove provided by an embodiment of the present disclosure. As shown in FIG. 2 , in combination with FIG. The groove bottoms of the light reflecting grooves 71a are all slopes, and the slope angle of the slopes is α, 20°≤α≤40°. The DBR layer 72 is located on the surface of the passivation layer 71 and inside the plurality of light reflection grooves 71a.

In the embodiment of the present disclosure, a plurality of grooves are arranged on the surface of the passivation layer, and the groove bottoms of the plurality of grooves are inclined surfaces, and the plurality of inclined surfaces are equivalent to forming a plurality of miniature reflective structures. After the electrons and holes recombine and emit light in the active layer, part of the axial light will be reflected by the slope at the bottom of the groove on the surface of the passivation layer and become side light, which can reduce the proportion of axial light and increase the side light. The proportion of axial light in the middle area is more, so the bevel angle is larger, which can increase the opening angle of the chip and obtain a good light shape without causing brightness loss.

As shown in FIG. 2, in the embodiment of the present disclosure, the inclination angle of the groove bottom slope of the light reflection groove 71a is an acute angle between the bottom of the light reflection groove 71a and the horizontal plane (the surface parallel to the surface of the passivation layer 71). angle.

Optionally, from the middle of the passivation layer 71 to the edge of the passivation layer 71 , the inclination angle of the groove bottom slope of the light reflection groove 71 a gradually decreases.

Since the axial light in the middle of the chip is relatively strong, setting the inclination angle of the groove bottom slope of the light reflection groove 71a located in the middle of the passivation layer 71 to the maximum will result in a larger corresponding reflection angle, which is beneficial for axial light. More reflection to the side of the chip, which can increase the chip angle. And from the middle of the chip to the edge of the chip, the proportion of axial light gradually decreases. Therefore, setting the inclination angle of the inclined surface to gradually decrease can further ensure the light intensity of the side light and obtain a good light shape.

Optionally, the inclination angles of the bottom surfaces of the plurality of light reflecting grooves 71a are α1, α2 and α3 respectively, α1=20°, α2=30°, α3=40°. This is beneficial to improving the uniformity of light output from the LED chip. If there are too many types of inclination angles, the manufacturing cost and difficulty will be increased.

Exemplarily, in the embodiment of the present disclosure, the light reflection grooves 71a on the surface of the passivation layer 71 can be divided into three types, and from the middle of the passivation layer 71 to the edge of the passivation layer, the bottom surfaces of the multiple light reflection grooves The angles of inclination gradually decrease to 40°, 30° and 20° respectively.

FIG. 3 is a top view of a passivation layer provided by an embodiment of the present disclosure. As shown in FIG. 3 , a plurality of light reflection grooves 71a are arranged at intervals, and the interval d between two adjacent light reflection grooves 71a is 2-2. 3um.

If the distance d between two adjacent light reflecting grooves 71a is too large, the effect of increasing the angle will not be obvious; if the distance between two adjacent light reflecting grooves 71a is too small, the processing difficulty will increase.

Optionally, the orthographic projection of each light reflection groove 71 a on the passivation layer 71 is circular or elliptical.

In the embodiment of the present disclosure, the light reflection groove 71 a can be formed on the passivation layer 71 by using photolithography technology, and the light reflection groove 71 a whose orthographic projection is circular or elliptical can be easily formed during the photolithography process.

In other implementations of the embodiments of the present disclosure, the orthographic projection of each light reflection groove 71 a on the passivation layer 71 may also be in other shapes such as rectangles and polygons. Embodiments of the present disclosure do not limit this.

Optionally, the length L of each light reflecting groove 71 a is 2-3 um, and the width D is 1-2 um.

If the length or width of each light reflection groove 71a is too large, the area occupied by each light reflection groove 71a is too large, which will cause the angle increase effect to be insignificant; if the length or width of each light reflection groove 71a is too small, Then the area occupied by each light reflection groove 71a is too small, which will increase the manufacturing difficulty.

Optionally, referring to FIG. 3 , the depth H of each light reflecting groove 71a is 0.5-2.5um.

If the depth H of each light reflection groove 71a is too deep, the film layer will be too thick and the stress will be too large; if the depth H of each light reflection groove 71a is too shallow, a complete reflection unit cannot be formed.

Optionally, the passivation layer 71 is a silicon oxide layer with a thickness of 3000-4000 nm, such as 3500 nm. The hardness of silicon oxide is relatively high, which can effectively protect the chip.

The number of silicon oxide layers and titanium oxide layers in the DBR layer 72 may be 30-40, such as 36. The reflection wavelength can be set according to 465nm.

Optionally, the substrate 1 is a patterned sapphire substrate. The surface of the patterned sapphire substrate has a plurality of evenly spaced conical protrusions, the bottom diameter of each conical protrusion is 1.3-1.7um, and the height of each conical protrusion 12 is 0.8-1.2um . Small-sized graphics can improve the effect of diffuse reflection of light, and further improve the angle of light emission, thereby improving the light extraction efficiency of the chip.

Exemplarily, the interval between any two adjacent conical protrusions is 0.3-0.5um.

Optionally, the N-type semiconductor layer 2 is N-type doped GaN, the active layer 3 includes alternately stacked InGaN layers and GaN layers, and the P-type semiconductor layer 4 is P-type doped GaN.

Optionally, both the N-type electrode 5 and the P-type electrode 6 include a Cr layer, an Al layer, a Cr layer, a Ti layer and an Al layer stacked in sequence.

Optionally, the protection layer 8 may be a silicon oxide layer. The thickness is 400-600nm, such as 500nm. The epitaxial wafer can be prevented from being corroded by oxygen and water vapor in the air by setting a protective layer.

Optionally, the LED chip further includes N-type pads 9 and P-type pads 10 . An N-type via hole 7 a extending to the N-type electrode 5 and a P-type via hole 7 b extending to the P-type electrode 6 are opened on the insulating layer 7 . The N-type pad 9 is located on the N-type via hole 7a and the insulating layer 7 around the N-type via hole 7a, and the P-type pad 10 is located on the P-type via hole 7b and the insulating layer 7 around the P-type via hole 7b.

Exemplarily, both the N-type pad 9 and the P-type pad 10 have a stacked structure of Ti/Al/Ti/Al/Ti/Au. Among them, the thickness of the first Ti layer and the third Ti layer are both 20nm, the thickness of the second Al layer and the fourth Al layer are both 1000nm, the thickness of the fifth Ti layer is 100nm, and the sixth layer of Au The thickness of the layer is 300 nm. The Ti layer can play the role of adhesion, and the Al layer can play the role of reflection, so as to reflect the light directed to the P-type pad or the N-type pad, so as to increase the light emitted by the chip from the transparent substrate. The Au layer acts as a solder layer, which can fix the chip on the circuit board through solder.

It should be noted that, in the embodiment of the present disclosure, as shown in FIG. 1 , part of the protective layer 8 is also coated on the sidewalls of the N-type pad 9 and the P-type pad 10 .

FIG. 4 is a schematic diagram of the distribution of P-type pads and N-type pads provided by an embodiment of the present disclosure. Referring to FIG. 9 and the P-type pad 10 have the same size on the insulating layer 7, which is convenient for forming a stable electrical connection with the circuit board.

An embodiment of the present disclosure provides a method for manufacturing a large-angle light-emitting diode chip, which is suitable for manufacturing the large-angle light-emitting diode chip shown in FIG. 1 . Fig. 5 is a flow chart of a method for manufacturing a large-angle light-emitting diode chip provided by an embodiment of the present disclosure. Referring to Fig. 5 , the manufacturing method includes:

Step 501, providing a substrate.

Wherein, the substrate may be a sapphire substrate.

Step 502 , growing an N-type semiconductor layer, an active layer, and a P-type semiconductor layer sequentially on the substrate.

Optionally, step 502 may include:

The metal-organic chemical vapor deposition (English: Metal-organic Chemical Vapor Deposition, MOCVD for short) technique is used to sequentially grow an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the substrate.

Step 503 , opening a groove extending to the N-type semiconductor layer on the P-type semiconductor layer.

Optionally, this step 503 may include:

Forming a patterned photoresist on the P-type semiconductor layer by photolithography;

Using an inductively coupled plasma etching (English: Inductively Coupled Plasma, ICP for short) technology is used to open a groove extending to the N-type semiconductor layer on the P-type semiconductor layer; wherein, the etching depth may be 5um.

Step 504, forming a P-type electrode on the P-type semiconductor layer.

Optionally, this step 504 may include:

Form a negative photoresist on the P-type semiconductor layer by photolithography;

Evaporation technology is used to form electrode materials on negative photoresist and P-type semiconductor layer;

The negative photoresist and the electrode material on the negative photoresist are removed, and the electrode material on the P-type semiconductor layer forms a P-type electrode.

Wherein, the P-type electrode includes a Cr layer, an Al layer, a Cr layer, a Ti layer and an Al layer stacked in sequence.

Step 505 , forming an N-type electrode on the N-type semiconductor layer in the groove.

Optionally, this step 505 may include:

Using photolithography technology to form a negative photoresist on the N-type semiconductor layer in the groove;

Using evaporation technology to form electrode materials on the negative photoresist and the N-type semiconductor layer in the groove;

The negative photoresist and the electrode material on the negative photoresist are removed, and the electrode material on the N-type semiconductor layer in the groove forms an N-type electrode.

Wherein, the N-type electrode includes a Cr layer, an Al layer, a Cr layer, a Ti layer and an Al layer stacked in sequence.

Step 506 , forming an insulating layer in the groove and on the N-type electrode, and on the P-type semiconductor layer and the P-type electrode.

In an embodiment of the present disclosure, the insulating layer includes a passivation layer and a DBR layer stacked in sequence. The passivation layer is a silicon oxide layer, and the DBR layer includes alternately stacked silicon oxide layers and titanium oxide layers; there are multiple light reflection grooves on the side of the passivation layer that is in contact with the distributed Bragg reflection layer, and the grooves of each light reflection groove The bottoms are slopes, and the slope angle is α, 20°≤α≤40°, and the distributed Bragg reflection layer is located on the surface of the passivation layer and in multiple light reflection grooves. Wherein, the specific structure of the light reflection groove can refer to the above-mentioned embodiments, and the embodiments of the present disclosure will not be repeated here.

Optionally, the passivation layer is a silicon oxide layer with a thickness of 3000-4000 nm, such as 3500 nm. The hardness of silicon oxide is relatively high, which can effectively protect the chip.

The number of silicon oxide layers and titanium oxide layers in the DBR layer may be 30-40, such as 36. The reflection wavelength can be set according to 465nm.

Exemplarily, step 506 may include:

The first step, forming a passivation layer in the groove and on the N-type electrode, and on the P-type semiconductor layer and the P-type electrode;

In the second step, a plurality of light reflection grooves are formed on the surface of the passivation layer by photolithography technology.

Exemplarily, the second step may include:

A patterned photoresist is formed on the surface of the passivation layer by photolithography, and the thickness of the patterned photoresist is uneven;

Using dry etching technology to form a plurality of light reflection grooves with slope bottoms on the surface of the passivation layer;

Remove the patterned photoresist.

In the embodiments of the present disclosure, a mask plate with an uneven thickness of the light-shielding layer may be disposed on the surface of the photoresist to form a patterned photoresist with an uneven thickness. The thinner the thickness of the light-blocking layer of the mask plate, the higher the light transmittance, and the thinner the thickness of the corresponding photoresist. The thinner the thickness of the photoresist, the shallower the depth of the finally formed light reflection groove.

The third step is to form a distributed Bragg reflection layer on the side of the passivation layer formed with a plurality of light reflection grooves and in the plurality of light reflection grooves.

Exemplarily, the passivation layer and the DBR layer may be formed by using a PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition) method.

Step 507, forming a protective layer on the insulating layer.

Wherein, the protective layer is a silicon oxide layer with a thickness of 400-600 nm, such as 500 nm.

Exemplarily, the protective layer can be formed by PECVD.

In the embodiment of the present disclosure, a plurality of grooves are arranged on the surface of the passivation layer, and the groove bottoms of the plurality of grooves are inclined surfaces, and the plurality of inclined surfaces are equivalent to forming a plurality of miniature reflective structures. After the electrons and holes recombine and emit light in the active layer, part of the axial light will be reflected by the slope at the bottom of the groove on the surface of the passivation layer and become side light, which can reduce the proportion of axial light and increase the side light. The proportion of axial light in the middle area is more, so the bevel angle is larger, which can increase the opening angle of the chip and obtain a good light shape without causing brightness loss.

The embodiment of the present disclosure provides another method for manufacturing a large-angle LED chip, which is suitable for manufacturing the large-angle LED chip shown in FIG. 1 . Fig. 6 is a flow chart of another method for manufacturing a large-angle light-emitting diode chip provided by an embodiment of the present disclosure. Referring to Fig. 6 , the manufacturing method includes:

Step 601, providing a substrate.

Wherein, the substrate may be a sapphire substrate.

Step 602, patterning the substrate.

Among them, the surface of the patterned sapphire substrate has a plurality of evenly spaced conical protrusions, the bottom diameter of each conical protrusion is 1.3-1.7um, and the height of each conical protrusion is 0.8-1.2um. um.

Step 603 , growing an N-type semiconductor layer, an active layer, and a P-type semiconductor layer sequentially on the substrate.

Optionally, step 603 may be the same as step 502, which will not be described in detail here.

Step 604, opening a groove extending to the N-type semiconductor layer on the P-type semiconductor layer.

Optionally, step 604 may be the same as step 503, which will not be described in detail here.

Optionally, the manufacturing method also includes:

Depositing indium tin oxide (Indium Tin Oxide, ITO) transparent conductive material on the epitaxial layer;

Use photolithography to form patterned photoresist on transparent conductive materials;

Wet etching of transparent conductive materials to form a transparent conductive layer;

Remove the patterned photoresist.

Among them, hydrochloric acid solution can be used as the etching solution.

Step 605, forming a P-type electrode on the P-type semiconductor layer.

Optionally, this step 605 may be the same as step 504, which will not be described in detail here.

Step 606, forming an N-type electrode on the N-type semiconductor layer in the groove.

Optionally, this step 606 may be the same as step 505, which will not be described in detail here.

Step 607 , forming an insulating layer in the groove and on the N-type electrode, and on the P-type semiconductor layer and the P-type electrode.

Optionally, this step 607 may be the same as step 506, which will not be described in detail here.

Step 608 , opening an N-type via hole extending to the N-type electrode and a P-type via hole extending to the P-type electrode on the insulating layer.

Optionally, step 608 may include:

Forming a patterned photoresist on the insulating layer by photolithography;

Opening N-type via holes extending to N-type electrodes and P-type via holes extending to P-type electrodes in the insulating layer by dry etching technology;

Remove the patterned photoresist.

Step 609 , forming a P-type pad in the P-type via hole on the insulating layer around the P-type via hole, and forming an N-type pad in the N-type via hole and on the insulating layer around the N-type via hole.

Exemplarily, both the N-type pad and the P-type pad have a stacked structure of Ti/Al/Ti/Al/Ti/Au. Among them, the thickness of the first Ti layer and the third Ti layer are both 20nm, the thickness of the second Al layer and the fourth Al layer are both 1000nm, the thickness of the fifth Ti layer is 100nm, and the sixth layer of Au The thickness of the layer is 300 nm.

Exemplarily, step 609 may include:

Form a negative photoresist on the insulating layer by photolithography;

Using evaporation technology to form a pad material in the N-type through hole, in the P-type through hole, and on the negative photoresist;

Remove the negative photoresist and the pad material on the negative photoresist, the pad material in the N-type via hole and on the insulating layer around the N-type via hole forms an N-type pad, and in the N-type via hole and The pad material on the insulating layer around the N-type via hole forms a P-type pad.

Step 610, forming a protective layer on the insulating layer.

Optionally, this step 610 may be the same as step 507, which will not be described in detail here.

Step 611 , thinning the substrate.

In an embodiment of the present disclosure, the final thickness of the thinned substrate is about 60-120 um, for example 100 um. In the case of ensuring the support strength, the loss of light in the substrate is reduced.

Step 612 , performing stealth dicing on the substrate.

In the embodiment of the present disclosure, a stealth dicing machine may be used to cut 5 scratches within half the depth of the surface of the substrate, and then roughen the side of the chip. Then use an ultraviolet surface cutting and dicing machine to cut out a depth of about 40um, and finally split and test to obtain the chip of the present invention. This is conducive to further improving the overall opening angle of the chip.

In the embodiment of the present disclosure, a plurality of grooves are arranged on the surface of the passivation layer, and the groove bottoms of the plurality of grooves are inclined surfaces, and the plurality of inclined surfaces are equivalent to forming a plurality of miniature reflective structures. After the electrons and holes recombine and emit light in the active layer, part of the axial light will be reflected by the slope at the bottom of the groove on the surface of the passivation layer and become side light, which can reduce the proportion of axial light and increase the side light. The proportion of axial light in the middle area is more, so the bevel angle is larger, which can increase the opening angle of the chip and obtain a good light shape without causing brightness loss.

The above descriptions are only optional embodiments of the present disclosure, and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection of the present disclosure. within range.

Claims (10)

1. A large-angle light-emitting diode chip, said large-angle light-emitting diode chip comprising a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, an N-type electrode, a P-type electrode, an insulating layer and a protective layer ; The N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially stacked on the first surface of the substrate; the P-type semiconductor layer is provided with a groove, the N-type electrode is arranged on the N-type semiconductor layer in the groove, the P-type electrode is arranged on the P-type semiconductor layer; the insulating layer is laid in the groove and On the N-type electrode, and on the P-type semiconductor layer and the P-type electrode, the protective layer is laid on the insulating layer, characterized in that: The insulating layer includes a passivation layer and a distributed Bragg reflection layer stacked in sequence, the passivation layer is a silicon oxide layer, and the distributed Bragg reflection layer includes alternately stacked silicon oxide layers and titanium oxide layers; There are a plurality of light reflection grooves on the surface of the layer in contact with the distributed Bragg reflection layer, the groove bottom of each light reflection groove is a slope, and the slope angle of the slope is α, 20°≤α ≤40°, the distributed Bragg reflection layer is located on the surface of the passivation layer and in the plurality of light reflection grooves. 2 . The large-angle light-emitting diode chip according to claim 1 , wherein, from the middle of the passivation layer to the edge of the passivation layer, the inclination angle of the slope gradually decreases. 3 . 3. The large-angle light-emitting diode chip according to claim 2, wherein the inclination angles of the bottom surfaces of the plurality of light reflection grooves are respectively α1, α2 and α3, α1=20°, α2=30°, α3=40°. 4 . The large-angle light-emitting diode chip according to claim 1 , wherein the plurality of light reflection grooves are arranged at intervals, and the distance between two adjacent light reflection grooves is 2-3 um. 5 . The large-angle light-emitting diode chip according to claim 4 , wherein the orthographic projection of each of the light reflection grooves on the passivation layer is circular or elliptical. 6 . The large-angle light-emitting diode chip according to claim 5 , wherein the length of each of the light reflection grooves is 2-3 um, and the width is 1-2 um. 7 . The large-angle light-emitting diode chip according to claim 5 , wherein the depth of each light reflection groove is 0.5-2.5 um. 8. A method for manufacturing a large-angle light-emitting diode chip, characterized in that the method comprises: providing a substrate; sequentially growing an N-type semiconductor layer, an active layer, and a P-type semiconductor layer on the substrate; opening a groove extending to the N-type semiconductor layer on the P-type semiconductor layer; forming a P-type electrode on the P-type semiconductor layer; forming an N-type electrode on the N-type semiconductor layer in the groove; An insulating layer is formed in the groove and on the N-type electrode, and on the P-type semiconductor layer and the P-type electrode, and the insulating layer includes a passivation layer and a distributed Bragg reflection layer stacked in sequence, so The passivation layer is a silicon oxide layer, and the distributed Bragg reflection layer includes alternately stacked silicon oxide layers and titanium oxide layers; the side of the passivation layer in contact with the distributed Bragg reflection layer has a plurality of light rays Reflecting grooves, the groove bottom of each of the light reflecting grooves is a slope, and the slope angle of the slope is α, 20°≤α≤40°, and the distributed Bragg reflection layer is located on the surface of the passivation layer and in the plurality of light reflecting grooves; A protective layer is formed on the insulating layer. 9. The manufacturing method according to claim 8, wherein an insulating layer is formed in the groove and on the N-type electrode, and on the P-type semiconductor layer and the P-type electrode, include: forming the passivation layer in the groove and on the N-type electrode, and on the P-type semiconductor layer and the P-type electrode; forming the plurality of light reflection grooves on the surface of the passivation layer by photolithography; The distributed Bragg reflection layer is formed on the side of the passivation layer on which the plurality of light reflection grooves are formed and in the plurality of light reflection grooves. 10. The manufacturing method according to claim 9, wherein the forming the plurality of light reflection grooves on the surface of the passivation layer using photolithography technology comprises: A patterned photoresist is formed on the surface of the passivation layer by photolithography, and the thickness of the patterned photoresist is uneven; Using dry etching technology to form a plurality of light reflection grooves with sloped groove bottoms on the surface of the passivation layer; removing the patterned photoresist.

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