CN113314650A - Light emitting diode chip for improving lateral light emitting intensity and manufacturing method thereof - Google Patents
Light emitting diode chip for improving lateral light emitting intensity and manufacturing method thereof Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
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Abstract
The disclosure provides a light emitting diode chip for improving lateral light emitting intensity and a manufacturing method thereof, and belongs to the technical field of semiconductors. The chip comprises a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, an N-type electrode, a P-type electrode, an insulating layer and a protective layer; the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially stacked on the first surface of the substrate; the N-type electrode is arranged on the N-type semiconductor layer, and the P-type electrode is arranged on the P-type semiconductor layer; the insulating layer is laid in the groove and on the N-type electrode, and on the P-type semiconductor layer and the P-type electrode, the protective layer is laid on the insulating layer, the insulating layer comprises a passivation layer and a distributed Bragg reflection layer which are sequentially stacked, at least one annular groove is formed in one surface of the passivation layer, which is in contact with the distributed Bragg reflection layer, and a plurality of aluminum oxide particles are filled in the at least one annular groove. The chip can increase the light-emitting effect of the chip on the side surface, and the stability of the visual effect of the chip under various observation angles is ensured.
Description
Technical Field
The disclosure relates to the technical field of semiconductors, and in particular relates to a light emitting diode chip for improving lateral light emitting intensity and a manufacturing method thereof.
Background
A Light Emitting Diode (LED) is a semiconductor device capable of Emitting Light. By adopting different semiconductor materials and structures, LEDs can cover the full color range from ultraviolet to infrared, and have been widely used in economic life for display, decoration, communication, and the like.
The chip is a core device of the LED, and in the related art, the LED chip comprises a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, an N-type electrode, a P-type electrode, an insulating layer and a protective layer; the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially stacked on the first surface of the substrate; a groove extending to the N-type semiconductor layer is formed in the P-type semiconductor layer, the N-type electrode is arranged on the N-type semiconductor layer in the groove, and the P-type electrode is arranged on the P-type semiconductor layer; the insulating layer is laid in the groove and on the N-type electrode, the P-type semiconductor layer and the P-type electrode, and the protective layer is laid on the insulating layer. The insulating layer includes a passivation layer and a Distributed Bragg Reflection (DBR) layer, which are sequentially stacked.
Through setting up the DBR layer in the above-mentioned flip LED chip, can increase substantially LED's luminous efficacy. Wherein, a part of light emitted by the active layer can be emitted from the P-type semiconductor layer, and the DBR layer can reflect the part of light back to the active layer, so that the part of light is finally emitted from the substrate direction, thereby improving the light emitting efficiency of the LED. However, the DBR layer has a problem of strong axial light, so that the light emitting intensity of the LED chip in the vertical direction is strong, and when the DBR layer is far away from the vertical direction, the light emitting intensity is significantly reduced, so that the light emitting from the side surface of the LED chip is weak, and the viewing angle of the display screen becomes limited.
Disclosure of Invention
The embodiment of the disclosure provides a light emitting diode chip for improving lateral light emitting intensity and a manufacturing method thereof, which can increase the light emitting effect of the LED chip on the side surface and ensure that the LED chip can also keep the stability of the visual effect under various observation angles. The technical scheme is as follows:
on one hand, the light emitting diode chip for improving the lateral light emitting intensity comprises a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, an N-type electrode, a P-type electrode, an insulating layer and a protective layer; the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially stacked on the first surface of the substrate; a groove extending to the N-type semiconductor layer is formed in the P-type semiconductor layer, the N-type electrode is arranged on the N-type semiconductor layer in the groove, and the P-type electrode is arranged on the P-type semiconductor layer; the insulating layer is laid in the groove and on the N-type electrode, the P-type semiconductor layer and the P-type electrode, the protective layer is laid on the insulating layer, the insulating layer comprises a passivation layer and a distributed Bragg reflection layer which are sequentially stacked,
and one surface of the passivation layer, which is in contact with the distributed Bragg reflection layer, is provided with at least one annular groove, and a plurality of aluminum oxide particles are filled in the at least one annular groove.
Optionally, each of the alumina particles has a diameter of 2-4 um.
Optionally, a surface of the passivation layer in contact with the distributed bragg reflector has a plurality of annular grooves, the plurality of annular grooves are all concentrically arranged with the passivation layer, and distances from the plurality of annular grooves to a center line of the passivation layer are different.
Optionally, the interval between any two adjacent annular grooves in the plurality of annular grooves is 10-30 um.
Optionally, the depth of each annular groove is 1-2 um.
Optionally, the width of each annular groove is 2-6 um.
Optionally, the light emitting diode chip further includes a light ray adjusting layer disposed on the second surface of the substrate, the light ray adjusting layer includes a body and a reflective layer, the body is a silicon oxide layer, a through hole is formed in the middle of the silicon oxide layer, the reflective layer is located in the through hole, the reflective layer includes i silicon oxide layers and titanium oxide layers which alternately grow periodically, i is greater than or equal to 1 and is less than or equal to 3.
Optionally, the second surface of the substrate has a plurality of dimples arranged in an array.
In another aspect, a method for manufacturing a light emitting diode chip capable of improving side light extraction intensity is provided, where the method includes:
sequentially growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on a substrate;
forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer;
forming a P-type electrode on the P-type semiconductor layer;
forming an N-type electrode on the N-type semiconductor layer in the groove;
forming an insulating layer in the groove and on the N-type electrode, and on the P-type semiconductor layer and the P-type electrode, wherein the insulating layer comprises a passivation layer and a distributed Bragg reflection layer which are sequentially stacked, at least one annular groove is formed in one surface of the passivation layer, which is in contact with the distributed Bragg reflection layer, and a plurality of aluminum oxide particles are filled in the at least one annular groove;
and forming a protective layer on the insulating layer.
Optionally, the manufacturing method comprises:
and carrying out laser treatment on the second surface of the substrate to form a plurality of pits on the second surface of the substrate, wherein the pits are arranged in an array.
The technical scheme provided by the embodiment of the disclosure has the following beneficial effects:
the surface of the passivation layer, which is in contact with the distributed Bragg reflector, is provided with at least one annular groove, and the at least one annular groove is filled with aluminum oxide particles, so that a strip for changing the photon direction can be formed on the passivation layer. Because the surface of the annular groove filled with the aluminum oxide particles is uneven and can generate diffuse reflection, when part of axial light emitted by the active layer emits to the insulating layer, the incident angle of the part of axial light is scattered by the aluminum oxide particles in the annular groove, the direction of the part of axial light is changed to be the side surface of the LED chip, the vertical reflection effect of the DBR layer can be weakened at the moment, the proportion of the lateral light of the LED chip is improved, the light emitting effect of the LED chip on the side surface is favorably increased, and the stability of the visual effect of the LED chip under various observation angles is ensured.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a light emitting diode chip for improving lateral light extraction intensity according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of an insulating layer according to an embodiment of the disclosure;
fig. 3 is a top view of a passivation layer provided by an embodiment of the present disclosure;
FIG. 4 is a cross-sectional view of a silicon oxide layer provided by an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a second surface of a substrate according to an embodiment of the disclosure;
FIG. 6 is a schematic distribution diagram of P-type pads and N-type pads provided by the embodiment of the present disclosure;
fig. 7 is a flowchart of a method for manufacturing a light emitting diode chip for improving lateral light extraction intensity according to an embodiment of the present disclosure;
fig. 8 is a flowchart of another method for manufacturing a light emitting diode chip capable of improving side light extraction intensity according to an embodiment of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a light emitting diode chip for improving lateral light extraction intensity, as shown in fig. 1, the light emitting diode chip includes a substrate 1, an N-type semiconductor layer 2, an active layer 3, a P-type semiconductor layer 4, an N-type electrode 5, a P-type electrode 6, an insulating layer 7, and a protective layer 8. An N-type semiconductor layer 2, an active layer 3, and a P-type semiconductor layer 4 are sequentially stacked on a first surface of the substrate 1. A groove extending to the N-type semiconductor layer 2 is formed in the P-type semiconductor layer 4, an N-type electrode 5 is arranged on the N-type semiconductor layer 2 in the groove, and the P-type electrode 5 is arranged on the P-type semiconductor layer 4. An insulating layer 7 is laid in the groove and on the N-type electrode 5, and on the P-type semiconductor layer 4 and the P-type electrode 6, and a protective layer 8 is laid on the insulating layer 7.
Fig. 2 is a schematic structural diagram of an insulating layer provided in an embodiment of the present disclosure, and as shown in fig. 2, the insulating layer 7 includes a passivation layer 71 and a DBR layer 72, which are sequentially stacked. The passivation layer 71 has at least one annular groove 71a on a surface thereof contacting the DBR layer 72.
Fig. 3 is a top view of a passivation layer provided by an embodiment of the present disclosure, and as shown in fig. 3, at least one annular groove 71a is filled with a plurality of alumina particles.
The embodiment of the disclosure may form a strip on the passivation layer for changing the photon direction by providing at least one annular groove on a surface of the passivation layer in contact with the distributed bragg reflector, and filling alumina particles in the at least one annular groove. Because the surface of the annular groove filled with the aluminum oxide particles is uneven and can generate diffuse reflection, when part of axial light emitted by the active layer emits to the insulating layer, the incident angle of the part of axial light is scattered by the aluminum oxide particles in the annular groove, the direction of the part of axial light is changed to be the side surface of the LED chip, the vertical reflection effect of the DBR layer can be weakened at the moment, the proportion of the lateral light of the LED chip is improved, the light emitting effect of the LED chip on the side surface is favorably increased, and the stability of the visual effect of the LED chip under various observation angles is ensured.
Optionally, each alumina particle has a diameter of 2-4 um (micrometers).
If the diameter of the alumina particles is too small, the number of the alumina particles to be filled is too large, and thus the cost is increased; if the diameter of the alumina particles is too large, the light scattering effect is not obvious.
Alternatively, the passivation layer 71 has a plurality of annular grooves 71a on a surface thereof contacting the DBR layer 72, the plurality of annular grooves 71a are each disposed concentrically with the passivation layer 71, and distances from the plurality of annular grooves 71a to a center line of the passivation layer 71 are different.
The provision of the plurality of annular grooves 71a has a larger area of the annular band than that of the annular groove of a single structure, so that the improvement effect on the light extraction from the side of the LED is better.
It should be noted that fig. 3 shows that the passivation layer 71 has two annular grooves 71a on the surface contacting the DBR layer 72. In other implementations of the embodiment of the present disclosure, the passivation layer 71 may also have, for example, one, three or four annular grooves 71a thereon, which is not limited by the embodiment of the present disclosure.
Illustratively, the passivation layer 71 has n annular grooves 71a on the side in contact with the DBR layer 72, 1. ltoreq. n.ltoreq.8.
Alternatively, referring to FIG. 3, the interval L between any adjacent two of the plurality of annular grooves 71a is 10-30 um.
If the interval L between two adjacent annular grooves 71a is too small, the machining becomes difficult. If the interval L between two adjacent annular grooves 71a is too large, the light changing effect is not preferable.
Illustratively, the intervals between any adjacent two of the plurality of annular grooves 71a are all equal. For example, 20um each, to facilitate the machining.
Optionally, the groove width d of each annular groove 71a is 2-6 um.
Wherein, the groove width d of the annular groove 71a is the length of the annular groove 71a along the cross section direction of the epitaxial wafer. If the groove width d of each annular groove 71a is too narrow, difficulty in machining may be increased. If the groove width d of each annular groove 71a is too wide, the effect of changing the light is not preferable.
Illustratively, the groove widths d of the plurality of annular grooves 71a are all equal. For example, the groove width d is 4um, so as to facilitate the processing and forming.
Optionally, referring to FIG. 2, the depth h of each annular groove 71a is 1-2 um.
Wherein the depth h of the annular groove 71a is the length of the annular groove 71a in the epitaxial wafer lamination direction. If the depth h of each annular groove 71a is too shallow, alumina particles do not easily aggregate. If the depth h of each annular groove 71a is too deep, a thicker passivation layer is required, resulting in an increase in cost.
Illustratively, the plurality of annular grooves 71a are all of equal depth. For example, the depth is 1.5um, so as to facilitate the processing and forming.
Optionally, the passivation layer 71 is a silicon oxide layer with a thickness of 4000-5000 nm, such as 4500 nm. The silicon oxide has higher hardness, and can effectively protect the chip.
Alternatively, the DBR layer 72 includes silicon oxide layers and titanium oxide layers that are alternately stacked, and the number of the silicon oxide layers and the titanium oxide layers is 30 to 40, such as 36.
Optionally, referring to fig. 1, the light emitting diode chip further includes a light adjusting layer 11 disposed on the second surface of the substrate 1, and the light adjusting layer 11 includes a body 111 and a reflective layer 112.
Fig. 4 is a cross-sectional view of a light adjusting layer according to an embodiment of the disclosure, as shown in fig. 4, a body 111 is a silicon oxide layer, and a through hole 111a is formed in the middle of the silicon oxide layer. The reflection layer 112 is located in the through hole 111a, the reflection layer 112 includes i silicon oxide layers 1121 and 1122 which are alternately grown periodically, i is greater than or equal to 1 and is less than or equal to 3. The number of i is not so large as to form a weak reflection region in the middle of the light adjusting layer.
The light adjusting layer 11 is composed of a silicon oxide layer 111 and a titanium oxide layer 112 which are alternately grown in at least two periods in the middle, and the light adjusting layer 11 is made of a silicon oxide layer in the edge. Therefore, the light ray adjusting layer can have a weak reflection effect on light rays from the quantum well in the area located in the center of the chip, and the edge area can have an anti-reflection effect on the light rays. Therefore, the light intensity of the central area of the LED chip is further weakened, the light intensity of the peripheral area of the chip is improved, and the side light emitting effect of the LED chip is enhanced.
Illustratively, the light ray adjusting layer 11 has a thickness of 150 to 250 nm. For example 200 nm.
Fig. 5 is a schematic structural diagram of a second surface of a substrate according to an embodiment of the present disclosure, and as shown in fig. 5, the second surface of the substrate 1 has a plurality of pits 1a, and the plurality of pits 1a are arranged in an array.
The light-emitting surface of the substrate 1 is provided with a plurality of pits 1a, so that a diffuse reflection structure is favorably formed. When the partial axial light that the active layer sent shoots towards the substrate, the incident angle of this partial axial light can change behind the diffuse reflection structure that is formed by a plurality of pits, and from the side light-emitting of LED chip, the vertical reflection effect of DBR layer can be weakened this moment, and the proportion of side direction light obtains promoting to be favorable to increasing the light-emitting effect of LED chip in the side, guarantee that the LED chip also can keep visual effect's stability under various observation angle.
Illustratively, the diameter of each pit 1a is 2-4 um, and the depth of each pit 1a is 1-2 um.
Illustratively, the interval between any two adjacent pits 1a is 2-3 mm along the row direction or the column direction of the array. Wherein the interval between the two pits 1a is the distance between the centers of the two pits 1 a.
Optionally, the substrate 1 is a sapphire substrate.
Alternatively, the protective layer 8 may be a silicon oxide layer with a thickness of 400 to 600nm, such as 500 nm. The protective layer can prevent the epitaxial wafer from being corroded by oxygen and water vapor in the air.
Optionally, the light emitting diode chip further includes an N-type pad 9 and a P-type pad 10. The insulating layer 7 is provided with an N-type via hole 7a extending to the N-type electrode 5 and a P-type via hole 7b extending to the P-type electrode 6. The N-type pad 9 is located on the insulating layer 7 around the N-type via hole 7a and the N-type via hole 7a, and the P-type pad 10 is located on the insulating layer 7 around the P-type via hole 7b and the P-type via hole 7 b.
Illustratively, the N-type pad 9 and the P-type pad 10 are each a Ti/Al/Ti/Al/Ti/Au stacked structure. The thickness of the first Ti layer and the thickness of the third Ti layer are both 20nm, the thickness of the second Al layer and the thickness of the fourth Al layer are both 1000nm, the thickness of the fifth Ti layer is 100nm, and the thickness of the sixth Au layer is 300 nm. The Ti layer can play a role in adhesion, and the Al layer can play a role in reflection so as to reflect light rays emitted to the P-type bonding pad or the N-type bonding pad and increase light rays emitted from the transparent substrate. The Au layer serves as a solder layer, and the chip can be fixed on the circuit board by solder.
It should be noted that, in the embodiment of the present disclosure, as shown in fig. 1, a part of the protective layer 8 is further coated on the sidewalls of the N-type pad 9 and the P-type pad 10.
Fig. 6 is a schematic distribution diagram of P-type pads and N-type pads provided by an embodiment of the present disclosure, and referring to fig. 6, N-type pads 9 and P-type pads 10 are disposed on insulating layer 7 at intervals, and the disposed areas of N-type pads 9 and P-type pads 10 on insulating layer 7 are the same in size, so as to facilitate forming stable electrical connection with a circuit board.
Alternatively, the N-type semiconductor layer 2 is N-type doped GaN, the active layer 3 includes InGaN layers and GaN layers alternately stacked, and the P-type semiconductor layer 4 is P-type doped GaN. Each of the N-type electrode 5 and the P-type electrode 6 includes a Cr layer, an Al layer, a Cr layer, a Ti layer, and an Al layer, which are sequentially stacked.
The embodiment of the disclosure provides a method for manufacturing a light emitting diode chip capable of improving lateral light extraction intensity, which is suitable for manufacturing the light emitting diode chip shown in fig. 1. Fig. 7 is a flowchart of a method for manufacturing a light emitting diode chip for improving lateral light extraction intensity, where referring to fig. 7, the method includes:
step 701: an N-type semiconductor layer, an active layer and a P-type semiconductor layer are sequentially grown on a substrate.
Optionally, the step 701 may include:
an N-type semiconductor layer, an active layer and a P-type semiconductor layer are sequentially grown on a substrate by using a Metal-organic Chemical Vapor Deposition (MOCVD) technology.
Step 702: and a groove extending to the N-type semiconductor layer is formed on the P-type semiconductor layer.
Optionally, this step 702 may include:
forming a patterned photoresist on the P-type semiconductor layer by adopting a photoetching technology;
forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer by adopting an Inductively Coupled Plasma etching (ICP); wherein, the etching depth can be 5 um.
Optionally, the manufacturing method further includes:
depositing Indium Tin Oxide (ITO) transparent conductive material on the epitaxial layer;
forming a patterned photoresist on the transparent conductive material by adopting a photoetching technology;
corroding the transparent conductive material by a wet method to form a transparent conductive layer;
and removing the patterned photoresist.
Step 703: and forming a P-type electrode on the P-type semiconductor layer.
Optionally, this step 703 may include:
forming a negative photoresist on the N-type semiconductor layer in the groove by adopting a photoetching technology;
forming an electrode material on the negative photoresist and the P-type semiconductor layer by adopting an evaporation technology;
and removing the negative photoresist and the electrode material on the negative photoresist, and forming a P-type electrode by the electrode material on the P-type semiconductor layer.
The P-type electrode comprises a Cr layer, an Al layer, a Cr layer, a Ti layer and an Al layer which are sequentially laminated.
Step 704: and forming an N-type electrode on the N-type semiconductor layer in the groove.
Optionally, this step 704 may include:
forming a negative photoresist on the P-type semiconductor layer by using a photoetching technology;
forming an electrode material on the negative photoresist and the N-type semiconductor layer in the groove by adopting an evaporation technology;
and removing the negative photoresist and the electrode material on the negative photoresist, and forming an N-type electrode by the electrode material on the N-type semiconductor layer in the groove.
The N-type electrode comprises a Cr layer, an Al layer, a Cr layer, a Ti layer and an Al layer which are sequentially laminated.
Step 705: and forming an insulating layer in the groove and on the N-type electrode, and the P-type semiconductor layer and the P-type electrode.
In the embodiment of the disclosure, the insulating layer includes a passivation layer and a distributed bragg reflector layer which are stacked in sequence, one surface of the passivation layer, which is in contact with the distributed bragg reflector layer, has at least one annular groove, and the at least one annular groove is filled with a plurality of aluminum oxide particles.
Optionally, this step 705 may include:
forming a passivation layer in the groove and on the N-type electrode, and on the P-type semiconductor layer and the P-type electrode;
processing at least one annular groove on the surface of the passivation layer by adopting a dry etching method;
spin-coating a plurality of alumina particles into at least one annular groove by adopting a spin-on glass method, standing for 60 minutes and curing;
a DBR layer is formed on a surface of the passivation layer having at least one annular groove.
Step 706: a protective layer is formed on the insulating layer.
Wherein the protective layer is a silicon oxide layer with a thickness of 400-600 nm, such as 500 nm.
Illustratively, the protective layer may be formed by a PECVD (Plasma Enhanced Chemical Vapor Deposition) method.
The embodiment of the disclosure may form a strip on the passivation layer for changing the photon direction by providing at least one annular groove on a surface of the passivation layer in contact with the distributed bragg reflector, and filling alumina particles in the at least one annular groove. Because the surface that is filled with the ring channel of aluminium oxide granule is unsmooth, can produce the diffuse reflection, consequently when the partial axial light that the active layer sent is to the insulating layer, the incident angle of this partial axial light can change after the ring channel, become the side of directive LED chip, the vertical reflection effect of DBR layer can be weakened this moment, the proportion of the side direction light of LED chip obtains promoting, thereby be favorable to increasing the light-emitting effect of LED chip at the side, guarantee that the LED chip also can keep visual effect's stability under various observation angles.
The embodiment of the present disclosure provides another method for manufacturing a light emitting diode chip capable of improving the lateral light extraction intensity, which is suitable for manufacturing the light emitting diode chip shown in fig. 1. Fig. 8 is a flowchart of another method for manufacturing a light emitting diode chip for improving side light extraction intensity according to an embodiment of the present disclosure, and referring to fig. 8, the manufacturing method includes:
step 801: an N-type semiconductor layer, an active layer and a P-type semiconductor layer are sequentially grown on a substrate.
Alternatively, step 801 may be the same as step 701 and will not be described in detail herein.
Step 802: and a groove extending to the N-type semiconductor layer is formed on the P-type semiconductor layer.
Alternatively, step 802 may be the same as step 702 and will not be described in detail herein.
Optionally, the manufacturing method further includes:
depositing Indium Tin Oxide (ITO) transparent conductive material on the epitaxial layer;
forming a patterned photoresist on the transparent conductive material by adopting a photoetching technology;
corroding the transparent conductive material by a wet method to form a transparent conductive layer;
and removing the patterned photoresist.
Step 803: and forming a P-type electrode on the P-type semiconductor layer.
Alternatively, this step 803 may be the same as step 703 and will not be described in detail here.
Step 804: and forming an N-type electrode on the N-type semiconductor layer in the groove.
Alternatively, step 804 may be the same as step 704 and will not be described in detail herein.
Step 805: and forming an insulating layer in the groove and on the N-type electrode, and the P-type semiconductor layer and the P-type electrode.
Alternatively, this step 805 may be the same as step 705 and will not be described in detail herein.
Step 806: an N-type via hole extending to the N-type electrode and a P-type via hole extending to the P-type electrode are formed in the insulating layer.
Optionally, step 806 may include:
forming a patterned photoresist on the insulating layer by adopting a photoetching technology;
adopting a dry etching technology to form an N-type communication hole extending to the N-type electrode and a P-type communication hole extending to the P-type electrode in the insulating layer;
and removing the patterned photoresist.
Step 807: a P-type pad is formed on the insulating layer in and around the P-type via hole in the P-type via hole, and an N-type pad is formed on the insulating layer in and around the N-type via hole.
Illustratively, the N-type pad 9 and the P-type pad 10 are each a Ti/Al/Ti/Al/Ti/Au stacked structure. The thickness of the first Ti layer and the thickness of the third Ti layer are both 20nm, the thickness of the second Al layer and the thickness of the fourth Al layer are both 1000nm, the thickness of the fifth Ti layer is 100nm, and the thickness of the sixth Au layer is 300 nm.
Illustratively, step 807 may include:
forming a negative photoresist on the insulating layer by using a photolithography technique;
forming pad materials in the N-type communicating holes, the P-type communicating holes and the negative photoresist by adopting an evaporation technology;
and removing the negative photoresist and the pad material on the negative photoresist, wherein the pad material in the N-type communication hole and on the insulating layer around the N-type communication hole forms an N-type pad, and the pad material in the N-type communication hole and on the insulating layer around the N-type communication hole forms a P-type pad.
Step 808 forms a protective layer on the insulating layer.
Alternatively, this step 808 may be the same as step 706 and will not be described in detail herein.
And step 809, thinning the substrate.
In the embodiment of the present disclosure, the final thickness of the thinned substrate is about 60 to 120 μm, for example, 80 μm. And the loss of light in the substrate is reduced under the condition of ensuring the supporting strength.
And 810, performing laser processing on the second surface of the substrate to form a plurality of pits on the second surface of the substrate.
Wherein the plurality of dimples are arranged in an array.
Illustratively, step 810 may include:
forming a plurality of pits in an array arrangement on a second surface of the substrate by using a laser dotting mode;
and treating the second surface of the substrate by using a KOH solution, and removing residues burnt by the laser.
The light ray adjusting layer comprises a body and a reflecting layer, the body is a silicon oxide layer, a through hole is formed in the middle of the silicon oxide layer, the reflecting layer is located in the through hole, the reflecting layer comprises i silicon oxide layers and titanium oxide layers which alternately grow in a periodic mode, and i is larger than or equal to 1 and smaller than or equal to 3.
Illustratively, the thickness of the light ray adjusting layer is 150-250 nm. For example 200 nm.
Illustratively, step 811 may include:
forming a silicon oxide layer on the second surface of the substrate by adopting a PECVD method;
forming a through hole in the middle of the silicon oxide layer by adopting a wet etching technology;
and i silicon oxide layers and titanium oxide layers which alternately grow in cycles are formed in the through holes, wherein i is more than or equal to 1 and less than or equal to 3.
Optionally, the manufacturing method further includes:
and cutting the substrate to obtain at least two mutually independent chips, and testing the chips.
In practical application, the cutting can be performed by firstly scratching and then splitting by using an invisible cutting technology, so that the cutting direction can be controlled, and the loss is reduced.
In the embodiment of the present disclosure, the steps 810 to 811 are optional steps.
The embodiment of the disclosure may form a strip on the passivation layer for changing the photon direction by providing at least one annular groove on a surface of the passivation layer in contact with the distributed bragg reflector, and filling alumina particles in the at least one annular groove. Because the surface of the annular groove filled with the aluminum oxide particles is uneven and can generate diffuse reflection, when part of axial light emitted by the active layer emits to the insulating layer, the incident angle of the part of axial light is scattered by the aluminum oxide particles in the annular groove, the direction of the part of axial light is changed to be the side surface of the LED chip, the vertical reflection effect of the DBR layer can be weakened at the moment, the proportion of the lateral light of the LED chip is improved, the light emitting effect of the LED chip on the side surface is favorably increased, and the stability of the visual effect of the LED chip under various observation angles is ensured.
The above description is intended to be exemplary only and not to limit the present disclosure, and any modification, equivalent replacement, or improvement made without departing from the spirit and scope of the present disclosure is to be considered as the same as the present disclosure.
Claims (10)
1. A light emitting diode chip for improving the side light emitting intensity comprises a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, an N-type electrode, a P-type electrode, an insulating layer and a protective layer; the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially stacked on the first surface of the substrate; a groove extending to the N-type semiconductor layer is formed in the P-type semiconductor layer, the N-type electrode is arranged on the N-type semiconductor layer in the groove, and the P-type electrode is arranged on the P-type semiconductor layer; the insulating layer is laid in the groove and on the N-type electrode, and the P-type semiconductor layer and the P-type electrode, the protective layer is laid on the insulating layer, the insulating layer includes a passivation layer and a distributed Bragg reflection layer which are stacked in sequence, and the semiconductor device is characterized in that:
and one surface of the passivation layer, which is in contact with the distributed Bragg reflection layer, is provided with at least one annular groove, and a plurality of aluminum oxide particles are filled in the at least one annular groove.
2. The light emitting diode chip as claimed in claim 1, wherein each of the alumina particles has a diameter of 2-4 um.
3. The light emitting diode chip as claimed in claim 1, wherein a surface of the passivation layer contacting the distributed bragg reflector has a plurality of annular grooves thereon, the plurality of annular grooves are all concentrically disposed with the passivation layer, and distances from the plurality of annular grooves to a center line of the passivation layer are different.
4. The light-emitting diode chip as claimed in claim 3, wherein the interval between any two adjacent annular grooves of the plurality of annular grooves is 10-30 um.
5. The light-emitting diode chip as claimed in claim 3, wherein each of the annular grooves has a depth of 1-2 um.
6. The light emitting diode chip as claimed in claim 3, wherein each of the annular grooves has a groove width of 2-6 um.
7. The light-emitting diode chip of any one of claims 1 to 6, wherein the light-emitting diode chip further comprises a light adjustment layer disposed on the second surface of the substrate, the light adjustment layer comprises a body and a reflective layer, the body is a silicon oxide layer, a through hole is formed in the middle of the silicon oxide layer, the reflective layer is located in the through hole, the reflective layer comprises i periods of silicon oxide layers and titanium oxide layers which are alternately grown, and i is greater than or equal to 1 and less than or equal to 3.
8. The light-emitting diode chip according to any one of claims 1 to 6, wherein the second surface of the substrate has a plurality of pits, and the plurality of pits are arranged in an array.
9. A manufacturing method of a light emitting diode chip for improving the lateral light extraction intensity is characterized by comprising the following steps:
sequentially growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on a substrate;
forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer;
forming a P-type electrode on the P-type semiconductor layer;
forming an N-type electrode on the N-type semiconductor layer in the groove;
forming an insulating layer in the groove and on the N-type electrode, and on the P-type semiconductor layer and the P-type electrode, wherein the insulating layer comprises a passivation layer and a distributed Bragg reflection layer which are sequentially stacked, at least one annular groove is formed in one surface of the passivation layer, which is in contact with the distributed Bragg reflection layer, and a plurality of aluminum oxide particles are filled in the at least one annular groove;
and forming a protective layer on the insulating layer.
10. The manufacturing method according to claim 9, characterized by comprising:
and carrying out laser treatment on the second surface of the substrate to form a plurality of pits on the second surface of the substrate, wherein the pits are arranged in an array.
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| CN114883469A (en) * | 2022-07-07 | 2022-08-09 | 华灿光电（浙江）有限公司 | Light emitting diode chip for improving current conduction and preparation method thereof |
| CN114093997B (en) * | 2021-09-23 | 2023-06-09 | 华灿光电（浙江）有限公司 | Large-opening-angle light-emitting diode chip and manufacturing method thereof |
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| CN114093997B (en) * | 2021-09-23 | 2023-06-09 | 华灿光电（浙江）有限公司 | Large-opening-angle light-emitting diode chip and manufacturing method thereof |
| CN114883469A (en) * | 2022-07-07 | 2022-08-09 | 华灿光电（浙江）有限公司 | Light emitting diode chip for improving current conduction and preparation method thereof |
| CN114883469B (en) * | 2022-07-07 | 2022-11-29 | 华灿光电（浙江）有限公司 | Light emitting diode chip for improving current conduction and preparation method thereof |
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