CN113990994A - High-stability light emitting diode chip and manufacturing method thereof - Google Patents
High-stability light emitting diode chip and manufacturing method thereof Download PDFInfo
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- CN113990994A CN113990994A CN202111051966.4A CN202111051966A CN113990994A CN 113990994 A CN113990994 A CN 113990994A CN 202111051966 A CN202111051966 A CN 202111051966A CN 113990994 A CN113990994 A CN 113990994A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000010410 layer Substances 0.000 claims abstract description 294
- 238000003466 welding Methods 0.000 claims abstract description 98
- 239000004065 semiconductor Substances 0.000 claims abstract description 85
- 239000011241 protective layer Substances 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims description 41
- 239000000758 substrate Substances 0.000 claims description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 29
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims description 26
- 229910000679 solder Inorganic materials 0.000 claims description 21
- 238000000231 atomic layer deposition Methods 0.000 claims description 13
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical group O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 7
- 238000007747 plating Methods 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 238000007738 vacuum evaporation Methods 0.000 claims description 3
- 238000007740 vapor deposition Methods 0.000 claims description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 8
- 239000003344 environmental pollutant Substances 0.000 abstract description 7
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- 239000010936 titanium Substances 0.000 description 17
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- 238000002161 passivation Methods 0.000 description 5
- 239000012466 permeate Substances 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 4
- 229910052594 sapphire Inorganic materials 0.000 description 4
- 239000010980 sapphire Substances 0.000 description 4
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 3
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- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0025—Processes relating to coatings
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Abstract
The disclosure provides a high-stability light emitting diode chip and a manufacturing method thereof, and belongs to the technical field of semiconductors. A first conductive hole extending to the N-type electrode and a second conductive hole extending to the P-type electrode are formed in the insulating layer of the chip, and the welding spots comprise a first welding spot and a second welding spot. The first welding points are positioned in the first conductive holes and on the surface of the insulating layer and are electrically connected with the corresponding N-type electrodes, and the second welding points are positioned in the second conductive holes and on the surface of the insulating layer and are electrically connected with the corresponding P-type electrodes. The parts of the first welding points and the second welding points, which are positioned on the surface of the insulating layer, are both of circular truncated cone structures, and the diameters of the cross sections of the circular truncated cone structures are gradually reduced along the stacking direction of the chips. And part of the protective layer of the chip is also coated on the side walls of the circular truncated cone structures of the first welding point and the second welding point. By adopting the light-emitting diode chip, pollutants such as water vapor and the like can be prevented from permeating between the protective layer and the side wall of the circular truncated cone structure, and the reliability of the light-emitting diode chip is improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a high-stability light emitting diode chip and a method for manufacturing the same.
Background
A Light Emitting Diode (LED) is a semiconductor device capable of Emitting Light. By adopting different semiconductor materials and structures, LEDs can cover the full color range from ultraviolet to infrared, and have been widely used in economic life for display, decoration, communication, and the like.
The chip is a core device of the LED, and in the related art, the LED chip comprises a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, an N-type electrode, a P-type electrode, an insulating layer and welding spots; an N-type semiconductor layer, an active layer and a P-type semiconductor layer are sequentially laminated on the surface of the substrate; a groove extending to the N-type semiconductor layer is formed in the P-type semiconductor layer, the N-type electrode is arranged on the N-type semiconductor layer in the groove, and the P-type electrode is arranged on the P-type semiconductor layer; the insulating layer is laid in the groove and on the N-type electrode, and the P-type semiconductor layer and the P-type electrode. The insulating layer is provided with a conductive hole extending to the N-type electrode and the P-type electrode, and the welding spot is positioned on the surface of the insulating layer and in the conductive hole and is electrically connected with the corresponding N-type electrode or the corresponding P-type electrode. The welding points are arranged so as to facilitate the LED chip to be welded on the circuit board through a reflow soldering mode. With the refinement of the display market, the requirement on the size of the chip is higher and higher, and when the size of the chip is small, the light ray is very seriously blocked by the electrode, and the brightness cannot meet the requirement of display, so that the Mini LED chip is produced.
The solder joints of the Mini LED usually need to be entirely exposed for subsequent soldering, but the metal in the Mini LED has relatively steep sidewalls. When the exposed welding spot is used, pollutants such as water vapor and the like can slowly permeate from the side surface of the welding spot, then the problem of corrosion and the like can be caused to the interface, and finally the reliability of the chip is reduced, so that the popularization of products is not facilitated.
Disclosure of Invention
The embodiment of the disclosure provides a high-stability light emitting diode chip and a manufacturing method thereof, which can prevent pollutants such as water vapor from permeating between a protective layer and the side wall of a circular truncated cone structure, thereby improving the reliability of the light emitting diode chip. The technical scheme is as follows:
on one hand, the high-stability light-emitting diode chip comprises a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, an N-type electrode, a P-type electrode, an insulating layer and welding spots; the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially laminated on the surface of the substrate; a groove extending to the N-type semiconductor layer is formed in the P-type semiconductor layer, the N-type electrode is arranged on the N-type semiconductor layer in the groove, and the P-type electrode is arranged on the P-type semiconductor layer; the insulating layer is laid in the groove, on the N-type electrode, on the P-type semiconductor layer and the P-type electrode, and is characterized in that:
the insulating layer is provided with a first conductive hole extending to the N-type electrode and a second conductive hole extending to the P-type electrode, the welding spots comprise a first welding spot and a second welding spot, the first welding spot is positioned in the first conductive hole and on the surface of the insulating layer and is electrically connected with the corresponding N-type electrode, and the second welding spot is positioned in the second conductive hole and on the surface of the insulating layer and is electrically connected with the corresponding P-type electrode; the parts, located on the surface of the insulating layer, of the first welding points and the second welding points are both in a circular truncated cone structure, and the diameter of the cross section of the circular truncated cone structure is gradually reduced along the stacking direction of the chips;
the high-stability light-emitting diode chip further comprises a protective layer, wherein the protective layer is laid on all regions of the insulating layer except the setting regions of the welding spots, and part of the protective layer is further coated on the side walls of the circular truncated cone structures of the first welding spot and the second welding spot.
Optionally, an included angle between the side wall of the circular truncated cone structure and the bottom surface of the circular truncated cone structure is α, and α is greater than or equal to 35 ° and less than 45 °.
Optionally, the first solder joint and the second solder joint are both a Ti/Al/Ti/Au stacked structure.
Optionally, the protective layer includes a first sublayer, a second sublayer, a third sublayer, a fourth sublayer and a fifth sublayer that are sequentially stacked, the first sublayer and the fifth sublayer are both silicon oxide layers prepared by a vapor deposition method of plasma enhanced chemistry, the second sublayer and the fourth sublayer are both silicon oxide layers prepared by an ALD method, and the third sublayer is an aluminum oxide layer prepared by an atomic layer deposition method.
Optionally, the thicknesses of the first sublayer and the fifth sublayer are the same, the thicknesses of the second sublayer and the fourth sublayer are the same, the thickness of the first sublayer is greater than that of the second sublayer, and the thickness of the second sublayer is greater than that of the third sublayer.
Optionally, the total thickness of the protective layer is 400-1000 nm.
On the other hand, the manufacturing method of the high-stability light emitting diode chip is provided, wherein a substrate is provided;
growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the substrate in sequence;
forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer;
forming a P-type electrode on the P-type semiconductor layer, and forming an N-type electrode on the N-type semiconductor layer in the groove;
insulating layers are formed in the groove and on the N-type electrode, the P-type semiconductor layer and the P-type electrode;
forming a first conductive hole extending to the N-type electrode and a second conductive hole extending to the P-type electrode on the insulating layer;
forming a first welding point electrically connected with the N-type electrode in the first conductive hole and on the surface of the insulating layer, forming a second welding point electrically connected with the P-type electrode in the second conductive hole and on the surface of the insulating layer, wherein the parts of the first welding point and the second welding point on the surface of the insulating layer are both in a circular truncated cone structure, and the diameter of the cross section of the circular truncated cone structure is gradually reduced along the stacking direction of the chips;
and forming a protective layer on all the areas of the insulating layer except the setting areas of the welding spots, wherein part of the protective layer is also coated on the side walls of the circular truncated cone structures of the first welding spot and the second welding spot.
Optionally, the forming a first pad electrically connected to the N-type electrode in the first conductive hole and on the surface of the insulating layer, and forming a second pad electrically connected to the P-type electrode in the second conductive hole and on the surface of the insulating layer includes:
forming photoresist with a set pattern on the surface of the insulating layer;
forming a first welding point in the first conductive hole and on the insulating layer which is not covered by the photoresist and is arranged around the first conductive hole;
forming a second welding point in the second conductive hole and on the insulating layer which is not covered by the photoresist and is arranged around the second conductive hole;
and removing the photoresist.
Optionally, the forming a first pad in the first conductive hole and on the insulating layer without photoresist coverage around the first conductive hole includes:
depositing Ti, Al, Ti and Au metal layers in sequence in the first conductive hole and on the insulating layer which is not covered by the photoresist around the first conductive hole by adopting a vacuum evaporation metal film plating process and a plating pot with a 50-degree inclination angle to form the first welding point;
and bombarding the first welding point by adopting Ar plasma, so that the included angle between the side wall of the circular truncated cone structure of the first welding point and the bottom surface of the circular truncated cone structure is alpha, and the alpha is more than or equal to 35 degrees and less than 45 degrees.
Optionally, the forming a protective layer on all regions of the insulating layer except for the region where the solder joint is disposed includes:
preparing a first sublayer by adopting a plasma enhanced chemical vapor deposition method, wherein the first sublayer is a silicon oxide layer;
preparing a second sublayer, a third sublayer and a fourth sublayer on the first sublayer in sequence by adopting an atomic layer deposition method, wherein the second sublayer is a silicon oxide layer, the third sublayer is an aluminum oxide layer, and the fourth sublayer is a silicon oxide layer;
and preparing a fifth sublayer on the fourth sublayer by adopting a plasma enhanced chemical vapor deposition method, wherein the fifth sublayer is a silicon oxide layer.
The technical scheme provided by the embodiment of the disclosure has the following beneficial effects:
the part of the welding spot, which is positioned on the surface of the insulating layer, is of a circular truncated cone structure, the side wall of the circular truncated cone structure is an inclined plane, and the angle of the side wall is more gentle. The side walls of the protective layer and the circular truncated cone structure are matched through the inclined planes, the contact area is larger, the tightness is better, even if pollutants such as water vapor exist in the chip when the chip is used, the chip is difficult to permeate from the side walls of the protective layer and the circular truncated cone structure, and therefore the reliability of the light-emitting diode chip can be improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a high-stability light emitting diode chip provided in an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a protective layer according to an embodiment of the disclosure;
FIG. 3 is a schematic diagram of a distribution of solder points provided by an embodiment of the present disclosure;
fig. 4 is a flowchart of a method for manufacturing a high-stability led chip according to an embodiment of the disclosure;
fig. 5 is a flowchart of another method for manufacturing a high-stability led chip according to an embodiment of the disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a high-stability light emitting diode chip provided by an embodiment of the present disclosure, and as shown in fig. 1, the high-stability light emitting diode chip 100 includes a substrate 1, an N-type semiconductor layer 2, an active layer 3, a P-type semiconductor layer 4, an N-type electrode 5, a P-type electrode 6, an insulating layer 7, and a pad. An N-type semiconductor layer 2, an active layer 3, and a P-type semiconductor layer 4 are sequentially stacked on the surface 1a of the substrate 1. The P-type semiconductor layer 4 is provided with a groove extending to the N-type semiconductor layer 2. An N-type electrode 5 is disposed on the N-type semiconductor layer 2 in the recess, and a P-type electrode 6 is disposed on the P-type semiconductor layer 4. An insulating layer 7 is laid in the grooves and on the N-type electrode 5, and on the P-type semiconductor layer 4 and the P-type electrode 6.
The insulating layer 7 is provided with a first conductive hole 7a extending to the N-type electrode 5 and a second conductive hole 7b extending to the P-type electrode 6. The welding spots comprise a first welding spot 91 and a second welding spot 92, the first welding spot 91 is positioned in the first conducting hole 7a and on the surface of the insulating layer 7 and is electrically connected with the corresponding N-type electrode 5. The second pads 92 are located in the second conductive holes 7b and on the surface of the insulating layer 7, and are electrically connected to the corresponding P-type electrodes 6.
The parts of the first welding point 91 and the second welding point 92, which are positioned on the surface of the insulating layer 7, are both in a circular truncated cone structure, and the diameter of the cross section of the circular truncated cone structure is gradually reduced along the stacking direction of the chips.
The high-stability light-emitting diode chip further comprises a protective layer 8, the protective layer 8 is laid on all the regions of the insulating layer 7 except for the setting regions of the welding spots, and part of the protective layer 8 is further coated on the side walls of the circular truncated cone structures of the first welding spot 91 and the second welding spot 92.
According to the embodiment of the disclosure, the part of the welding spot, which is positioned on the surface of the insulating layer, is of the circular truncated cone structure, the side wall of the circular truncated cone structure is an inclined plane, and the angle of the side wall is more gentle. The side walls of the protective layer and the circular truncated cone structure are matched through the inclined planes, the contact area is larger, the tightness is better, even if pollutants such as water vapor exist in the chip when the chip is used, the chip is difficult to permeate from the side walls of the protective layer and the circular truncated cone structure, and therefore the reliability of the light-emitting diode chip can be improved.
Optionally, an included angle between the side wall of the circular truncated cone structure and the bottom surface of the circular truncated cone structure is α, and α is greater than or equal to 35 degrees and less than 45 degrees.
If the included angle between the side wall of the circular truncated cone structure and the bottom surface of the circular truncated cone structure is too large, the effect of improving the tightness between the protective layer and the side wall of the circular truncated cone structure cannot be achieved. If the included angle between the side wall of the circular truncated cone structure and the bottom surface of the circular truncated cone structure is too small, the circular truncated cone structure is difficult to manufacture.
Illustratively, as shown in fig. 1, the portions of the first solder joints 91 on the surface of the insulating layer 7 are all first circular truncated cone structures 91a, and the cross-sectional diameter of each first circular truncated cone structure 91a gradually decreases along the stacking direction of the chips. An included angle between the side wall of the first circular truncated cone structure 91a and the bottom surface of the first circular truncated cone structure 91a is α 1, and α 1 is 35 °.
The parts of the second welding points 92 on the surface of the insulating layer 7 are all second round table structures 92a, and the cross section diameter of each second round table structure 92a is gradually reduced along the stacking direction of the chips. An included angle α 2 between the side wall of the second circular truncated cone structure 92a and the bottom surface of the second circular truncated cone structure 92a is 35 °.
Alternatively, the first pads 91 and the second pads 92 are each a Ti/Al/Ti/Au laminated structure.
The first layer is a Ti layer, the Ti has good adhesion, and the welding spot can be firmly fixed on the surface of the chip. A Ti layer is arranged between the second Al layer and the last Au layer, so that the structural strength inside the welding spot can be guaranteed. The last layer is an Au layer, so that the surface oxidation of the welding spot can be avoided.
Illustratively, the thickness of the first Ti layer of the first pad 91 and the second pad 92 is 20nm, the thickness of the second Al layer is 1000nm, the thickness of the third Ti layer is 100nm, and the thickness of the fourth Au layer is 600 nm.
Fig. 2 is a schematic structural diagram of a protective layer provided in an embodiment of the present disclosure, and as shown in fig. 2, the protective layer 8 includes a first sub-layer 81, a second sub-layer 82, a third sub-layer 83, a fourth sub-layer 84, and a fifth sub-layer 85, which are sequentially stacked. The first sublayer 81 and the fifth sublayer 85 are silicon oxide layers prepared by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, and the second sublayer 82 and the fourth sublayer 84 are silicon oxide layers prepared by an Atomic Layer Deposition (ALD) method. The third sub-layer 83 is an aluminum oxide layer prepared by an ALD method.
In the protective layer with the above structure, silicon oxide can be firmly adhered to the underlying semiconductor layer, and aluminum oxide (i.e., the third sub-layer 83) formed by the ALD method can play a good role in blocking, so that the solder joint can be covered tightly, and the invasion of water vapor can be further prevented.
Optionally, the thicknesses of the first sublayer 81 and the fifth sublayer 85 are the same, the thicknesses of the second sublayer 82 and the fourth sublayer 84 are the same, the thickness of the first sublayer 81 is greater than that of the second sublayer 82, and the thickness of the second sublayer 82 is greater than that of the third sublayer 83.
Illustratively, the first sublayer 81 and the fifth sublayer 85 have a thickness of 200nm, the second sublayer 82 and the fourth sublayer 84 have a thickness of 30nm, and the third sublayer 83 has a thickness of 20 nm.
Optionally, the total thickness of the protective layer 8 is 400-1000 nm.
In one implementation of the disclosed embodiment, the high-stability led chip may be a gan-based blue-green chip. In this case, the substrate may be a sapphire substrate, and the N-type semiconductor layer may be an N-type doped GaN layer having a thickness of 4000 nm. The active layer can comprise a plurality of InGaN well layers and GaN barrier layers which alternately grow in a period, the thickness of each well layer is 3-5 nm, and the thickness of each barrier layer is 7-8 nm. The P-type semiconductor layer may be a GaN layer doped with Mg and has a thickness of 5000 nm.
In another implementation manner of the embodiment of the present disclosure, the high-stability light emitting diode chip may be an aluminum gallium indium phosphide-based red light chip. In this case, the substrate may be a sapphire substrate, and the N-type semiconductor layer may be an N-doped AlGaInP layer having a thickness of 4000 nm. The active layer may include a plurality of well layers and barrier layers alternately grown in a plurality of periods, and the well layer may be AlxGa1-xAn InP layer and a barrier layer of AlyGa1-yAnd the InP layer, x is less than y, the thickness of the well layer is 3-5 nm, and the thickness of the barrier layer is 7-8 nm. The P-type semiconductor layer is a P-type doped GaP layer with the thickness of 5000 nm.
Alternatively, the N-type electrode 5 may be an AuGe layer and the P-type electrode 6 may be an AuBe layer.
Alternatively, the insulating layer 7 includes a passivation layer and a distributed bragg reflector layer, which are sequentially stacked.
Wherein the passivation layer is a silicon oxide layer with a thickness of 400-600 nm, such as 500 nm. The silicon oxide has higher hardness, and can effectively protect the chip. The distributed Bragg reflection layer comprises silicon oxide layers and titanium oxide layers which are alternately stacked, and the number of the silicon oxide layers and the titanium oxide layers is 30-40, such as 36. The reflection wavelength may be set at 620 nm.
Fig. 3 is a schematic diagram illustrating a distribution of solder joints provided by an embodiment of the present disclosure, and referring to fig. 3, a first solder joint 91 and a second solder joint 92 are disposed on an insulating layer 7 at an interval. The sizes of the arrangement areas of the first welding spot 91 and the second welding spot 92 on the insulating layer 7 are the same, and the orthographic projections of the first welding spot 91 and the second welding spot 92 on the insulating layer 7 are not overlapped, so that stable electric connection with a circuit board is conveniently formed.
The embodiment of the disclosure provides a method for manufacturing a high-stability light emitting diode chip, which is suitable for manufacturing the high-stability light emitting diode chip shown in fig. 1. Fig. 4 is a flowchart of a method for manufacturing a high-stability light emitting diode chip according to an embodiment of the present disclosure, and referring to fig. 4, the method for manufacturing includes:
Wherein the substrate may be a sapphire substrate.
Optionally, this step 402 may include:
an N-type semiconductor layer, an active layer and a P-type semiconductor layer are sequentially grown on a substrate by using a Metal-organic Chemical Vapor Deposition (MOCVD) technology.
And 403, forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer.
Optionally, this step 403 may include:
forming a patterned photoresist on the P-type semiconductor layer by adopting a photoetching technology;
forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer by adopting an Inductively Coupled Plasma etching (ICP); wherein, the etching depth can be 5 um.
Step 404 forms a P-type electrode on the P-type semiconductor layer and an N-type electrode on the N-type semiconductor layer in the recess.
Optionally, step 404 comprises:
forming a negative photoresist on the P-type semiconductor layer by using a photoetching technology;
forming an electrode material on the negative photoresist and the P-type semiconductor layer by adopting an evaporation technology;
and removing the negative photoresist and the electrode material on the negative photoresist, and forming a P-type electrode by the electrode material on the P-type semiconductor layer.
Optionally, the P-type electrode is an AuBe layer.
Optionally, step 404 comprises:
forming a negative photoresist on the N-type semiconductor layer in the groove by adopting a photoetching technology;
forming an electrode material on the negative photoresist and the N-type semiconductor layer in the groove by adopting an evaporation technology;
and removing the negative photoresist and the electrode material on the negative photoresist, and forming an N-type electrode by the electrode material on the N-type semiconductor layer in the groove.
Optionally, the N-type electrode is an AuGe layer.
In an embodiment of the present disclosure, the insulating layer includes a passivation layer and a distributed bragg reflector layer that are sequentially stacked. Wherein the passivation layer is a silicon oxide layer with a thickness of 400-600 nm, such as 500 nm. The silicon oxide has higher hardness, and can effectively protect the chip. The distributed Bragg reflection layer comprises silicon oxide layers and titanium oxide layers which are alternately stacked, and the number of the silicon oxide layers and the titanium oxide layers is 30-40, such as 36.
Illustratively, the passivation layer may be formed using a PECVD (Plasma Enhanced Chemical Vapor Deposition) method.
Illustratively, the DBR layer may be formed using an ion source assisted evaporation technique. Wherein, the DBR layer comprises silicon oxide layer and titanium oxide layer which are alternately laminated. The number of cycles of the silicon oxide layer and the titanium oxide layer may be 32.
Alternatively, a dry etching technique may be used to respectively open a first conductive hole extending to the N-type electrode and a second conductive hole extending to the P-type electrode on the insulating layer.
The parts of the first welding points and the second welding points, which are positioned on the surface of the insulating layer, are both of circular truncated cone structures, and the diameters of the cross sections of the circular truncated cone structures are gradually reduced along the stacking direction of the chips.
And 408, forming a protective layer on all the areas of the insulating layer except the setting areas of the welding points, so that part of the protective layer is coated on the side walls of the circular truncated cone structures of the first welding points and the second welding points.
According to the embodiment of the disclosure, the part of the welding spot, which is positioned on the surface of the insulating layer, is of the circular truncated cone structure, the side wall of the circular truncated cone structure is an inclined plane, and the angle of the side wall is more gentle. The side walls of the protective layer and the circular truncated cone structure are matched through the inclined planes, the contact area is larger, the tightness is better, even if pollutants such as water vapor exist in the chip when the chip is used, the chip is difficult to permeate from the side walls of the protective layer and the circular truncated cone structure, and therefore the reliability of the light-emitting diode chip can be improved.
The embodiment of the present disclosure provides another method for manufacturing a high-stability led chip, which is suitable for manufacturing the high-stability led chip shown in fig. 1. Fig. 5 is a flowchart of another method for manufacturing a high-stability light emitting diode chip according to an embodiment of the present disclosure, and referring to fig. 5, the method includes:
Wherein the substrate may be a sapphire substrate.
Exemplarily, the substrate surface after the patterning treatment is provided with a plurality of conical protrusions which are uniformly distributed at intervals, the diameter of the bottom of each conical protrusion is 1.3-1.7 um, and the height of each conical protrusion is 0.8-1.2 um.
In the practice of the present disclosure, step 502 may be an optional step.
Alternatively, step 503 may be the same as step 402 and will not be described in detail herein.
And step 504, forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer.
Alternatively, step 504 may be the same as step 403 and will not be described in detail herein.
And 505, forming a P-type electrode on the P-type semiconductor layer, and forming an N-type electrode on the N-type semiconductor layer in the groove.
Alternatively, step 505 may be the same as step 404 and will not be described in detail herein.
Alternatively, this step 506 may be the same as step 405 and will not be described in detail herein.
Alternatively, this step 507 may be the same as step 406 and will not be described in detail here.
And step 508, forming a first welding point electrically connected with the N-type electrode in the first conductive hole and on the surface of the insulating layer, and forming a second welding point electrically connected with the P-type electrode in the second conductive hole and on the surface of the insulating layer.
The parts of the first welding points and the second welding points, which are positioned on the surface of the insulating layer, are both of circular truncated cone structures, and the diameters of the cross sections of the circular truncated cone structures are gradually reduced along the stacking direction of the chips.
Illustratively, step 508 may include:
firstly, photoresist with a set pattern is formed on the surface of an insulating layer.
And secondly, forming a first welding point in the first conductive hole and on the insulating layer which is not covered by the photoresist and is arranged around the first conductive hole.
In an embodiment of the present disclosure, the second step may include:
depositing Ti, Al, Ti and Au metal layers in sequence in the first conductive hole and on the insulating layer which is not covered by the photoresist around the first conductive hole by adopting a vacuum evaporation metal film plating process and a plating pot with an inclination angle of 50 degrees to form a first welding point;
ar plasma is adopted to bombard the first welding point, so that the included angle between the side wall of the circular truncated cone structure of the first welding point and the bottom surface of the circular truncated cone structure is alpha, and alpha is more than or equal to 35 degrees and less than 45 degrees.
And thirdly, forming a second welding point in the second conductive hole and on the insulating layer which is not covered by the photoresist and is arranged around the second conductive hole.
Illustratively, the process of forming the second solder joint in the third step is the same as the process of forming the first solder joint in the second step. The embodiments of the present disclosure are not described herein in detail.
And fourthly, removing the photoresist.
Optionally, the first solder joint and the second solder joint are both a Ti/Al/Ti/Au stacked structure.
Illustratively, the thickness of the first Ti layer in the first solder joint and the second solder joint is 20nm, the thickness of the second Al layer is 1000nm, the thickness of the third Ti layer is 100nm, and the thickness of the fourth Au layer is 600 nm.
Illustratively, step 509 may include:
preparing a first sublayer by adopting a PECVD method, wherein the first sublayer is a silicon oxide layer;
preparing a second sublayer on the first sublayer by adopting an ALD method, wherein the second sublayer is a silicon oxide layer;
preparing a third sublayer on the second sublayer by adopting an ALD method, wherein the third sublayer is an aluminum oxide layer;
preparing a fourth sublayer on the third sublayer by adopting an ALD method, wherein the fourth sublayer is a silicon oxide layer;
and preparing a fifth sublayer on the fourth sublayer by adopting a PECVD method, wherein the fifth sublayer is a silicon oxide layer.
Optionally, the thicknesses of the first sublayer and the fifth sublayer are the same, the thicknesses of the second sublayer and the fourth sublayer are the same, the thickness of the first sublayer is greater than that of the second sublayer, and the thickness of the second sublayer is greater than that of the third sublayer.
Illustratively, the first and fifth sublayers have a thickness of 200nm, the second and fourth sublayers have a thickness of 30nm, and the third sublayer has a thickness of 20 nm.
Optionally, the total thickness of the protective layer is 400-1000 nm.
In the embodiment of the present disclosure, the final thickness of the thinned substrate is about 60-120 um, for example, 80 um. And the loss of light in the substrate is reduced under the condition of ensuring the supporting strength.
Optionally, the manufacturing method may further include:
and carrying out invisible cutting and scratching on the substrate.
In practical application, the cutting can be performed by scratching and splitting by using an invisible cutting technology, so that the brightness is improved. During invisible cutting, laser photons can be injected from the back surface of the chip, and the laser wavelength can be 1024 nm.
According to the embodiment of the disclosure, the part of the welding spot, which is positioned on the surface of the insulating layer, is of the circular truncated cone structure, the side wall of the circular truncated cone structure is an inclined plane, and the angle of the side wall is more gentle. The side walls of the protective layer and the circular truncated cone structure are matched through the inclined planes, the contact area is larger, the tightness is better, even if pollutants such as water vapor exist in the chip when the chip is used, the chip is difficult to permeate from the side walls of the protective layer and the circular truncated cone structure, and therefore the reliability of the light-emitting diode chip can be improved.
The above description is intended to be exemplary only and not to limit the present disclosure, and any modification, equivalent replacement, or improvement made without departing from the spirit and scope of the present disclosure is to be considered as the same as the present disclosure.
Claims (10)
1. A high-stability light-emitting diode chip comprises a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, an N-type electrode, a P-type electrode, an insulating layer and welding spots, wherein the N-type semiconductor layer is arranged on the substrate; the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially laminated on the surface of the substrate; a groove extending to the N-type semiconductor layer is formed in the P-type semiconductor layer, the N-type electrode is arranged on the N-type semiconductor layer in the groove, and the P-type electrode is arranged on the P-type semiconductor layer; the insulating layer is laid in the groove, on the N-type electrode, on the P-type semiconductor layer and the P-type electrode, and is characterized in that:
the insulating layer is provided with a first conductive hole extending to the N-type electrode and a second conductive hole extending to the P-type electrode, the welding spots comprise a first welding spot and a second welding spot, the first welding spot is positioned in the first conductive hole and on the surface of the insulating layer and is electrically connected with the corresponding N-type electrode, and the second welding spot is positioned in the second conductive hole and on the surface of the insulating layer and is electrically connected with the corresponding P-type electrode; the parts, located on the surface of the insulating layer, of the first welding points and the second welding points are both in a circular truncated cone structure, and the diameter of the cross section of the circular truncated cone structure is gradually reduced along the stacking direction of the chips;
the high-stability light-emitting diode chip further comprises a protective layer, wherein the protective layer is laid on all regions of the insulating layer except the setting regions of the welding spots, and part of the protective layer is further coated on the side walls of the circular truncated cone structures of the first welding spot and the second welding spot.
2. The high-stability light-emitting diode chip as claimed in claim 1, wherein an included angle between the side wall of the circular truncated cone structure and the bottom surface of the circular truncated cone structure is α, α is greater than or equal to 35 ° and less than 45 °.
3. The high stability light emitting diode chip as claimed in claim 1, wherein the first solder joint and the second solder joint are both Ti/Al/Ti/Au stacked structures.
4. The high-stability light-emitting diode chip as claimed in claim 1, wherein the protective layer includes a first sub-layer, a second sub-layer, a third sub-layer, a fourth sub-layer and a fifth sub-layer stacked in sequence, the first sub-layer and the fifth sub-layer are both silicon oxide layers prepared by a vapor deposition method of plasma enhanced chemistry, the second sub-layer and the fourth sub-layer are both silicon oxide layers prepared by an atomic layer deposition method, and the third sub-layer is an aluminum oxide layer prepared by an atomic layer deposition method.
5. The high stability light emitting diode chip as claimed in claim 4, wherein the first sub-layer and the fifth sub-layer have the same thickness, the second sub-layer and the fourth sub-layer have the same thickness, the thickness of the first sub-layer is greater than that of the second sub-layer, and the thickness of the second sub-layer is greater than that of the third sub-layer.
6. The highly stable light emitting diode chip as claimed in claim 5, wherein the total thickness of the protection layer is 400-1000 nm.
7. A method for manufacturing a high-stability light emitting diode chip is characterized by comprising the following steps:
providing a substrate;
growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the substrate in sequence;
forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer;
forming a P-type electrode on the P-type semiconductor layer, and forming an N-type electrode on the N-type semiconductor layer in the groove;
insulating layers are formed in the groove and on the N-type electrode, the P-type semiconductor layer and the P-type electrode;
forming a first conductive hole extending to the N-type electrode and a second conductive hole extending to the P-type electrode on the insulating layer;
forming a first welding point electrically connected with the N-type electrode in the first conductive hole and on the surface of the insulating layer, forming a second welding point electrically connected with the P-type electrode in the second conductive hole and on the surface of the insulating layer, wherein the parts of the first welding point and the second welding point on the surface of the insulating layer are both in a circular truncated cone structure, and the diameter of the cross section of the circular truncated cone structure is gradually reduced along the stacking direction of the chips;
and forming a protective layer on all the areas of the insulating layer except the setting areas of the welding spots, wherein part of the protective layer is also coated on the side walls of the circular truncated cone structures of the first welding spot and the second welding spot.
8. The method of claim 7, wherein forming a first pad in the first conductive hole and on the surface of the insulating layer to be electrically connected to the N-type electrode and forming a second pad in the second conductive hole and on the surface of the insulating layer to be electrically connected to the P-type electrode comprises:
forming photoresist with a set pattern on the surface of the insulating layer;
forming a first welding point in the first conductive hole and on the insulating layer which is not covered by the photoresist and is arranged around the first conductive hole;
forming a second welding point in the second conductive hole and on the insulating layer which is not covered by the photoresist and is arranged around the second conductive hole;
and removing the photoresist.
9. The method of manufacturing according to claim 8, wherein the forming of the first pads in the first conductive holes and on the insulating layer not covered by the photoresist around the first conductive holes comprises:
depositing Ti, Al, Ti and Au metal layers in sequence in the first conductive hole and on the insulating layer which is not covered by the photoresist around the first conductive hole by adopting a vacuum evaporation metal film plating process and a plating pot with a 50-degree inclination angle to form the first welding point;
and bombarding the first welding point by adopting Ar plasma, so that the included angle between the side wall of the circular truncated cone structure of the first welding point and the bottom surface of the circular truncated cone structure is alpha, and the alpha is more than or equal to 35 degrees and less than 45 degrees.
10. The manufacturing method according to claim 7, wherein the forming of the protective layer on all regions of the insulating layer except for the region where the solder joint is provided includes:
preparing a first sublayer by adopting a plasma enhanced chemical vapor deposition method, wherein the first sublayer is a silicon oxide layer;
preparing a second sublayer, a third sublayer and a fourth sublayer on the first sublayer in sequence by adopting an atomic layer deposition method, wherein the second sublayer is a silicon oxide layer, the third sublayer is an aluminum oxide layer, and the fourth sublayer is a silicon oxide layer;
and preparing a fifth sublayer on the fourth sublayer by adopting a plasma enhanced chemical vapor deposition method, wherein the fifth sublayer is a silicon oxide layer.
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