CN112133804B - Light emitting diode chip and manufacturing method thereof - Google Patents
Light emitting diode chip and manufacturing method thereof Download PDFInfo
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- CN112133804B CN112133804B CN202010771139.1A CN202010771139A CN112133804B CN 112133804 B CN112133804 B CN 112133804B CN 202010771139 A CN202010771139 A CN 202010771139A CN 112133804 B CN112133804 B CN 112133804B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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Abstract
The disclosure provides a light emitting diode chip and a manufacturing method thereof, and belongs to the technical field of semiconductors. The light emitting diode chip comprises a transparent substrate, an epitaxial layer and a metal electrode; the epitaxial layer covers the first surface of the transparent substrate; the second surface of the epitaxial layer comprises a convex part, a concave part and a connecting part, the second surface is opposite to the third surface of the epitaxial layer, and the third surface is in contact with the first surface; the convex part and the concave part are planes which are parallel to each other, and the distance between the convex part and the first surface is greater than the distance between the concave part and the first surface; the convex part and the concave part are connected together through a connecting part, and the included angles between tangent planes of all points on the connecting part and the convex part are the same; the metal electrode at least covers the convex part and the connecting part, and metal atoms in the metal electrode are diffused into the epitaxial layer to form ohmic contact. The present disclosure can avoid a voltage rise of a chip in the case of a reduction in chip size.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a light emitting diode chip and a method for manufacturing the same.
Background
An LED (Light Emitting Diode) emits Light by energy released by recombination of electrons and holes. By adopting different semiconductor materials and structures, the LED can cover the full color range from ultraviolet to infrared, and can be widely applied to the fields of display, decoration, communication and the like in economic life.
The chip is a core device of the LED and comprises a forward mounting structure, a flip mounting structure and a vertical mounting structure. In the related art, the LED chip of the flip chip structure includes a transparent substrate, a first type semiconductor layer, an active layer, a second type semiconductor layer, a first type electrode, and a second type electrode. The first type semiconductor layer, the active layer and the second type semiconductor layer are sequentially stacked on the transparent substrate, and the second type semiconductor layer is provided with a groove extending to the first type semiconductor layer. The first type electrode is arranged on the first type semiconductor layer in the groove, and the second type electrode is arranged on the second type semiconductor layer. The first type electrode and the second type electrode are respectively fixed on the circuit board, and current is injected into the chip through the first type electrode and the second type electrode, so that carriers provided by the first type semiconductor layer and the second type semiconductor layer are injected into the active layer to carry out compound light emission.
Along with the continuous improvement of the display requirements of people, the size of a chip is continuously reduced, the voltage of the chip is increased, the chip is easy to lose efficacy, the service life is shortened, and the popularization and the application of the chip are influenced.
Disclosure of Invention
The embodiment of the disclosure provides a light emitting diode chip and a manufacturing method thereof, which can avoid the voltage rise of the chip under the condition of chip size reduction, so that the service life of the chip meets the application requirement. The technical scheme is as follows:
in one aspect, an embodiment of the present disclosure provides a light emitting diode chip, where the light emitting diode chip includes a transparent substrate, an epitaxial layer, and a metal electrode; the epitaxial layer covers the first surface of the transparent substrate; the second surface of the epitaxial layer comprises a convex part, a concave part and a connecting part, the second surface is opposite to a third surface of the epitaxial layer, and the third surface is in contact with the first surface; the convex part and the concave part are planes parallel to each other, and the distance between the convex part and the first surface is greater than the distance between the concave part and the first surface; the convex part and the concave part are connected together through the connecting part, and the included angles between tangent planes of all points on the connecting part and the convex part are the same; the metal electrode at least covers the convex part and the connecting part, and metal atoms in the metal electrode are diffused into the epitaxial layer to form ohmic contact.
Optionally, an included angle between a tangent plane of a point on the connecting portion and the convex portion is 165 ° to 175 °.
Optionally, the number of the connecting portions is at least two, at least two of the connecting portions are sequentially arranged in the direction from the protruding portion to the recessed portion, and the included angle between the tangent plane of the upper point of at least two of the connecting portions and the protruding portion is gradually reduced in the direction from the protruding portion to the recessed portion.
Optionally, the protrusion is polygonal.
Optionally, the metal electrode further covers a region where the recess is connected to the connection portion.
Optionally, the epitaxial layer includes a first type semiconductor layer, an active layer and a second type semiconductor layer stacked on the first surface in sequence, a groove extending from the second type semiconductor layer to the first type semiconductor layer is formed in the epitaxial layer, and an isolation groove extending from the second type semiconductor layer to the transparent substrate is formed outside the epitaxial layer; the groove divides the second type semiconductor layer and the active layer into a first part and a second part which are isolated from each other, the first part is positioned in the groove, and the second part is positioned outside the groove; the metal electrode comprises a first type electrode and a second type electrode, the first type electrode is arranged on the first type semiconductor layer, and the second type electrode is arranged on the second type semiconductor layer of the first part.
Optionally, a projection of the second portion on the first surface includes an annular region and two protruding regions, the two protruding regions are respectively connected to an inner ring of the annular region, the two protruding regions are located on two opposite sides of the first-type electrode, and a central connecting line of the two protruding regions is perpendicular to a central connecting line of the first-type electrode and the second-type electrode.
On the other hand, the embodiment of the present disclosure provides a manufacturing method of a light emitting diode chip, where the manufacturing method includes:
providing a transparent substrate with a first surface covered with an epitaxial layer;
forming a convex portion, a concave portion and a connecting portion on a second surface of the epitaxial layer; wherein the second surface is opposite a third surface of the epitaxial layer, the third surface being in contact with the first surface; the convex part and the concave part are planes parallel to each other, and the distance between the convex part and the first surface is greater than the distance between the concave part and the first surface; the convex part and the concave part are connected together through the connecting part, and the included angles between tangent planes of all points on the connecting part and the convex part are the same;
and forming a metal electrode at least on the convex part and the connecting part, wherein metal atoms in the metal electrode are diffused into the epitaxial layer to form ohmic contact.
Optionally, the forming of the protrusion, the recess, and the connection portion on the second surface of the epitaxial layer includes:
forming a patterned photoresist on the second surface by adopting a photoetching technology;
dry etching the epitaxial layer to form a convex part, a concave part and a connecting part on the second surface; wherein the etching rate of the epitaxial layer is less than that of the patterned photoresist;
and removing the patterned photoresist.
Optionally, the epitaxial layer includes a first type semiconductor layer, an active layer, and a second type semiconductor layer stacked in this order on the first surface;
the manufacturing method further comprises the following steps:
forming a groove extending from the second type semiconductor layer to the first type semiconductor layer in the epitaxial layer, and forming an isolation groove extending from the second type semiconductor layer to the transparent substrate outside the epitaxial layer; the groove divides the second type semiconductor layer and the active layer into a first part and a second part which are isolated from each other, the first part is positioned in the groove, and the second part is positioned outside the groove; the metal electrode comprises a first type electrode and a second type electrode, the first type electrode is arranged on the first type semiconductor layer, and the second type electrode is arranged on the second type semiconductor layer of the first part.
The technical scheme provided by the embodiment of the disclosure has the following beneficial effects:
become including bellying, depressed part and connecting portion through the surface with epitaxial layer dorsad transparent substrate, bellying and depressed part be parallel to each other and with the transparent substrate between the plane that the distance is different, bellying and depressed part link together through connecting portion, the tangent plane of each point on the connecting portion is the same with the contained angle between the bellying to form the crystal face of two kinds of different crystal orientations of connecting portion and bellying. The metal electrode at least covers the protruding portion and the connecting portion, the possibility that the metal electrode covers the (100) crystal face of the epitaxial layer can be increased, the deviation between the covering surface of the metal electrode and the (100) crystal face of the epitaxial layer can be reduced, the metal atoms in the metal electrode are promoted to be diffused into the epitaxial layer by utilizing the reduction of the atomic density of the covering surface of the metal electrode, the number of the metal atoms diffused into the epitaxial layer by the metal electrode is increased, the influence of a contact potential barrier between the metal electrode and the epitaxial layer is reduced, the voltage of a chip is reduced, and the service life of the chip is prolonged.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a light emitting diode chip provided in an embodiment of the present disclosure;
fig. 2 is a top view of an epitaxial layer provided by embodiments of the present disclosure;
fig. 3 is a side view of a light emitting diode chip provided by an embodiment of the present disclosure;
fig. 4 is a top view of a light emitting diode chip provided by an embodiment of the present disclosure;
fig. 5 is a flowchart of a method for manufacturing a light emitting diode chip according to an embodiment of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
The LED chip comprises a forward mounting structure, a reverse mounting structure and a vertical structure. The LED chip with the flip structure comprises a transparent substrate, a first type semiconductor layer, an active layer, a second type semiconductor layer, a first type electrode and a second type electrode. The first type semiconductor layer, the active layer and the second type semiconductor layer are sequentially stacked on the transparent substrate, and the second type semiconductor layer is provided with a groove extending to the first type semiconductor layer. The first type electrode is arranged on the first type semiconductor layer in the groove, and the second type electrode is arranged on the second type semiconductor layer. The first type electrode and the second type electrode are respectively fixed on the circuit board, and light emitted by the active layer is emitted from the side where the transparent substrate is located.
The first type semiconductor layer and the second type semiconductor layer are made of semiconductor layer materials, the first type electrode and the second type electrode are made of metal materials, contact barriers exist at the contact position of the first type electrode and the first type semiconductor layer and the contact position of the second type electrode and the second type semiconductor layer, and ohmic contact needs to be formed between the first type electrode and the first type semiconductor layer and between the second type electrode and the second type semiconductor layer.
For the red LED chip, ohmic contact is formed by the diffusion of metal atoms in the first type electrode into the first type semiconductor layer and the diffusion of metal atoms in the second type electrode into the second type semiconductor layer. Along with the continuous reduction of the size of the chip, the setting area of a first type electrode on the first type semiconductor layer and the setting area of a second type electrode on the second type semiconductor layer are reduced, the number of metal atoms diffused to the first type semiconductor layer by the first type electrode and the number of metal atoms diffused to the second type semiconductor layer by the second type electrode are correspondingly reduced, the influence of a contact barrier between the first type electrode and the first type semiconductor layer and the influence of the contact barrier between the second type electrode and the second type semiconductor layer are increased, the voltage of the chip is increased, the chip is easy to lose efficacy, the service life is shortened, and the popularization and the application of the chip are not facilitated.
Based on the above situation, the embodiment of the present disclosure provides a light emitting diode chip. Fig. 1 is a schematic structural diagram of a light emitting diode chip according to an embodiment of the present disclosure. Referring to fig. 1, the light emitting diode chip includes a transparent substrate 10, an epitaxial layer 20, and a metal electrode 30. The epitaxial layer 20 is coated on the first surface of the transparent substrate 10. A second surface of the epitaxial layer 20, which is opposite to a third surface of the epitaxial layer 20, the third surface being in contact with the first surface, includes the protrusions 21, the recesses 22, and the connection portions 23. The protruding portion 21 and the recessed portion 22 are planes parallel to each other, and the distance between the protruding portion 21 and the first surface is larger than the distance between the recessed portion 22 and the first surface. The convex part 21 and the concave part 22 are connected together through a connecting part 23, and the included angle between the tangent plane of each point on the connecting part 23 and the convex part 21 is the same. The metal electrode 30 covers at least the protruding portion 21 and the connection portion 23, and metal atoms in the metal electrode 30 diffuse into the epitaxial layer 20 to form ohmic contact.
The epitaxial layer 20 theoretically covers the (100) crystal plane of the transparent substrate 10, and the metal electrode 30 covers the (100) crystal plane of the epitaxial layer 20 at this time. Since the lowest atomic density of the (100) crystal plane is most favorable for the metal atoms in the metal electrode 30 to diffuse into the epitaxial layer 20, the number of the metal atoms diffused into the epitaxial layer 20 by the metal electrode 30 is maximized, and the ohmic contact formed between the metal electrode 30 and the epitaxial layer 20 is better. However, the transparent substrate 10 cannot ensure that the surface covered by the epitaxial layer 20 is the (100) crystal plane of the transparent substrate 10 in the actual processing process, and there is usually a certain deviation between the two.
The surface of the epitaxial layer back to the transparent substrate is changed to include the protruding portion, the recessed portion and the connecting portion, the protruding portion and the recessed portion are parallel to each other and planes with different distances from the transparent substrate, the protruding portion and the recessed portion are connected together through the connecting portion, included angles between a tangent plane of each point on the connecting portion and the protruding portion are the same, and therefore crystal faces of the connecting portion and the protruding portion in two different crystal directions are formed. The metal electrode at least covers the protruding portion and the connecting portion, the possibility that the metal electrode covers the (100) crystal face of the epitaxial layer can be increased, the deviation between the covering surface of the metal electrode and the (100) crystal face of the epitaxial layer can be reduced, the metal atoms in the metal electrode are promoted to be diffused into the epitaxial layer by utilizing the reduction of the atomic density of the covering surface of the metal electrode, the number of the metal atoms diffused into the epitaxial layer by the metal electrode is increased, the influence of a contact potential barrier between the metal electrode and the epitaxial layer is reduced, the voltage of a chip is reduced, and the service life of the chip is prolonged.
Alternatively, as shown in fig. 1, the included angle α between the tangent plane of the point on the connecting portion 23 and the boss portion 21 is 165 ° to 175 °.
An included angle alpha between a tangent plane of a point on the connecting portion 23 and the boss portion 21 is 165-175 degrees, a difference between a crystal direction of a crystal face formed by the connecting portion 23 and a crystal direction of a crystal face formed by the boss portion 21 is small, a deviation between a setting surface of the metal electrode 30 and a (100) crystal face can be effectively compensated, and the metal electrode 30 is favorably formed by the (100) crystal face.
For example, the difference between the processing surface of the transparent substrate 10 and the (100) crystal plane of the transparent substrate 10 is 10 °, that is, the difference between the convex portion 21 and the concave portion 22 and the (100) crystal plane is 10 °, and if the angle α between the tangent plane to the point on the connecting portion 23 and the convex portion 21 is 170 °, the connecting portion 23 is exactly the (100) crystal plane.
Alternatively, as shown in fig. 1, the number of the connecting portions 23 is at least two, the at least two connecting portions 23 are sequentially arranged in a direction from the convex portion 21 to the concave portion 22, and an included angle α between a tangent plane of points on the at least two connecting portions 23 and the convex portion 21 decreases one by one in the direction from the convex portion 21 to the concave portion 22.
The number of the connecting portions 23 is at least two, and the included angle between the tangent plane of the points on the at least two connecting portions 23 and the protruding portion 21 is gradually reduced along the direction from the protruding portion 21 to the recessed portion 22, so that the possibility that the metal electrode covers the (100) crystal face of the epitaxial layer can be effectively increased, and the formation of the (100) crystal face is facilitated, and the metal electrode 30 is arranged. Moreover, the inclined transition between the connecting portion 23 and the protruding portion 21 is more gradual, which is beneficial to the stable arrangement of the metal electrode 30.
For example, the difference between the processing surface of the transparent substrate 10 and the (100) crystal plane of the transparent substrate 10 is 10 °, that is, the difference between the convex portion 21 and the concave portion 22 and the (100) crystal plane is 10 °, and if the included angle α between the tangent plane to the points on the two connection portions 23 and the convex portion 21 is 165 ° and 170 ° in order in the direction from the convex portion 21 to the concave portion 22, one of the connection portions 23 is exactly the (100) crystal plane.
Fig. 2 is a top view of an epitaxial layer provided by an embodiment of the present disclosure. Referring to fig. 2, optionally, the boss 21 is polygonal.
The protruding portion 21 is polygonal, and the connecting portion 23 can be formed by connecting a plurality of planes end to end, so that the connecting portion 23 can be formed conveniently.
Illustratively, as shown in fig. 2, the boss 21 is hexagonal or octagonal.
Alternatively, the boss 21 may be circular.
Alternatively, as shown in fig. 1, the metal electrode 30 is also covered on a region where the recess 22 and the connection portion 23 are connected.
The metal electrode 30 also covers the region where the recess 22 is connected to the connection portion 23, which facilitates the metal electrode 30 to be stably disposed on the epitaxial layer 20.
Fig. 3 is a side view of a light emitting diode chip provided by an embodiment of the present disclosure. Referring to fig. 3, alternatively, the epitaxial layer 20 includes a first type semiconductor layer 24, an active layer 25, and a second type semiconductor layer 26 sequentially stacked on the first surface, the epitaxial layer 20 has a groove 41 therein extending from the second type semiconductor layer 26 to the first type semiconductor layer 24, and the epitaxial layer 20 has an isolation groove 42 outside thereof extending from the second type semiconductor layer 26 to the transparent substrate 10. The recess 41 divides the second-type semiconductor layer 26 and the active layer 25 into a first portion 27 and a second portion 28 isolated from each other, the first portion 27 being located inside the recess 41, and the second portion 28 being located outside the recess 41. The metal electrode 30 includes a first-type electrode 31 and a second-type electrode 32, the first-type electrode 31 being disposed on the first-type semiconductor layer 24, the second-type electrode 32 being disposed on the second-type semiconductor layer 26 of the first portion 27.
The embodiment of the disclosure divides the second type semiconductor layer 26 and the active layer 25 into the first part 27 and the second part 28 which are isolated from each other by arranging the groove 41 which extends from the second type semiconductor layer 26 to the first type semiconductor layer 24 in the epitaxial layer 20, and arranging the isolation groove 42 which extends from the second type semiconductor layer 26 to the transparent substrate 10 outside the epitaxial layer 20, wherein the first part 27 can emit light after being electrified, and the second part 28 can play an isolation role in the scribing of the isolation groove 42, so that the chip leakage caused by the damage to the first part 27 in the scribing process is avoided. And because the second part 28 can protect the first part 27, the second part 28 can be realized by reducing the isolation groove 42, the light-emitting area of the active layer 25 is not influenced, meanwhile, the mesa area of the chip is increased, the chip is conveniently fixed on the adhesive film for transfer, and the problem that the chip is inclined on the adhesive film along with the reduction of the size is solved.
Fig. 4 is a top view of a light emitting diode chip provided in an embodiment of the present disclosure. Referring to fig. 4, optionally, the projection of the second portion 28 on the first surface includes an annular region 281 and two protruding regions 282, the two protruding regions 282 are respectively connected to the inner ring of the annular region 281, the two protruding regions 282 are located at two opposite sides of the first-type electrode 31, and a central connecting line of the two protruding regions 282 is perpendicular to a central connecting line of the first-type electrode 31 and the second-type electrode 32.
The first portion 27 is disposed in the region on the opposite sides of the first-type electrode 31 in the related art, and the embodiment of the disclosure changes the first portion 27 into the second portion 28 (i.e., two protruding regions 282), so that the mesa area at the edge of the chip can be increased, the chip can be fixed on the adhesive film for transfer, and the problem that the chip tilts on the adhesive film along with the reduction of the size can be effectively solved. And the regions on opposite sides of the first-type electrode 31 emit less light, and the first portion 27 is provided instead of the second portion 28, with a negligible effect on the emission luminance.
Illustratively, as shown in FIG. 4, the annular region 281 is a square ring and the two protruding regions 282 are squares.
Illustratively, the material of the transparent substrate 10 is one of sapphire, gallium phosphide, silicon carbide, aluminum oxide, zinc oxide, silicon nitride, and glass. The sapphire substrate has high light transmittance, high material hardness and stable chemical properties.
The first type semiconductor layer 24 includes a Mg-doped GaP layer and a Mg-doped AlInP layer, which are sequentially stacked, the active layer 25 is an undoped AlGaInP layer, and the second type semiconductor layer 26 includes a Si-doped AlInP layer and a Si-doped AlGaInP layer, which are sequentially stacked. Among them, the P-type GaP layer is also referred to as a window layer, the P-type AlInP layer and the N-type AlInP layer are also referred to as a confinement layer, and the N-type AlGaInP layer is also referred to as a current spreading layer. The first-type electrode 31 is a gold beryllium alloy layer, and the second-type electrode 32 is a gold germanium alloy layer.
Illustratively, the thickness of the window layer is from 5 microns to 7 microns, such as 6 microns.
Alternatively, as shown in fig. 3, the light emitting diode chip further includes a transparent adhesive layer 40 laminated between the transparent substrate 10 and the first-type semiconductor layer 24.
Illustratively, the transparent adhesive layer 40 includes a silicon Oxide layer, a zinc Oxide layer, a silicon nitride layer, an ITO (Indium Tin Oxide) layer, In2O3Layer, SnO2Layer, TiO2Layer, ZrO2At least one of the layers.
Illustratively, the transparent bonding layer has a thickness of 2.5 microns to 3.5 microns, such as 3 microns.
The embodiment of the disclosure provides a manufacturing method of a light emitting diode chip, which is suitable for manufacturing the light emitting diode chip shown in fig. 1. Fig. 5 is a flowchart of a method for manufacturing a light emitting diode chip according to an embodiment of the present disclosure. Referring to fig. 5, the manufacturing method includes:
step 201: a transparent substrate with a first surface covered with an epitaxial layer is provided.
Optionally, the step 201 includes:
the method comprises the following steps of firstly, growing a GaAs buffer layer, a corrosion stop layer, a second type semiconductor layer, an active layer and a first type semiconductor layer on a GaAs substrate in sequence by adopting a Metal-organic Chemical Vapor Deposition (MOCVD) technology;
a second step of bonding a transparent substrate on the first type semiconductor layer using a transparent adhesive layer;
and thirdly, removing the GaAs substrate, the GaAs buffer layer and the corrosion stop layer.
Optionally, before the second step, the step 201 further includes:
and roughening the surface of the window layer.
In practical applications, the surface of the window layer may be roughened using a roughening solution.
Optionally, the second step comprises:
forming transparent bonding layers on the window layer and the transparent substrate respectively;
the transparent adhesive layer formed on the transparent substrate and the transparent adhesive layer formed on the window layer are bonded together using pressure.
Illustratively, the temperature when forming the transparent bonding layer is 200 ℃.
Optionally, before the transparent adhesive layers are bonded together, the manufacturing method further comprises:
and polishing the transparent bonding layer.
Illustratively, the thickness of the polished transparent bonding layer is 1 micrometer. The polishing is carried out by using the polishing pad, and the roughness of the transparent bonding layer can reach the level of Ra0.2 and is smoother.
Optionally, before the transparent adhesive layers are bonded together, the manufacturing method further comprises:
treating the surface of the transparent bonding layer formed on the transparent substrate and the surface of the transparent bonding layer formed on the window layer by using ammonia water;
and placing the transparent bonding layer formed on the transparent substrate and the transparent bonding layer formed on the window layer in an electric field environment, and treating the surface of the transparent bonding layer formed on the transparent substrate and the surface of the transparent bonding layer formed on the window layer by using oxygen.
The surface of the transparent bonding layer is treated by ammonia water, and then the surface of the transparent bonding layer is treated by oxygen in an electric field environment, so that-OH ions on the surface of the transparent bonding layer can be effectively activated, and a good bonding effect is obtained.
Illustratively, the bonding temperature is 300 ℃ and the bonding pressure is 10 tons.
Optionally, the epitaxial layer includes a first type semiconductor layer, an active layer, and a second type semiconductor layer sequentially stacked on the first surface.
The manufacturing method also comprises the following steps:
forming a groove extending from the second type semiconductor layer to the first type semiconductor layer in the epitaxial layer, and forming an isolation groove extending from the second type semiconductor layer to the transparent substrate outside the epitaxial layer; the groove divides the second type semiconductor layer and the active layer into a first part and a second part which are isolated from each other, the first part is positioned in the groove, and the second part is positioned outside the groove; the metal electrode includes a first type electrode disposed on the first type semiconductor layer and a second type electrode disposed on the second type semiconductor layer of the first portion.
Illustratively, the groove can be formed by utilizing an Inductively Coupled Plasma etching (ICP) device, the Plasma density is high, the etching speed is high, the photoresist loss is less, and the chip yield is favorably improved.
Step 202: a bump, a recess, and a connection portion are formed on the second surface of the epitaxial layer.
In an embodiment of the disclosure, the second surface is opposite to a third surface of the epitaxial layer, the third surface being in contact with the first surface. The convex part and the concave part are planes parallel to each other, and the distance between the convex part and the first surface is larger than the distance between the concave part and the first surface. The convex part and the concave part are connected together through the connecting part, and included angles between tangent planes of all points on the connecting part and the convex part are the same.
Optionally, this step 202 includes:
forming a patterned photoresist on the second surface by using a photoetching technology;
dry etching the epitaxial layer to form a convex part, a concave part and a connecting part on the second surface; wherein the etching rate of the epitaxial layer is less than that of the patterned photoresist;
and removing the patterned photoresist.
And etching an inclined plane, namely the connecting part, at the edge of the photoresist by using the fact that the etching rate of the epitaxial layer is less than that of the patterned photoresist.
Step 203: and forming a metal electrode at least on the convex part and the connecting part, wherein metal atoms in the metal electrode are diffused into the epitaxial layer to form ohmic contact.
Optionally, this step 203 comprises:
forming a negative photoresist with a set pattern in the groove and on the second-type semiconductor layer by adopting a photoetching technology;
laying electrode materials on the negative photoresist and the epitaxial layer which is not covered by the negative photoresist by adopting an evaporation technology;
and removing the electrode materials on the negative photoresist and the negative photoresist, and forming a metal electrode by the electrode materials left on the epitaxial layer.
Illustratively, the power of evaporation is ensured when the electrode material is evaporated, and the evaporation time is avoided to exceed 5 seconds, so that the deviation of the alloy composition is prevented.
Optionally, after step 203, the manufacturing method further includes:
a passivation protection layer is formed on the epitaxial layer except for the electrode.
Illustratively, the passivation protective layer is a combined structure of silicon nitride and silicon oxide, and the protection effect is good.
Optionally, after step 203, the manufacturing method further includes:
and thinning the substrate.
Illustratively, the thickness of the substrate after thinning is 120 μm.
Optionally, after step 203, the manufacturing method further includes:
carrying out invisible cutting on the substrate;
splitting the substrate to obtain at least two mutually independent chips;
and testing the chip.
By stealth dicing and breaking, the loss of brightness can be better reduced.
The above description is intended to be exemplary only and not to limit the present disclosure, and any modification, equivalent replacement, or improvement made without departing from the spirit and scope of the present disclosure is to be considered as the same as the present disclosure.
Claims (9)
1. A light emitting diode chip, characterized in that it comprises a transparent substrate (10), an epitaxial layer (20) and a metal electrode (30); the epitaxial layer (20) covers the first surface of the transparent substrate (10); a second surface of the epitaxial layer (20) comprising protrusions (21), recesses (22) and connecting portions (23), the second surface being opposite to a third surface of the epitaxial layer (20), the third surface being in contact with the first surface; the convex part (21) and the concave part (22) are planes parallel to each other, and the distance between the convex part (21) and the first surface is larger than the distance between the concave part (22) and the first surface; the convex part (21) and the concave part (22) are connected together through the connecting part (23); the metal electrode (30) at least covers the convex part (21) and the connecting part (23), and metal atoms in the metal electrode (30) are diffused into the epitaxial layer (20) to form ohmic contact;
the quantity of connecting portion (23) is at least two, at least two connecting portion (23) are followed bellying (21) is to the direction of depressed part (22) sets gradually, at least two tangent plane of connecting portion (23) upper point with contained angle between bellying (21) is along following bellying (21) is to the direction of depressed part (22) reduces one by one.
2. The light-emitting diode chip as claimed in claim 1, characterized in that the angle between the tangent plane to the point on the connection portion (23) and the protrusion (21) is 165 ° to 175 °.
3. The light-emitting diode chip as claimed in claim 1 or 2, characterized in that the elevation (21) is polygonal.
4. The light-emitting diode chip as claimed in claim 1 or 2, characterized in that the metal electrode (30) also covers the region of the depression (22) which is connected to the connection (23).
5. The light-emitting diode chip as claimed in claim 1 or 2, wherein the epitaxial layer (20) comprises a first type semiconductor layer (24), an active layer (25) and a second type semiconductor layer (26) which are sequentially stacked on the first surface, the epitaxial layer (20) has a groove (41) therein extending from the second type semiconductor layer (26) to the first type semiconductor layer (24), and the epitaxial layer (20) has an isolation trench (42) therein extending from the second type semiconductor layer (26) to the transparent substrate (10); the groove (41) divides the second type semiconductor layer (26) and the active layer (25) into a first portion (27) and a second portion (28) which are isolated from each other, the first portion (27) is located inside the groove (41), and the second portion (28) is located outside the groove (41); the metal electrode (30) comprises a first type electrode (31) and a second type electrode (32), the first type electrode (31) is arranged on the first type semiconductor layer (24), and the second type electrode (32) is arranged on the second type semiconductor layer (26) of the first part (27).
6. The light-emitting diode chip according to claim 5, characterized in that the projection of said second portion (28) on said first surface comprises an annular region (281) and two protruding regions (282), said two protruding regions (282) being respectively connected on an inner ring of said annular region (281), said two protruding regions (282) being located on opposite sides of said electrode of the first type (31), a line of centers of said two protruding regions (282) being perpendicular to a line of centers of said electrode of the first type (31) and said electrode of the second type (32).
7. A manufacturing method of a light emitting diode chip is characterized by comprising the following steps:
providing a transparent substrate with a first surface covered with an epitaxial layer;
forming a convex portion, a concave portion and a connecting portion on a second surface of the epitaxial layer; wherein the second surface is opposite a third surface of the epitaxial layer, the third surface being in contact with the first surface; the convex part and the concave part are planes parallel to each other, and the distance between the convex part and the first surface is greater than the distance between the concave part and the first surface; the convex part and the concave part are connected together through the connecting part; the number of the connecting parts is at least two, the at least two connecting parts are sequentially arranged along the direction from the convex part to the concave part, and the included angles between tangent planes of upper points of the at least two connecting parts and the convex part are gradually reduced along the direction from the convex part to the concave part;
and forming a metal electrode at least on the convex part and the connecting part, wherein metal atoms in the metal electrode are diffused into the epitaxial layer to form ohmic contact.
8. The method of manufacturing according to claim 7, wherein the forming of the convex portion, the concave portion, and the connection portion on the second surface of the epitaxial layer includes:
forming a patterned photoresist on the second surface by adopting a photoetching technology;
dry etching the epitaxial layer to form a convex part, a concave part and a connecting part on the second surface; wherein the etching rate of the epitaxial layer is less than that of the patterned photoresist;
and removing the patterned photoresist.
9. The method according to claim 7 or 8, wherein the epitaxial layer comprises a first type semiconductor layer, an active layer and a second type semiconductor layer which are sequentially laminated on the first surface;
the manufacturing method further comprises the following steps:
forming a groove extending from the second type semiconductor layer to the first type semiconductor layer in the epitaxial layer, and forming an isolation groove extending from the second type semiconductor layer to the transparent substrate outside the epitaxial layer; the groove divides the second type semiconductor layer and the active layer into a first part and a second part which are isolated from each other, the first part is positioned in the groove, and the second part is positioned outside the groove; the metal electrode comprises a first type electrode and a second type electrode, the first type electrode is arranged on the first type semiconductor layer, and the second type electrode is arranged on the second type semiconductor layer of the first part.
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