CN113594318B - High-brightness light-emitting diode chip and manufacturing method thereof - Google Patents
High-brightness light-emitting diode chip and manufacturing method thereof Download PDFInfo
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- CN113594318B CN113594318B CN202110604200.8A CN202110604200A CN113594318B CN 113594318 B CN113594318 B CN 113594318B CN 202110604200 A CN202110604200 A CN 202110604200A CN 113594318 B CN113594318 B CN 113594318B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0025—Processes relating to coatings
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Abstract
The disclosure provides a high-brightness light-emitting diode chip and a manufacturing method thereof, and belongs to the technical field of semiconductors. High-brightness light-emitting diode chip: the second surface of the substrate has an open groove extending from the second surface to an inside of the substrate, and the open groove is arranged around a peripheral wall of the second surface; the high-brightness light-emitting diode chip also comprises a filling layer arranged in the open slot, wherein the filling layer is a silicon oxide layer doped with diamond particles. By adopting the chip, the cross section of each LED unit after the LED chip is scratched can be rectangular, and the light-emitting symmetry of each LED unit is improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a high-brightness light emitting diode chip and a method for manufacturing the same.
Background
A Light Emitting Diode (LED) is a semiconductor device capable of Emitting Light. By adopting different semiconductor materials and structures, LEDs can cover the full color range from ultraviolet to infrared, and have been widely used in economic life for display, decoration, communication, and the like.
The chip is a core device of the LED, and in the related technology, the LED chip comprises a sapphire substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, an N-type electrode, a P-type electrode, an insulating layer and a protective layer; the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially stacked on the first surface of the sapphire substrate; a groove extending to the N-type semiconductor layer is formed in the P-type semiconductor layer, the N-type electrode is arranged on the N-type semiconductor layer in the groove, and the P-type electrode is arranged on the P-type semiconductor layer; the insulating layer is laid in the groove and on the N-type electrode, the P-type semiconductor layer and the P-type electrode, and the protective layer is laid on the insulating layer.
After the LED chip is manufactured, the LED chip is usually scratched in an invisible cutting mode. Since the crystal orientation of the sapphire is not perpendicular to the first surface of the sapphire, the cross section of each LED unit obtained by scribing has a parallelogram shape, so that the light-emitting symmetry of each LED unit is deteriorated.
Disclosure of Invention
The embodiment of the disclosure provides a high-brightness light-emitting diode chip and a manufacturing method thereof, which can enable the cross section of each LED unit after the LED chip is scratched to be rectangular, and improve the light-emitting symmetry of each LED unit. The technical scheme is as follows:
in one aspect, a high-brightness light emitting diode chip is provided, which includes a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, an N-type electrode, a P-type electrode, an insulating layer, and a protective layer; the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially stacked on the first surface of the substrate; a groove extending to the N-type semiconductor layer is formed in the P-type semiconductor layer, the N-type electrode is arranged on the N-type semiconductor layer in the groove, and the P-type electrode is arranged on the P-type semiconductor layer; the insulating layer is laid in the groove and on the N-type electrode, the P-type semiconductor layer and the P-type electrode, the protective layer is laid on the insulating layer,
the second surface of the substrate has an open groove extending from the second surface to an inside of the substrate, and the open groove is arranged around a peripheral wall of the second surface;
the high-brightness light-emitting diode chip also comprises a filling layer arranged in the open slot, wherein the filling layer is a silicon oxide layer doped with diamond particles.
Optionally, the depth of the filling layer is 8-15 um.
Optionally, the doping proportion of diamond in the filling layer is 10% to 30%.
Optionally, the side wall of the open slot is rough.
Optionally, a side of the filling layer away from the first surface has a pattern.
Optionally, the high-brightness light emitting diode chip includes two P-type electrodes and one N-type electrode, the groove where the N-type electrode is located in the middle of the P-type semiconductor layer, orthographic projections of the two P-type electrodes on the substrate are respectively located on two sides of an orthographic projection of the N-type electrode on the substrate, and the two P-type electrodes are connected.
In another aspect, a method for manufacturing a high-brightness light emitting diode chip is provided, the method comprising:
providing a substrate, wherein the substrate comprises a first surface and a second surface which are opposite;
growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the first surface of the substrate in sequence;
forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer, forming an N-type electrode on the N-type semiconductor layer in the groove, and forming a P-type electrode on the P-type semiconductor layer;
forming insulating layers in the groove, on the N-type electrode, the P-type semiconductor layer and the P-type electrode;
forming a protective layer on the insulating layer;
thinning the substrate;
opening an open groove in the second surface of the substrate, the open groove extending from the second surface to the inside of the substrate, and the open groove being arranged around a peripheral wall of the second surface;
forming a filling layer in the open slot, wherein the filling layer is a silicon oxide layer doped with diamond particles;
and carrying out laser invisible cutting and scribing on the substrate at the position of the filling layer.
Optionally, the doping proportion of diamond in the filling layer is 10% to 30%.
Optionally, before the substrate is subjected to laser stealth dicing and scribing at the position of the filling layer, the manufacturing method further includes:
and carrying out graphical processing on one surface of the filling layer, which is far away from the first surface.
Optionally, the opening a groove extending to the N-type semiconductor layer on the P-type semiconductor layer, forming an N-type electrode on the N-type semiconductor layer in the groove, and forming a P-type electrode on the P-type semiconductor layer includes:
a groove extending to the N-type semiconductor layer is formed in the middle of the P-type semiconductor layer;
forming the N-type electrode on the N-type semiconductor layer in the groove;
and respectively forming two P-type electrodes on the P-type semiconductor layers on two sides of the groove, so that orthographic projections of the two P-type electrodes on the substrate are respectively positioned on two sides of orthographic projections of the N-type electrode on the substrate, and the two P-type electrodes are connected.
The technical scheme provided by the embodiment of the disclosure has the following beneficial effects:
an open groove is formed in the second surface of the substrate, and a filling layer is arranged in the open groove. The open grooves are arranged around the peripheral wall of the second surface, and the open grooves extend from the second surface to the interior of the substrate, namely the periphery of the substrate is provided with the filling layer. And the filling layer is a silicon oxide layer doped with diamond particles, and the processing pattern is more regular because the crystal orientation of the silicon oxide material is not obvious. Therefore, when the chip is subjected to laser invisible cutting and scribing from the filling layer, a controlled and stable edge angle can be obtained, so that the cross section of each LED unit after the LED chip is scribed is rectangular, and the light-emitting symmetry of each LED unit is improved. Meanwhile, the surfaces of all cut LED units can be ensured to be smooth. And the diamond particles are doped in the silicon oxide layer, so that the refractive index of the filling layer is closer to that of sapphire, and the light emitting efficiency of the LED chip is not influenced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a high-brightness light emitting diode chip according to an embodiment of the present disclosure;
fig. 2 is a bottom view of a high-brightness led chip provided in an embodiment of the present disclosure;
FIG. 3 is a diagram of a positional relationship between an N-type electrode and a P-type electrode according to an embodiment of the disclosure;
FIG. 4 is a schematic distribution diagram of P-type pads and N-type pads provided by the embodiment of the present disclosure;
fig. 5 is a flowchart of a method for manufacturing a high-brightness led chip according to an embodiment of the present disclosure;
fig. 6 is a flowchart of a method for manufacturing another high-brightness led chip according to an embodiment of the disclosure;
fig. 7 is a schematic distribution diagram of a light spot provided by an embodiment of the disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a high-brightness light emitting diode chip provided by an embodiment of the present disclosure, and as shown in fig. 1, the light emitting diode chip includes a substrate 1, an N-type semiconductor layer 2, an active layer 3, a P-type semiconductor layer 4, an N-type electrode 5, a P-type electrode 6, an insulating layer 7, and a protective layer 8. An N-type semiconductor layer 2, an active layer 3, and a P-type semiconductor layer 4 are sequentially stacked on the first surface 1a of the substrate 1. A groove extending to the N-type semiconductor layer 2 is formed in the P-type semiconductor layer 4, an N-type electrode 5 is arranged on the N-type semiconductor layer 2 in the groove, and the P-type electrode 5 is arranged on the P-type semiconductor layer 4. An insulating layer 7 is laid in the groove and on the N-type electrode 5, and on the P-type semiconductor layer 4 and the P-type electrode 6, and a protective layer 8 is laid on the insulating layer 7.
Fig. 2 is a bottom view of a high-brightness light emitting diode chip provided by an embodiment of the present disclosure, and as shown in fig. 2, the second surface 1b of the substrate 1 has an open groove 11, the open groove 11 extends from the second surface 1b to the inside of the substrate, and the open groove 11 is arranged around the peripheral wall of the second surface 1 b.
The high-brightness light-emitting diode chip also comprises a filling layer Q arranged in the open groove 11, wherein the filling layer Q is a silicon oxide layer doped with diamond particles.
The embodiment of the disclosure forms an open groove on the second surface of the substrate, and a filling layer is arranged in the open groove. The open grooves are arranged around the peripheral wall of the second surface, and the open grooves extend from the second surface to the inner part of the substrate, namely the periphery of the substrate is provided with the filling layer. And the filling layer is a silicon oxide layer doped with diamond particles, and the processing pattern is more regular because the crystal orientation of the silicon oxide material is not obvious. Therefore, when the chip is subjected to laser invisible cutting and scribing from the filling layer, a controlled and stable edge angle can be obtained, so that the cross section of each LED unit after the LED chip is scribed is rectangular, and the light-emitting symmetry of each LED unit is improved. Meanwhile, the surfaces of all cut LED units can be ensured to be smooth. And the diamond particles are doped in the silicon oxide layer, so that the refractive index of the filling layer is closer to that of sapphire, and the light emitting efficiency of the LED chip is not influenced.
Optionally, the depth of the filling layer Q is 8-15 um.
If the depth of the filling layer Q is too deep, the cost increases and the filling layer Q is easily broken. If the depth of the filling layer Q is too small, the effect of improving the symmetry of the light output of each LED unit is not obtained.
Optionally, the depth of the filling layer Q is 10 um.
Optionally, the doping proportion of diamond in the filling layer Q is 10% to 30%.
If the doping ratio of diamond is too small, the refractive index of the filling layer Q cannot be made close to the refractive index of the sapphire substrate. If the doping proportion of the diamond is too much, the content of the silicon oxide is low, and the effect of enabling the cross section of each LED unit after the LED chip is scratched to be rectangular cannot be achieved.
Alternatively, the side walls of the open slots 11 are roughened.
Through setting up the lateral wall of open slot 11 into the matte, when light jetted out from sapphire substrate side, the matte can form diffuse reflection structure to the intensity of the side light-emitting of increase chip.
Illustratively, the roughened surface may be a surface having a plurality of pyramidal projections.
Optionally, a side of the filling layer Q away from the first surface 1a has a pattern.
Through setting up the pattern to when carrying out stealthy cutting of laser and drawing apart to the substrate, the position of knowing filling layer Q accurately, thereby can carry out stealthy cutting of laser and draw apart from filling layer Q department. The specific pattern can be set according to actual needs, and the embodiment of the disclosure does not limit this.
Alternatively, referring to fig. 1, the high-brightness light emitting diode chip includes two P-type electrodes 6 and one N-type electrode 5. The groove where the N-type electrode 5 is located in the middle of the P-type semiconductor layer 4, the orthographic projections of the two P-type electrodes 6 on the substrate 1 are respectively located on two sides of the orthographic projection of the N-type electrode 5 on the substrate 1, and the two P-type electrodes 6 are connected.
Fig. 3 is a positional relationship diagram of an N-type electrode and a P-type electrode provided in an embodiment of the disclosure, and as shown in fig. 3, the N-type electrode 5 is located between two P-type electrodes 6.
Alternatively, the N-type semiconductor layer 2 is N-type doped GaN, the active layer 3 includes InGaN layers and GaN layers alternately stacked, and the P-type semiconductor layer 4 is P-type doped GaN.
Alternatively, each of the N-type electrode 5 and the P-type electrode 6 includes a Cr layer, an Al layer, a Cr layer, a Ti layer, and an Al layer, which are sequentially stacked.
Alternatively, the insulating layer 7 includes a passivation layer and a distributed bragg reflector layer, which are sequentially stacked.
Wherein the passivation layer is a silicon oxide layer with a thickness of 400-600 nm, such as 500 nm. The silicon oxide has higher hardness, and can effectively protect the chip.
The distributed Bragg reflection layer comprises silicon oxide layers and titanium oxide layers which are alternately stacked, and the number of the silicon oxide layers and the titanium oxide layers is 30-40, such as 36.
Alternatively, the protective layer 8 may be a silicon oxide layer. The thickness is 400 to 600nm, such as 500 nm. The protective layer can prevent the epitaxial wafer from being corroded by oxygen and water vapor in the air.
Optionally, the light emitting diode chip further includes an N-type pad 9 and a P-type pad 10. The insulating layer 7 is provided with an N-type via hole 7a extending to the N-type electrode 5 and a P-type via hole 7b extending to the P-type electrode 6. The N-type pad 9 is located on the insulating layer 7 around the N-type via hole 7a and the N-type via hole 7a, and the P-type pad 10 is located on the insulating layer 7 around the P-type via hole 7b and the P-type via hole 7 b.
Illustratively, the N-type pad 9 and the P-type pad 10 are each a Ti/Al/Ti/Al/Ti/Au stacked structure. The thickness of the first Ti layer and the thickness of the third Ti layer are both 20nm, the thickness of the second Al layer and the thickness of the fourth Al layer are both 1000nm, the thickness of the fifth Ti layer is 100nm, and the thickness of the sixth Au layer is 300 nm. The Ti layer can play a role in adhesion, and the Al layer can play a role in reflection so as to reflect light rays which are emitted to the P-type bonding pad or the N-type bonding pad and increase light rays emitted from the chip from the transparent substrate. The Au layer serves as a solder layer, and the chip can be fixed on the circuit board by solder.
It should be noted that, in the embodiment of the present disclosure, as shown in fig. 1, a part of the protective layer 8 is further coated on the sidewalls of the N-type pad 9 and the P-type pad 10.
Fig. 4 is a schematic distribution diagram of P-type pads and N-type pads provided by an embodiment of the present disclosure, and referring to fig. 4, N-type pads 9 and P-type pads 10 are disposed on insulating layer 7 at intervals, and the disposed areas of N-type pads 9 and P-type pads 10 on insulating layer 7 are the same in size, so as to facilitate forming stable electrical connection with a circuit board.
The embodiment of the present disclosure provides a method for manufacturing a high-brightness light emitting diode chip, which is suitable for manufacturing the high-brightness light emitting diode chip shown in fig. 1. Fig. 5 is a flowchart of a method for manufacturing a high-brightness light emitting diode chip according to an embodiment of the present disclosure, and referring to fig. 5, the method for manufacturing includes:
Wherein the substrate includes opposing first and second surfaces. The substrate may be a sapphire substrate.
Optionally, this step 502 may include:
an N-type semiconductor layer, an active layer and a P-type semiconductor layer are sequentially grown on a substrate by using a Metal-organic Chemical Vapor Deposition (MOCVD) technology.
Illustratively, step 503 may include:
firstly, a groove extending to the N-type semiconductor layer is formed in the middle of the P-type semiconductor layer.
Illustratively, this step may include:
forming a patterned photoresist on the P-type semiconductor layer by adopting a photoetching technology;
and forming a groove extending to the N-type semiconductor layer in the middle of the P-type semiconductor layer by adopting an Inductively Coupled Plasma etching (ICP). Wherein, the etching depth can be 5 um.
And secondly, forming an N-type electrode on the N-type semiconductor layer in the groove.
Illustratively, this step may include:
forming a negative photoresist on the N-type semiconductor layer in the groove by adopting a photoetching technology;
forming an electrode material on the negative photoresist and the N-type semiconductor layer in the groove by adopting an evaporation technology;
and removing the negative photoresist and the electrode material on the negative photoresist, and forming an N-type electrode by the electrode material on the N-type semiconductor layer in the groove.
The N-type electrode comprises a Cr layer, an Al layer, a Cr layer, a Ti layer and an Al layer which are sequentially laminated.
And thirdly, respectively forming two P-type electrodes on the P-type semiconductor layers on the two sides of the groove, so that orthographic projections of the two P-type electrodes on the substrate are respectively positioned on the two sides of the orthographic projection of the N-type electrode on the substrate, and the two P-type electrodes are connected.
Illustratively, this step may include:
forming a negative photoresist on the P-type semiconductor layer by using a photoetching technology;
forming an electrode material on the negative photoresist and the P-type semiconductor layer by adopting an evaporation technology;
and removing the negative photoresist and the electrode material on the negative photoresist, and forming a P-type electrode by the electrode material on the P-type semiconductor layer.
The P-type electrode comprises a Cr layer, an Al layer, a Cr layer, a Ti layer and an Al layer which are sequentially laminated.
In an embodiment of the present disclosure, the insulating layer includes a passivation layer and a distributed bragg reflector layer that are sequentially stacked.
Illustratively, the passivation layer may be formed using a PECVD (Plasma Enhanced Chemical Vapor Deposition) method.
Wherein the protective layer is a silicon oxide layer with a thickness of 400-600 nm, such as 500 nm.
Illustratively, the protective layer may be formed by a PECVD (Plasma Enhanced Chemical Vapor Deposition) method.
And 507, opening an open groove on the second surface of the substrate.
Wherein the open groove extends from the second surface to an inside of the substrate, and the open groove is arranged around a peripheral wall of the second surface.
Illustratively, step 507 may include:
and opening grooves are formed in the second surface of the substrate in an ultraviolet cutting mode, and rough surfaces are formed on the side walls of the opening grooves.
Wherein, the filling layer is a silicon oxide layer doped with diamond particles. A coating process may be used to form the fill layer within the open trench. The specific structure of the filling layer is referred to the above embodiments, and the embodiments of the present disclosure are not described herein again.
And 509, carrying out laser invisible cutting and scribing on the substrate at the position of the filling layer.
The embodiment of the disclosure forms an open groove on the second surface of the substrate, and a filling layer is arranged in the open groove. Since the open grooves are arranged around the peripheral wall of the second surface and extend from the second surface to the inside of the substrate, the substrate has the filling layer all around. And the filling layer is a silicon oxide layer doped with diamond particles, and the processing pattern is more regular because the crystal orientation of the silicon oxide material is not obvious. Therefore, when the chip is subjected to laser invisible cutting and scribing from the filling layer, a controlled and stable edge angle can be obtained, so that the cross section of each LED unit after the LED chip is scribed is rectangular, and the light-emitting symmetry of each LED unit is improved. But also the surface of each cut LED unit is relatively smooth. Meanwhile, because the diamond particles are doped in the silicon oxide layer, the refractive index of the filling layer is closer to that of sapphire, and the light emitting efficiency of the LED chip cannot be influenced.
The embodiment of the present disclosure provides another method for manufacturing a high-brightness led chip, which is suitable for manufacturing the high-brightness led chip shown in fig. 1. Fig. 6 is a flowchart of another method for manufacturing a high-brightness led chip according to an embodiment of the disclosure, and referring to fig. 6, the method includes:
Wherein the substrate includes opposing first and second surfaces. The substrate may be a sapphire substrate.
Wherein, the first surface of graphical sapphire substrate has the toper arch of a plurality of interval equipartitions, and the bellied bottom diameter of every toper is 1.3 ~ 1.7um, and the bellied height of every toper is 0.8 ~ 1.2 um.
Alternatively, this step 603 may be the same as step 502 and will not be described in detail here.
Alternatively, step 604 may be the same as step 503 and will not be described in detail herein.
Optionally, the manufacturing method further comprises:
depositing Indium Tin Oxide (ITO) transparent conductive material on the epitaxial layer;
forming a patterned photoresist on the transparent conductive material by adopting a photoetching technology;
corroding the transparent conductive material by a wet method to form a transparent conductive layer;
and removing the patterned photoresist.
Among them, hydrochloric acid solution may be used as the etching solution.
Alternatively, step 605 may be the same as step 504 and will not be described in detail here.
Step 606 is to form an N-type via extending to the N-type electrode and a P-type via extending to the P-type electrode on the insulating layer.
Optionally, step 606 may include:
forming a patterned photoresist on the insulating layer by adopting a photoetching technology;
adopting a dry etching technology to form an N-type communication hole extending to the N-type electrode and a P-type communication hole extending to the P-type electrode in the insulating layer;
and removing the patterned photoresist.
Step 607 is to form a P-type pad on the insulating layer in and around the P-type via hole in the P-type via hole and an N-type pad on the insulating layer in and around the N-type via hole.
Illustratively, the N-type bonding pad and the P-type bonding pad are both of a Ti/Al/Ti/Al/Ti/Au laminated structure. The thickness of the first Ti layer and the thickness of the third Ti layer are both 20nm, the thickness of the second Al layer and the thickness of the fourth Al layer are both 1000nm, the thickness of the fifth Ti layer is 100nm, and the thickness of the sixth Au layer is 300 nm.
Illustratively, step 607 may include:
forming a negative photoresist on the insulating layer by using a photolithography technique;
forming pad materials in the N-type communicating holes, the P-type communicating holes and the negative photoresist by adopting an evaporation technology;
and removing the negative photoresist and the pad material on the negative photoresist, wherein the pad material in the N-type communication hole and on the insulating layer around the N-type communication hole forms an N-type pad, and the pad material in the N-type communication hole and on the insulating layer around the N-type communication hole forms a P-type pad.
Step 608 forms a protective layer over the insulating layer.
Alternatively, step 608 may be the same as step 505 and will not be described in detail herein.
And step 609, thinning the substrate.
In the embodiment of the disclosure, the final thickness of the thinned substrate is about 60-120 um, for example, 80 um. And the loss of light in the substrate is reduced under the condition of ensuring the supporting strength.
Alternatively, this step 610 may be the same as step 507 and will not be described in detail herein.
Alternatively, this step 611 may be the same as step 508 and will not be described in detail here.
Illustratively, before performing step 611, the manufacturing method may further include:
and patterning the side of the filling layer far away from the first surface to enable the side of the filling layer far away from the first surface to have a pattern.
Through setting up the pattern to when carrying out stealthy cutting of laser and drawing apart to the substrate, the position of knowing the filling layer of accuracy, thereby can carry out stealthy cutting of laser and draw apart from the filling layer department. The specific pattern can be set according to actual needs, and the embodiment of the disclosure does not limit this.
And 612, carrying out laser invisible cutting and scribing on the substrate at the position of the filling layer.
In the disclosed embodiments, laser stealth dicing techniques may be employed to stealth scribe the substrate. The laser invisible cutting is used as a scheme for cutting the wafer by laser, so that the problems of grinding wheel scribing are well avoided. The laser invisible cutting is that single pulse of pulse laser is optically shaped to be transmitted through the surface of a material to be focused in the material, the energy density in a focus area is high, and a multi-photon absorption nonlinear absorption effect is formed, so that the material is modified to form cracks. Each laser pulse acts at equal intervals, and an altered layer can be formed in the material by forming equal-interval damage. The molecular bonds of the material are broken at the modified layer position, and the connection of the material becomes fragile and easy to separate. And after cutting, fully separating the product in a manner of stretching the carrier film, and enabling a gap to be formed between the chip and the chip. The processing mode avoids damage to the chip caused by mechanical direct contact and pure water flushing.
Fig. 7 is a schematic distribution diagram of a light spot provided by an embodiment of the present disclosure, and as shown in fig. 7, when a chip is scribed by laser stealth dicing, laser is also optimized in position setting, and scribing by laser stealth dicing is performed at A, B, C as shown in the figure. The distance from the position A to the second surface 1B is L1, the distance from the position B to the position A is L2, the distance from the position C to the position B is L3, and L1 < L2 < L3.
Illustratively, L1 ═ 10um, L2 ═ 20um, and L3 ═ 30 um.
The embodiment of the disclosure forms an open groove on the second surface of the substrate, and a filling layer is arranged in the open groove. Since the open grooves are arranged around the peripheral wall of the second surface and extend from the second surface to the inside of the substrate, the substrate has the filling layer all around. And the filling layer is a silicon oxide layer doped with diamond particles, and the processing pattern is more regular because the crystal orientation of the silicon oxide material is not obvious. Therefore, when the chip is subjected to laser invisible cutting and scribing from the filling layer, a controlled and stable edge angle can be obtained, so that the cross section of each LED unit after the LED chip is scribed is rectangular, and the light-emitting symmetry of each LED unit is improved. But also the surface of each cut LED unit is relatively smooth. Meanwhile, because the diamond particles are doped in the silicon oxide layer, the refractive index of the filling layer is closer to that of sapphire, and the light emitting efficiency of the LED chip cannot be influenced.
The above description is intended to be exemplary only and not to limit the present disclosure, and any modification, equivalent replacement, or improvement made without departing from the spirit and scope of the present disclosure is to be considered as the same as the present disclosure.
Claims (10)
1. A high-brightness light-emitting diode chip comprises a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, an N-type electrode, a P-type electrode, an insulating layer and a protective layer; the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially stacked on the first surface of the substrate; a groove extending to the N-type semiconductor layer is formed in the P-type semiconductor layer, the N-type electrode is arranged on the N-type semiconductor layer in the groove, and the P-type electrode is arranged on the P-type semiconductor layer; the insulating layer is laid in the groove, on the N-type electrode, the P-type semiconductor layer and the P-type electrode, and the protective layer is laid on the insulating layer, which is characterized in that:
the second surface of the substrate has an open groove extending from the second surface to an inside of the substrate, and the open groove is arranged around a peripheral wall of the second surface;
the high-brightness light-emitting diode chip further comprises a filling layer arranged in the open slot, the filling layer is a silicon oxide layer doped with diamond particles, and the filling layer is used for carrying out laser invisible cutting.
2. The high-brightness light-emitting diode chip as claimed in claim 1, wherein the depth of the filling layer is 8-15 um.
3. The high-brightness light-emitting diode chip as claimed in claim 2, wherein the doping ratio of diamond in the filling layer is 10% to 30%.
4. The high intensity led chip of claim 1, wherein the side walls of the open slots are rough.
5. The high brightness light emitting diode chip of claim 1, wherein a side of the filling layer away from the first surface has a pattern.
6. The high brightness light emitting diode chip according to any one of claims 1 to 5, wherein the high brightness light emitting diode chip comprises two of the P-type electrodes and one of the N-type electrodes, the N-type electrode is located in the middle of the P-type semiconductor layer, the orthographic projections of the two of the P-type electrodes on the substrate are respectively located on two sides of the orthographic projection of the N-type electrode on the substrate, and the two of the P-type electrodes are connected.
7. A method for manufacturing a high-brightness light emitting diode chip is characterized by comprising the following steps:
providing a substrate, wherein the substrate comprises a first surface and a second surface which are opposite;
growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the first surface of the substrate in sequence;
forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer, forming an N-type electrode on the N-type semiconductor layer in the groove, and forming a P-type electrode on the P-type semiconductor layer;
forming insulating layers in the groove, on the N-type electrode, the P-type semiconductor layer and the P-type electrode;
forming a protective layer on the insulating layer;
thinning the substrate;
opening an open groove in the second surface of the substrate, the open groove extending from the second surface to the inside of the substrate, and the open groove being arranged around a peripheral wall of the second surface;
forming a filling layer in the open slot, wherein the filling layer is a silicon oxide layer doped with diamond particles;
and carrying out laser invisible cutting and scribing on the substrate at the position of the filling layer.
8. The manufacturing method according to claim 7, wherein the doping ratio of diamond in the filler layer is 10% to 30%.
9. The manufacturing method according to claim 7, wherein before the laser stealth dicing and scribing the substrate at the position of the filling layer, the manufacturing method further comprises:
and carrying out graphical processing on one surface of the filling layer, which is far away from the first surface.
10. The method according to claim 7, wherein the forming a groove extending to the N-type semiconductor layer in the P-type semiconductor layer, forming an N-type electrode on the N-type semiconductor layer in the groove, and forming a P-type electrode on the P-type semiconductor layer comprises:
a groove extending to the N-type semiconductor layer is formed in the middle of the P-type semiconductor layer;
forming the N-type electrode on the N-type semiconductor layer in the groove;
and respectively forming two P-type electrodes on the P-type semiconductor layers on two sides of the groove, so that orthographic projections of the two P-type electrodes on the substrate are respectively positioned on two sides of orthographic projections of the N-type electrode on the substrate, and the two P-type electrodes are connected.
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| JP2006086516A (en) * | 2004-08-20 | 2006-03-30 | Showa Denko Kk | Method for manufacturing semiconductor light emitting device |
| JP5101645B2 (en) * | 2010-02-24 | 2012-12-19 | 株式会社東芝 | Semiconductor light emitting device |
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