KR20180095426A - Light emitting diode having side reflection layer - Google Patents

Abstract

Disclosed is a light emitting diode including a side reflection layer which can reduce an orientation angle by reducing the amount light emitted to a side surface. The light emitting diode includes: a substrate having a side surface and an upper surface; a semiconductor stack disposed under the substrate, and including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer interposed between the first conductive semiconductor layer and the second conductive semiconductor layer; an ohmic reflection layer electrically connected to the second conductive semiconductor layer; first and second bump pads disposed under the ohmic reflection layer, and electrically connected to the first conductive semiconductor layer and the second conductive semiconductor layer, respectively; a side reflection layer covering the side surface of the substrate; and a capping layer covering the upper surface of the substrate and the side reflection layer.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a light emitting diode (LED)

BACKGROUND OF THE INVENTION 1. Field of the Invention [0002] The present invention relates to a light emitting diode, and more particularly, to a light emitting diode in which a side reflecting layer is used to narrow a directing angle.

In general, nitrides of a Group III element such as gallium nitride (GaN) and aluminum nitride (AlN) have excellent thermal stability and have a direct bandgap energy band structure. Recently, nitride materials for visible light and ultraviolet Has received a lot of attention. In particular, blue and green light emitting diodes using indium gallium nitride (InGaN) are utilized in various applications such as large-scale natural color flat panel displays, traffic lights, indoor lights, high density light sources, camera flashes, high resolution output systems and optical communication. In addition, since the light emitting diode is excellent in the linearity of the emitted light, it has been widely applied to headlamps for automobiles in recent years.

The light emitting diodes need to adjust the directivity angle depending on the application. Particularly, a headlamp for a car or a light emitting diode applied to a flashlight is advantageous as it has a narrow directivity angle. Also, when a backlight light source module for dispersing light using a lens is used, such as an LED TV, the light emitted to the side of the light emitting diode is difficult to be emitted to the outside through the lens, so that the light loss may increase. Therefore, it is necessary to reflect light traveling to the side surface of the light emitting diode and to emit it into a narrow angular range of angles.

A technique of forming a reflective layer on a side surface of a light emitting diode in order to reflect light traveling on a side surface has been studied.

However, the side surface of the light emitting diode includes a rough surface formed by a scribing process or the like. When a reflective layer is formed on such a rough surface, the reflectance may be relatively low. Therefore, a technique for improving the reflectance of the side reflective layer formed on the side surface of the light emitting diode including the rough surface is required.

Further, when a metal layer is formed on the side surface of the light emitting diode, problems may occur in surface mount technology (SMT) using solder. That is, since the affinity between the solder and the metal layer is good, the solder can ride on the metal layer to the side of the light emitting diode. This causes the solder to bond with the metal layer and damage the metal layer. Damage to the metal layer leads to deterioration of reflection efficiency, defective optical characteristics such as change of directivity characteristics, and the like.

Further, the reflective layer formed on the side surface is liable to be adhered to a defect due to the limitation of the deposition technique, and thus is likely to be peeled off from the light emitting diode. Therefore, a technique for stably maintaining the reflective layer on the side surface of the light emitting diode is required.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a light emitting diode capable of reducing the amount of light emitted to a side surface and reducing a directivity angle.

Another object of the present invention is to provide a light emitting diode capable of improving the reflectance of a side reflective layer formed on a side surface of a light emitting diode including a rough surface.

Another object of the present invention is to provide a light emitting diode which includes a side reflective layer and is surface mountable using solder.

Another object of the present invention is to provide a light emitting diode capable of stably maintaining the side reflecting layer.

A light emitting diode according to an embodiment of the present invention includes: a substrate having a side surface; A semiconductor stacked structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer interposed between the first conductive semiconductor layer and the second conductive semiconductor layer; An ohmic reflective layer electrically connected to the second conductive semiconductor layer; A first bump pad and a second bump pad disposed under the ohmic reflective layer and electrically connected to the first conductive semiconductor layer and the second conductive semiconductor layer, respectively; A side reflective layer covering a side surface of the substrate; And a capping layer covering the upper surface of the substrate and the side reflective layer.

According to embodiments of the present invention, it is possible to provide a light emitting diode having a narrow directivity angle by reflecting light directed to the side surface of the light emitting diode by adopting the side reflective layer. Furthermore, the side reflective layer and the capping layer covering the upper surface of the substrate are formed to stably bond the side reflective layer to the substrate structure, thereby preventing peeling of the side reflective layer.

Other advantages and effects of the present invention will become more apparent from the detailed description.

1 is a schematic plan view illustrating a light emitting diode according to an embodiment of the present invention.
2 is a cross-sectional view taken along the perforated line AA of FIG.
3 is a schematic cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention.
4 is a schematic cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention.
5 is a schematic cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention.
6 is a schematic cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention.
7 is a schematic cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention.
8 is a schematic cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention.
9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 16A, 16B, , 17B, 17C and 17D are schematic views for explaining a method of manufacturing a light emitting diode according to an embodiment of the present invention.
18A, 18B, 18C and 18D are schematic cross-sectional views for explaining a method of manufacturing a light emitting diode according to another embodiment of the present invention.
19A, 19B, 19C, and 19D are schematic cross-sectional views for explaining a method of manufacturing a light emitting diode according to another embodiment of the present invention.
20 is a schematic cross-sectional view for explaining a light emitting module according to an embodiment of the present invention.
21 is a schematic plan view for explaining a light emitting diode according to an embodiment of the present invention.
22 is a sectional view taken along the tear line AB in Fig.
23 is a schematic cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention.
24 is a schematic cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention.
25 is a schematic cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention.
26 is a schematic cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention.
27 is a schematic cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention.
28 and 29 are plan views and sectional views for explaining a method of manufacturing the light emitting diode 800 according to an embodiment. Fig. 28A is a plan view, and Fig. 28B is a cross-sectional view taken along the tear line AA in Fig. 28A.
30 is a schematic plan view illustrating a light emitting diode according to another embodiment of the present invention.
31 is a cross-sectional view taken along the tear line AA in Fig.
32A and 32B are partially enlarged cross-sectional views for explaining various examples of the light emitting diode of FIG.
33 is a schematic cross-sectional view illustrating a light source module according to an embodiment of the present invention.
34 is a schematic perspective view showing a vehicle equipped with a headlamp to which a light emitting diode according to embodiments of the present invention is applied.
35 is a schematic perspective view showing a mobile device equipped with a camera flash to which a light emitting diode according to embodiments of the present invention is applied.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can sufficiently convey the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the width, length, thickness, etc. of components may be exaggerated for convenience. It is also to be understood that when an element is referred to as being "above" or "above" another element, But also includes the case where another component is interposed between the two. Like reference numerals designate like elements throughout the specification.

A light emitting diode according to an embodiment of the present invention includes: a substrate having a side surface; A semiconductor stacked structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer interposed between the first conductive semiconductor layer and the second conductive semiconductor layer; An ohmic reflective layer electrically connected to the second conductive semiconductor layer; A first bump pad and a second bump pad disposed under the ohmic reflective layer and electrically connected to the first conductive semiconductor layer and the second conductive semiconductor layer, respectively; A side reflective layer covering a side surface of the substrate; And a capping layer covering the upper surface of the substrate and the side reflective layer.

The light directing angle of the light emitting diode can be reduced by reflecting light traveling to the side surface of the substrate by the side reflective layer. Further, since the side reflection layer can be firmly coupled to the substrate using the capping layer, a structurally stable light emitting diode can be provided.

The light emitting diode may further include a light-transmissive material layer interposed between the side surface of the substrate and the side reflective layer. By arranging the light-transmitting material layer between the substrate side surface and the side reflective layer, the adhesion of the side reflective layer can be improved and the reflectivity of the side reflective layer can be improved.

The substrate includes four side surfaces, and the light-transmissive material layer and the side reflective layer may cover four sides of the substrate. Accordingly, most of the light generated in the active layer is emitted to the outside through the top surface of the substrate.

The light-transmitting material layer may be an inorganic material layer such as a transparent electrode or an insulating layer, for example, ITO, ZnO, SiNx, SiON or SiO2. By using these material layers, an overall echo reflector (ODR) can be formed.

Furthermore, the lower end portions of the light-transmitting material layer and the side reflection layer may be parallel to each other.

The side reflective layer may include a reflective metal layer and a barrier layer. The barrier layer protects the reflective metal layer.

In one embodiment, the upper ends of the reflective metal layer and the barrier layer may be located outside the upper surface of the substrate. Therefore, light emitted through the upper surface of the substrate can be emitted to the outside without being reflected by the reflective metal layer.

On the other hand, the upper end of the barrier layer may be located higher than the upper end of the reflective metal layer.

Meanwhile, the side surface of the substrate may include a side surface perpendicular to the upper surface of the first conductive type semiconductor layer and a side surface inclined with respect to the vertical side surface. In one embodiment, the oblique side may be further away from the top surface of the substrate than the vertical side.

The inclined side surface may have an inclination angle of about 10 degrees or more with respect to the vertical side surface.

On the other hand, the inclined side surface may be a surface formed by a scraping process, and the vertical side surface may be a surface formed by braking. The surface formed by braking is smoother than the surface formed by the scribing process. Thus, the inclined side is a rougher side than the vertical side.

Meanwhile, the capping layer may include SiO2, ITO, a primer, or SOG.

The light emitting diode may include a mesa disposed on the first conductive semiconductor layer. The mesa includes the active layer and the second conductivity type semiconductor layer, and is spaced from the sides. In addition, the side reflective layer may be spaced laterally from the mesa.

The light emitting diode may further include a lower insulating layer covering the ohmic reflective layer, the lower insulating layer including a first opening exposing the first conductivity type semiconductor layer and a second opening exposing the ohmic reflective layer. A first pad metal layer disposed on the lower insulating layer and electrically connected to the first conductive semiconductor layer through the first opening; A second pad metal layer disposed on the lower insulating layer and electrically connected to the ohmic reflective layer through the second opening; And an upper insulating layer covering the first pad metal layer and the second pad metal layer, the upper insulating layer including a first opening exposing the first pad metal layer and a second opening exposing the second pad metal layer, The first and second bump pads may be disposed on the upper insulating layer and connected to the first pad metal layer and the second pad metal layer through the first opening and the second opening of the upper insulating layer, respectively.

The mesa may include a through hole through the second conductivity type semiconductor layer and the active layer to expose the first conductivity type semiconductor layer, and the first pad metal layer may include a first conductivity type semiconductor layer exposed through the through hole, And may be electrically connected to the semiconductor layer.

Further, the mesa may further include concave portions for exposing the first conductive type semiconductor layer on the side surfaces, and the first pad metal layer may be electrically connected to the first conductive type semiconductor layer exposed through the concave portions .

The mesa may have a shape in which the edges are cut, and the first pad metal layer may be electrically connected to the first conductivity type semiconductor layer in the vicinity of the edges of the mesa.

The light emitting diode may further include an ohmic oxide layer in ohmic contact with the second conductivity type semiconductor layer around the ohmic reflective layer. By adopting the ohmic oxide layer, the contact resistance can be reduced and the forward voltage can be lowered.

The light emitting diode may further include a wavelength converter disposed on the substrate. The wavelength converter may include a wavelength conversion sheet or a ceramic plate phosphor. Particularly, the ceramic plate phosphor has high heat resistance and can be used without being discolored for a long time even in a high temperature environment.

Furthermore, the wavelength converter may be bonded to the capping layer via an adhesive.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic plan view for explaining a light emitting diode 100 according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along a perforated line A-A in FIG.

1 and 2, the light emitting diode includes a substrate 21, a first conductive semiconductor layer 23, an active layer 25, a second conductive semiconductor layer 27, an ohmic reflective layer 31, An insulating layer 33, a first pad metal layer 35a, a second pad metal layer 35b, an upper insulating layer 37, a first bump pad 39a, a second bump pad 39b, a roughness reducing layer 53 , Or a light-transmitting material layer) and a side reflective layer 41. The first conductivity type semiconductor layer 23, the active layer 25, and the second conductivity type semiconductor layer 27 form a semiconductor laminate 30. Furthermore, the light emitting diode may further include an ohmic oxide layer 29.

The substrate 21 can be a sapphire substrate or a gallium nitride-based substrate, for example, on which a gallium nitride-based semiconductor layer can be grown. The sapphire substrate can grow the gallium nitride based semiconductor layer at a relatively low cost. On the other hand, since the gallium nitride based substrate has the same or similar refractive index as the first conductivity type semiconductor layer 23, the light emitted from the active layer 25 can be incident on the substrate without undergoing a large refractive index change, . The upper surface of the substrate 21 may have a roughness R, and light is emitted to the outside through the roughness R. Accordingly, the light extraction efficiency of the light emitting diode can be improved. However, the present invention is not limited thereto, and the roughness R may be omitted, and the upper surface of the substrate 21 may be a flat surface.

The larger the distance from the active layer 23 to the upper surface of the substrate 21, the narrower the directivity angle of light. The distance is not less than 50 mu m, and the upper limit is not particularly limited, but may be, for example, not more than 500 mu m and further not more than 300 mu m. The size of the substrate 21 is not particularly limited and may be variously selected.

In the present embodiment, the substrate 21 is a growth substrate. However, the substrate 21 is not limited thereto, and may be a relatively thick gallium nitride based semiconductor layer grown on a separate growth substrate. Or a continuous layer of the first conductivity type semiconductor layer 23 may be substituted for the substrate. A separate growth substrate can be removed.

In this embodiment, the substrate 21 may have side surfaces perpendicular to the lower surface of the substrate 21 and inclined surfaces with respect to the vertical side surface. In this case, the vertical side is located closer to the upper surface of the substrate 21 than the inclined side. Further, the angle between the vertical side and the inclined side may be approximately 10 degrees or more. The inclination angle of the vertical side can be determined by scribing. When the scribing process using laser is applied, the inclination is steeper than that when the scribing process using the blade is applied. The vertical side may be formed by braking. The sloped side formed by the scribing process may be a rougher side than the vertical side formed by braking. The boundary between the vertical side and the inclined side is indicated by a dotted line. The vertical side surface and the inclined side surface may be formed on all four sides of the substrate 21.

 The first conductivity type semiconductor layer 23 may be disposed on the substrate 21. In particular, the first conductivity type semiconductor layer 23 is disposed adjacent to the inclined side surface of the substrate 21. The first conductive semiconductor layer 23 may be a layer grown on the substrate 21 and may be a gallium nitride-based semiconductor layer. The first conductive semiconductor layer 23 may be a gallium nitride-based semiconductor layer doped with an impurity, for example, Si. Here, it is described that the first conductive type semiconductor layer 23 is distinguished from the substrate 21, but the boundary therebetween may not be clearly distinguished. Particularly, when the substrate 21 is made of the same material as the first conductivity type semiconductor layer 23, the boundary between the substrate 21 and the first conductivity type semiconductor layer 23 is difficult to distinguish clearly. Meanwhile, as shown in the figure, a part of the inclined side surface may include the first conductivity type semiconductor layer 23.

A mesa (M) is disposed on the first conductivity type semiconductor layer (23). The mesa M may be located within the region surrounded by the first conductivity type semiconductor layer 23 so that the regions near the edges of the first conductivity type semiconductor layer are not covered by the mesa M, Can be exposed.

The mesa M includes a second conductivity type semiconductor layer 27 and an active layer 25. In addition, the mesa M may include a thickness of the first conductivity type semiconductor layer 23. The active layer 25 is interposed between the first conductivity type semiconductor layer 23 and the second conductivity type semiconductor layer 27. The active layer 25 may have a single quantum well structure or a multiple quantum well structure. The composition and thickness of the well layer in the active layer 25 determine the wavelength of the generated light. In particular, by controlling the composition of the well layer, it is possible to provide an active layer that generates ultraviolet light, blue light or green light.

On the other hand, the second conductivity type semiconductor layer 27 may be a p-type impurity, for example, a gallium nitride based semiconductor layer doped with Mg. Although the first conductive semiconductor layer 23 and the second conductive semiconductor layer 27 may each be a single layer, the present invention is not limited thereto, and may be a multiple layer or a superlattice layer. The first conductivity type semiconductor layer 23, the active layer 25 and the second conductivity type semiconductor layer 27 are formed by a known method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) And may be formed on the substrate 21 by growing.

The mesa M has a side inclined so that the area becomes narrower as the distance from the first conductivity type semiconductor layer 23 increases. The inclination of the mesa M may be more gentle than the inclination of the side surface of the substrate 21. [ However, the present invention is not limited thereto, and the inclined side surface of the substrate 21 may be more gentle than the side surface of the mesa M.

The mesa M may include a through hole 30a through the second conductivity type semiconductor layer 27 and the active layer 25 to expose the first conductivity type semiconductor layer 23. The through hole 30a is surrounded by the second conductivity type semiconductor layer 27 and the active layer 25. The mesa M has a generally rectangular shape and may have a shape in which the edges are cut. The mesa M may further include a depression 30b for exposing the first conductivity type semiconductor layer 23. The depressed portion 30b is partially surrounded by the second conductivity type semiconductor layer 27 and the active layer 25. The depressions 30b may be disposed on all four sides of the mesa M, but the present invention is not limited thereto and may be limited to one to three sides. The side wall of the through hole 30a and the depression 30b may be inclined in a manner similar to the side surface of the mesa M. In addition, the inclination of these side walls may be more gentle than the side inclination of the substrate 21. [

On the other hand, the ohmic reflective layer 31 is disposed on the mesa M and contacts the second conductive type semiconductor layer 27. The ohmic reflective layer 31 may be disposed over substantially the entire area of the mesa M in the mesa M upper region. For example, the ohmic reflective layer 31 may cover 80% or more of the upper region of the mesa (M), and moreover, 90% or more.

The OMR reflective layer 31 may include a reflective metal layer so that the light generated in the active layer 25 and traveling to the OMR reflective layer 31 can be reflected to the substrate 21 side. For example, the ohmic reflective layer 31 may be formed of a single reflective metallic layer, but is not limited thereto, and may include an ohmic layer and a reflective layer. As the ohmic layer, a metal layer such as Ni may be used, and as the reflective layer, a metal layer having high reflectance such as Ag or Al may be used. The ohmic reflective layer 31 may also include a barrier layer and may include, for example, Ni, Ti, and Au. For example, the ohmic reflective layer may have a stacked structure of Ni / Ag / Ni / Ti / Ni / Ti / Au / Ti.

In the present embodiment, the description is given of the case where the ohmic reflective layer 31 is a multilayer structure of metal layers, but the present invention is not limited thereto. For example, a transparent oxide layer such as ITO or ZnO may be formed as an ohmic layer, a reflective layer such as Ag or Al may be formed thereon, or a dielectric layer such as an SiO2 layer may be disposed between the transparent oxide layer and the reflective layer . However, the dielectric layer provides a passageway allowing electrical connection between the transparent oxide layer and the reflective layer. By arranging a dielectric layer such as SiO2 between the transparent oxide layer and the metal reflective layer, the reflectivity of the ohmic reflective layer can be further increased.

On the other hand, the ohmic oxide layer 29 may cover the mesa M around the ohmic reflective layer 31. The ohmic oxide layer 29 may be formed of a transparent oxide layer such as indium tin oxide (ITO) or ZnO. The side of the ohmic oxide layer 29 may be generally parallel to the side of the mesa M. [ By disposing the ohmic oxide layer 29 around the ohmic reflective layer 31, the ohmic contact region can be widened, thereby reducing the forward voltage of the light emitting diode.

The lower insulating layer 33 covers the mesa M, the ohmic oxide layer 29 and the ohmic reflective layer 31. The lower insulating layer 33 may cover the mesa M side along the mesa M and may cover a part of the first conductivity type semiconductor layer 23 exposed around the mesa M. [ The lower insulating layer 33 covers the side wall of the through hole 30a in the through hole 30a and covers the side wall of the recess 30b.

The lower insulating layer 33 has a first opening 33a for exposing the first conductivity type semiconductor layer and a second opening 33b for exposing the ohmic reflective layer 31. [ The first opening 33a may be disposed in the through hole 30a and the recess 30b. In addition, the lower insulating layer 33 may expose the first conductivity type semiconductor layer 23 along the mesa M.

The second opening 33b of the lower insulating layer 33 exposes the ohmic reflective layer 31. A plurality of second openings 33b may be formed and these second openings 33b may be disposed near one side edge of the mesa M. [

The lower insulating layer 33 may be formed of a single layer of SiO ₂ or Si ₃ N ₄ , but is not limited thereto. For example, the lower insulating layer 33 may have a multilayer structure including a silicon nitride film and a silicon oxide film, and may include a distributed Bragg reflector in which dielectric layers having different refractive indexes are alternately stacked, such as a silicon oxide film and a titanium oxide film have.

The first pad metal layer 35a is disposed on the lower insulating layer 33 and is insulated from the mesa M and the ohmic reflective layer 31 by the lower insulating layer 33. [ The first pad metal layer 35a contacts the first conductive semiconductor layer 23 through the first openings 33a of the lower insulating layer 33. [ The first pad metal layer 35a has an external contact portion that contacts the first conductivity type semiconductor layer 23 around the mesa M and an internal contact portion that contacts the first conductivity type semiconductor layer 23 in the through hole 30a. . ≪ / RTI > The external contact portion may be formed near the concave portion 30a formed around the mesa M and may also be formed near the four corners of the mesa M. [ At least one of the inner contact portion and the outer contact portion may be used. By using both of them, the current dispersion performance of the light emitting diode can be improved.

The second pad metal layer 35b is disposed on the upper portion of the mesa M on the lower insulating layer 33 and electrically connected to the ohmic reflective layer 31 through the second openings 33b of the lower insulating layer 33 Respectively. The second pad metal layer 35b may be surrounded by the first pad metal layer 35a and a boundary region 35ab may be formed therebetween. The lower insulating layer 33 is exposed in the boundary region 35ab and the boundary region 35ab is covered with the upper insulating layer 37 described later.

The first pad metal layer 35a and the second pad metal layer 35b may be formed of the same material in the same process. The first and second pad metal layers 35a and 35b may include an ohmic reflective layer such as an Al layer and the ohmic reflective layer may be formed on an adhesive layer such as Ti, Cr, or Ni. Further, a protective layer of a single layer or a multiple layer structure such as Ni, Cr, Au or the like may be formed on the ohmic reflective layer. The first and second pad metal layers 35a and 35b may have a multilayer structure of Cr / Al / Ni / Ti / Ni / Ti / Au / Ti, for example.

The upper insulating layer 37 covers the first and second pad metal layers 35a and 35b. The upper insulating layer 37 may cover the first conductive semiconductor layer 23 along the mesa M. However, the upper insulating layer 37 may expose the first conductivity type semiconductor layer 23 along the edge of the substrate 21.

The upper insulating layer 37 has a first opening 37a exposing the first pad metal layer 35a and a second opening 37b exposing the second pad metal layer 35b. The first opening 37a and the second opening 37b may be disposed in the upper region of the mesa M and may be arranged to face each other. In particular, the second opening 37b may be confined within the upper region of the second pad metal layer 35b.

Although the second opening 37b is shown and described as exposing all the upper regions of the second openings 33b of the lower insulating layer 33 in the present embodiment, the second openings 37b of the upper insulating layer, And the second openings 33b of the lower insulating layer 33 may be spaced apart from each other in the horizontal direction. That is, the second openings 33b may be disposed outside the second openings 37b, and the plurality of second openings 37b may be disposed horizontally spaced apart from the second openings 33b have.

The upper insulating layer 37 may be formed of a single layer of SiO ₂ or Si ₃ N ₄ , but is not limited thereto. For example, the upper insulating layer 37 may have a multilayer structure including a silicon nitride film and a silicon oxide film, and may include a distributed Bragg reflector in which dielectric layers having different refractive indexes are alternately stacked, such as a silicon oxide film and a titanium oxide film have.

On the other hand, the first bump pad 39a is in electrical contact with the first pad metal layer 35a exposed through the first opening 37a of the upper insulating layer 37, and the second bump pad 39b is electrically connected to the second And is in electrical contact with the exposed second pad metal layer 35b through the opening 37b. As shown in Figs. 1 and 2, the first bump pad 39a and the second bump pad 39b may be positioned within the first opening 37a and the second opening 37b, respectively, The first openings 37a and the second openings 37b may be all covered and sealed.

The first bump pad 39a is electrically connected to the first conductivity type semiconductor layer 23 through the first pad metal layer 35a and the second bump pad 39b is electrically connected to the second pad metal layer 35b and the ohmic reflective layer 35b. And is electrically connected to the second conductivity type semiconductor layer 27 through the second conductive type semiconductor layer 31. The second pad metal layer 35b may be omitted and the second bump pad 39b may be directly connected to the ohmic reflective layer 31. [

As shown in Fig. 1, the second bump pad 39b may be located within the upper region of the second pad metal layer 35a. However, the present invention is not limited thereto, and a part of the second bump pad 39b may overlap with the first pad metal layer 35a. However, an upper insulating layer 37 is disposed between the first pad metal layer 35a and the second bump pad 39b to isolate them.

On the other hand, the side reflective layer 41 is disposed on the side surfaces of the substrate 21. The side reflective layer 41 covers the vertical side as well as the inclined side of the substrate 21. The side reflective layer 41 may also cover the side surface of the first conductive type semiconductor layer 23.

The side reflection layer 41 may cover all four sides of the substrate 21, but the present invention is not limited thereto and may cover one to three sides.

On the other hand, the side reflective layer 41 is spaced apart from the mesa M in the lateral direction. Further, as shown in the enlarged portion of FIG. 2, the side reflective layer 41 is laterally spaced from the first pad metal layer 35a. In particular, the side reflective layer 41 may be located above the upper surface of the mesa M and therefore above the exposed surface of the first conductive semiconductor layer 23 around the mesa M. For example, the lower end of the side reflective layer 41 may be parallel to the exposed surface of the first conductive type semiconductor layer 23, and may be positioned above the exposed surface of the first conductive type semiconductor layer 23, can do. A part of the exposed surface of the first conductivity type semiconductor layer 23 around the mesa M may be exposed to the outside between the side reflective layer 41 and the upper insulating layer 37. [

The side reflective layer 41 may comprise a metal reflective layer of Ag or Al, and a barrier layer such as Ni and / or Ti may be disposed on the metal reflective layer. Further, an oxidation preventing film such as Au may be disposed on the barrier layer for preventing oxidation. In addition, Ni and Mo may be included in the barrier layer. Further, an adhesive layer such as Ni or Ti may be disposed between the metal reflection layer and the substrate 21 to improve the adhesion property of the metal reflection layer. For example, the side reflection layer 41 may be formed of a material selected from the group consisting of Ni / Ag / Ni / Ti / Au, Ni / Ag / Ni / Mo / Ni / Mo, or Ni / Ag / Can be used. Furthermore, the side reflection layer 41 is not limited to the metal reflection layer, and may include a distributed Bragg reflector (DBR) or an omni-directional reflector (ODR).

The side reflective layer 41 is disposed on the side surfaces of the substrate 21 and the first conductivity type semiconductor layer 23 to prevent the side reflective layer 41 from being directly connected to the first pad metal layer 35a Therefore, it is possible to reduce the electrical interference caused by the side reflective layer 41.

When the side reflective layer 41 includes a metal reflective layer and the metal reflective layer overlaps the first pad metal layer 35a, undesirable defects such as pinholes or cracks in the upper insulating layer 37 may cause undesired side reflection layer 41, May be electrically connected directly to the first pad metal layer 35a. In this case, the electrical characteristics of the light emitting diode, such as the forward voltage, can be drastically changed depending on whether the side reflective layer 41 and the first pad metal layer 35a are in contact with each other, Lt; / RTI > In contrast, according to the embodiment of the present invention, light emitting diodes having small electrical characteristic variations can be manufactured in large quantities by separating the side reflective layer 41 from the first pad metal layer 35a.

On the other hand, the roughness reducing layer 53 is interposed between the side surface of the substrate 21 and the side reflective layer 41. The roughness reducing layer 53 may cover both the vertical side surface and the inclined side surface of the substrate 21. Further, the roughness reducing layer 53 may be laterally spaced from the mesa M like the side reflective layer 41. The roughness reducing layer 53 may cover an area substantially similar to the side reflective layer 41 and may be located on the side of the substrate 21 so as to expose the upper and lower surfaces of the substrate 21.

Further, in the present embodiment, the roughness reducing layer 53 may be spaced apart from the upper insulating layer 37 and the lower insulating layer 33.

The roughness reducing layer 53 may be formed of a transparent oxide layer or a nitride layer such as an ITO or SiO2 layer. The roughness reducing layer 53 may be formed so that the surface roughness Ra is 2 nm or less. The roughness reducing layer 53 may also function as an adhesive layer for improving the adhesion of the side reflective layer 41. [

When the sapphire substrate is ground, a rough surface is formed such that it is difficult to measure the surface roughness. When the metal reflection layer was formed on such a rough surface, light (wavelength: 450 nm) was incident on the sapphire substrate side, and the reflectance of the metal reflection layer was measured. As a result, it was confirmed that the reflectance was about 50%. However, when the SiO 2 layer was formed before forming the metal reflection layer to have a surface roughness (Ra) of about 2 nm, it was confirmed that the reflectance of the metal reflection layer increased to about 70%.

That is, by forming a roughness-reducing layer such as an ITO or SiO2 layer on a rough surface, the reflectivity of the metal reflection layer formed thereon can be improved.

Further, by disposing a transparent roughness reducing layer 53 between the side reflective layer 41 and the substrate 21, an omni directional reflector (ODR) may be formed.

3 is a schematic cross-sectional view illustrating a light emitting diode 200 according to another embodiment of the present invention.

Referring to FIG. 3, the light emitting diode 200 according to the present embodiment is substantially similar to the light emitting diode 100 described with reference to FIGS. 1 and 2, except that the upper insulating layer 37 is inclined And serves as a roughness reducing layer to cover the side surface.

That is, the upper insulating layer 37 covers all of the first conductivity type semiconductor layer 23 exposed around the mesa M and further covers the side surface of the first conductivity type semiconductor layer 23 and the side surface of the substrate 21 Cover the side of the picture. However, the upper insulating layer 37 does not cover the vertical side surface of the substrate 21.

On the other hand, the side reflection layer 41 can directly contact the vertical side surface of the substrate 21 and covers the upper insulation layer 37 on the inclined side surface. In this case, the lower end of the side reflective layer 41 may be parallel to the exposed surface of the first conductive type semiconductor layer 23, but may be located lower than the exposed surface of the first conductive type semiconductor layer 23 as indicated by a dotted line. However, the lower end of the side reflective layer 41 is aligned with or above the horizontal plane of the upper insulating layer 37.

4 is a schematic cross-sectional view illustrating a light emitting diode 300 according to another embodiment of the present invention.

Referring to FIG. 4, the light emitting diode 300 according to the present embodiment is substantially similar to the light emitting diode 100 described with reference to FIGS. 1 and 2, And the other is located closer to the side. The inclined side surface may be adjacent to the upper surface of the substrate 21, and the vertical side surface may be adjacent to the first conductive type semiconductor layer 23.

On the other hand, the vertical side surface and the inclined side surface are covered with the side reflective layer 41, and the roughness reducing layer 53 is interposed between the side surface of the substrate 21 and the side reflective layer 41.

Since the inclined side face is disposed on the upper surface side of the substrate 21, the light emitting diode 300 according to the present embodiment can have a narrower directional angle than the light emitting diode 100 of FIGS.

5 is a schematic cross-sectional view illustrating a light emitting diode 400 according to another embodiment of the present invention.

5, the light emitting diode 400 according to the present embodiment is substantially similar to the light emitting diode 300 described with reference to FIG. 4, except that the side reflecting layer 41 and the roughness reducing layer 53 are formed on the substrate 21, As shown in Fig. That is, the side reflective layer 41 extends to the upper surface of the substrate 21 and covers the upper surface of the substrate 21 along the upper surface edge of the substrate 21. The roughness reducing layer 53 also extends to the upper surface side of the substrate 21 and is interposed between the side surface reflecting layer 41 and the upper surface of the substrate. In this embodiment, the roughness reducing layer 53 is partially formed on the upper surface of the substrate 21.

The light emitting diode 400 according to the present embodiment can have a narrower directivity angle than the light emitting diode 300 because the side reflective layer 41 covers the edge of the upper surface of the substrate 21. [

6 is a schematic cross-sectional view illustrating a light emitting diode 500 according to another embodiment of the present invention.

Referring to FIG. 6, the light emitting diode 500 according to the present embodiment is substantially similar to the light emitting diode 400 described with reference to FIG. 5, but differs in the arrangement of the roughness reducing layer 53.

That is, in this embodiment, the roughness reducing layer 53 covers the inclined side surface of the substrate 21, but does not cover the vertical side surface. Further, the roughness reducing layer 53 may cover the entire upper surface of the substrate 21. [ On the other hand, the side reflecting layer 41 can directly contact the vertical side surface and covers the roughness reducing layer 53 on the inclined side surface.

In this embodiment, the roughness R on the upper surface of the substrate 21 may be omitted, but is not limited thereto.

7 is a schematic cross-sectional view illustrating a light emitting diode 600 according to another embodiment of the present invention.

7, the light emitting diode 600 according to the present embodiment is substantially similar to the light emitting diode 100 described with reference to FIG. 6, except that the side reflective layer 41 is formed on the substrate (not shown) along the edge of the upper surface of the substrate 21. [ 21) is partially covered.

The orientation angle of the light emitting diode can be adjusted by making the side reflective layer 41 cover the upper surface of the substrate 21. [

8 is a schematic cross-sectional view illustrating a light emitting diode 700 according to another embodiment of the present invention.

8, the light emitting diode 700 according to the present embodiment is substantially similar to the light emitting diode 100 described with reference to FIGS. 1 and 2, except that the side surface of the substrate 21 is a vertical side surface . The side reflecting layer 41 and the roughness reducing layer 53 are formed on the vertical side.

Although the side reflecting layer 41 and the roughness reducing layer 53 are shown as being limited on the side surface of the substrate 21 in the present embodiment, The upper surface of the base 21 may be partially covered.

9 to 17 are plan views and sectional views for explaining a method of manufacturing a light emitting diode according to an embodiment of the present invention. Figures 9a, 10a, 11a, 12a, 13a, 14a, 15a and 16a are plan views and Figures 9b, 10b, 11b, 12b, 13b, 14b, 15b and 16b are cross-sectional views taken along the perforations A-

9A and 9B, a semiconductor laminated layer 30 including a first conductive type semiconductor layer 23, an active layer 25, and a second conductive type semiconductor layer 27 is formed on a substrate 21, And an ohmic oxide layer 29 is formed thereon.

The substrate 21 may be a sapphire substrate or a gallium nitride-based substrate. For a gallium nitride substrate, for example, n-type impurity doping concentration to be 7E17 ~ 9E17 / cm ^3. On the other hand, the first conductive type semiconductor layer 23 is an n-type impurity doping concentration be, for 9E18 ~ 2E19 / cm ³ g.

The first conductivity type semiconductor layer 23, the active layer 25 and the second conductivity type semiconductor layer 27 are formed by a known method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) Gt; can be grown on the substrate 21 within the substrate.

On the other hand, the ohmic oxide layer 29 may be formed of, for example, ITO or ZnO. The ohmic oxide layer 29 may be formed by an electron beam evaporation method or a sputtering method. The ohmic oxide layer 29 may cover the second conductivity type semiconductor layer 27 and make ohmic contact with the second conductivity type semiconductor layer 27.

Referring to FIGS. 10A and 10B, the mesa M is formed by patterning the ohmic oxide layer 29 and the semiconductor stack 30. As the mesa M is formed, the first conductivity type semiconductor layer 23 is exposed around the mesa M. The mesa M has a through hole 30a and a concave portion 30b, and may be formed so that the corners have a cut shape. The ohmic oxide layer 29 almost covers the upper portion of the mesa M and has the same planar shape as the mesa M. [

In this embodiment, the ohmic oxide layer 29 may be patterned using a wet etch process using a photoresist pattern, and the semiconductor stack 30 may be patterned using a dry etch process. However, the present invention is not limited thereto, and the ohmic oxide layer 29 and the semiconductor stacked layer 30 may be patterned using a dry etching process. On the other hand, in the patterning process of the ohmic oxide layer 29 and the semiconductor laminate 30, the same photoresist pattern can be continuously used.

11A and 11B, the ohmic oxide layer 29 is patterned to expose the second conductivity type semiconductor layer 27, and the ohmic reflective layer 31 is formed in the exposed region. The ohmic reflective layer 31 includes a metal reflective layer such as Ag or Al, and may include an ohmic metal layer such as Ni. Since the material of the ohmic reflective layer 31 has been described above with reference to FIGS. 1 and 2, detailed description thereof is omitted in order to avoid duplication. The OMR reflective layer 31 may be formed using an electron beam evaporation method or sputtering.

12A and 12B, a lower insulating layer 33 covering the ohmic oxide layer 29 and the ohmic reflective layer 31 is formed. The lower insulating layer 33 also covers the side surface of the through hole 30a, covering the side surface of the mesa M. [ The lower insulating layer 31 has a first opening 33a for exposing the first conductivity type semiconductor layer 23 and a second opening 33b for exposing the ohmic reflective layer 31.

The first opening 33a may be formed in the through hole 30a, for example, and may be formed in the vicinity of the concave portion 30b. Further, the lower insulating layer 33 may cover a portion of the first conductivity type semiconductor layer 23 along the mesa M. Accordingly, the first conductivity type semiconductor layer 23 may be partially exposed along the periphery of the mesa M.

The second opening 33b is located on the mesa M on the ohmic reflective layer 31. [ The plurality of second openings 33b may be distributed to one side of the mesa M. [ And the ohmic reflective layer 31 is exposed through the second opening 33b. In this embodiment, five second openings 33b are shown, but the present invention is not limited thereto. One second openings 33b may be formed, and two or more second openings 33b may be formed. .

Referring to FIGS. 13A and 13B, a first pad metal layer 35a and a second pad metal layer 35b are formed on the lower insulating layer 33. FIG. The first pad metal layer 35a is electrically connected to the first conductive semiconductor layer 23 exposed through the first opening 33a and the second pad metal layer 35b is exposed to the second openings 33b And is electrically connected to the formed ohmic reflective layer 31.

The first pad metal layer 35a can be connected to the first conductivity type semiconductor layer 23 through the first openings 30a near the through holes 30a and the recesses 30b, And can be connected to the first conductivity type semiconductor layer 23 near the edges. The first pad metal layer 35a has an inner contact portion which contacts the first conductivity type semiconductor layer 23 through the through hole 30a and an outer contact portion which contacts the first conductivity type semiconductor layer 23 around the mesa M. [ . The first pad metal layer 35a has internal contacts and external contacts to evenly distribute current across the entire region of the mesa M. [

The second pad metal layer 35b may be surrounded by the first pad metal layer 35a and the boundary region 35ab may be formed between the first pad metal layer 35a and the second pad metal layer 35b . The second pad metal layer 35b covers the second openings 33b and may be located on the mesa M region.

The first pad metal layer 35a and the second pad metal layer 35b may be formed of the same material using, for example, a lift-off process, and thus may be disposed on the same level.

 14A and 14B, an upper insulating layer 37 is formed on the first pad metal layer 35a and the second pad metal layer 35b. The upper insulating layer 37 has a first opening 37a and a second opening 37b exposing the first pad metal layer 35a and the second pad metal layer 35b. The upper insulating layer 37 may cover the lower insulating layer 33 around the mesa M and may expose the first conductive semiconductor layer 23 along the mesa M. [ The outer contact portions of the concave portion 30b of the mesa M and the first pad metal layer 35a formed near the edges are also covered with the upper insulating layer 37. [

On the other hand, the second opening 37b may be located within the upper region of the second pad metal layer 35b. The first opening 37a is located within the upper region of the first pad metal layer 35a and may be located within the upper region of the mesa M although not necessarily limited thereto. The first opening 37a and the second opening 37b are spaced apart from each other.

Although the first and second openings 37a and 37b are formed one by one in this embodiment, a plurality of first openings 37a and a plurality of second openings 37b are formed .

Although the second openings 37b are formed on the second openings 33b of the lower insulating layer 33 and overlap each other, the second openings 33b may extend from the second openings 37b to the horizontal Direction and may not overlap with each other.

15A and 15B, a first bump pad 39a and a second bump pad 39b are formed in the first and second openings 37a and 37b of the upper insulating layer 37. Referring to FIG. The first and second bump pads 39a and 39b may be formed of, for example, AuSn. The first and second bump pads 39a and 39b are pads bonded to the submount or the lead frame when the light emitting diode is mounted on the submount or the lead frame. The first and second bump pads 39a and 39b may be formed using known techniques such as lift off.

Although the first and second bump pads 39a and 39b are formed in the first and second openings 37a and 37b, respectively, in the present embodiment, the present invention is not limited thereto, 2 openings 37a and 37b may be completely covered and sealed.

16A and 16B, after the first and second bump pads 39a and 39b are formed, the lower surface of the substrate 21 is polished to reduce the thickness of the substrate 21, Thereby forming a varnish (R). The lower surface of the substrate 21 may be polished using a lapping and / or polishing technique, and a roughness R may be formed using dry and wet etching techniques. In some embodiments, the process of forming the roughness R may be omitted.

Next, a description will be given of a technique of forming the side reflective layer 41 on the side surface of the substrate 21 with reference to FIG. 17 shows schematic cross-sectional views for explaining a method of forming a side reflective layer 41 of a light emitting diode 100 according to an embodiment of the present invention. Although FIG. 17 shows two light emitting diode regions manufactured with reference to FIGS. 9 to 16, a larger number of light emitting diode regions may be formed on the substrate 21, and a mesa M may be formed in each light emitting diode region. And bump pads 39a and 39b are formed.

17A, after the first and second bump pads 39a and 39b are formed, a scribing line LS is formed in the substrate 21 from the first conductivity type semiconductor layer 21 side. The scribing lines LS are formed in the divided regions of the light emitting diodes, so that a plurality of scribing lines LSs can be formed on the substrate 21 in a mesh shape. The scribing line LS may be formed using a laser, or may be formed using a blade.

On the other hand, a masking material 51, for example, is coated on the substrate 21 on which the roughness R is formed, for example. The masking material 51 may be formed on the substrate 21 using a technique such as spin coating. The masking material 51 may be formed of, for example, a photoresist film.

Referring to FIG. 17B, the individual light emitting diode regions may be separated from each other by braking on a stretchable tape such as a blue tape and separating the individual light emitting diode regions. Thereafter, the separated individual light emitting diode regions can be transferred and adhered onto the support 61. For example, as the support 61, a polymer, a polyimide film, or another supporting substrate may be used. The individual light emitting diode regions can be transferred to a polymer or polyimide film, or can be individually attached or transferred to a support substrate or the like. At this time, the mesa M may be buried in the support 61, and thus the first conductivity type semiconductor layer 23 exposed around the mesa M may be in contact with the upper surface of the support 61. However, the present invention is not limited to this, and a portion of the light emitting diode region in contact with the support 61 may be adjusted, and a part of the thickness of the first conductivity type semiconductor layer 23 may be buried in the support 61.

On the other hand, the side surface of the substrate 21 of the individual light emitting diode region may be formed with a tilted side formed by laser scribing and a vertical surface formed by braking. The inclined side formed by the scribing line LS is formed as a rougher surface relative to the vertical side formed by braking. To improve the roughness of such a rough surface, it is possible to etch the surface with phosphoric acid or hydrochloric acid, but there is a limit to improve the surface roughness.

Referring to FIG. 17C, a roughness reducing layer 53 is deposited on the individual light emitting diode regions, and then a side reflective layer 41 is deposited. The roughness reducing layer 53 may be deposited, for example, with ITO or SiO2 using plasma enhanced chemical vapor deposition (PECVD) or sputtering techniques, for example. The side reflective layer 41 includes a metal reflective layer such as Ag or Al. Since the specific structure and material of the side reflective layer 41 are the same as those described with reference to FIGS. 1 and 2, detailed description thereof is omitted in order to avoid duplication.

The roughness reducing layer 53 and the side reflecting layer 41 are formed on the side surface of the substrate 21 with a substantially uniform thickness on the inclined side surface and the vertical side surface. The roughness reducing layer 53 and the side reflective layer 41 are formed on the exposed surface of the first conductivity type semiconductor layer 23 because the exposed surface of the first conductivity type semiconductor layer 23 is covered with the support 61 . Therefore, it is possible to prevent the side reflective layer 41 from overlapping with the first pad metal layer 35a.

17D, the side reflective layer 41 formed on the substrate 21 can be removed by removing the masking material 51, and the light emitting diode 100 is completed by separating the side reflective layer 41 from the support 61. [

On the other hand, in the present embodiment, the scribing line LS may be formed using a laser, or may be formed using a blade. When the blade is used, the inclination of the inclined surface of the side surface of the substrate 21 can be made more gentle.

Although the scribing line LS is described as being formed after the first and second bump pads 39a and 39b are formed in the present embodiment, the scribing line LS may be formed on the upper insulating layer 37 may be formed. In this case, the upper insulating layer 37 may be formed inside the scribing line LS, and thus the light emitting diode 200 as in the embodiment of FIG. 3 can be manufactured.

The side surface reflection layer 41 and the roughness reducing layer 53 may partially cover the upper surface of the substrate 21 along the edge of the upper surface of the substrate 21 by previously patterning the masking material 51.

The roughness reducing layer 53 and the side reflective layer 41 formed on the substrate 21 are removed by using the lift-off technique using the masking material 51 in the present embodiment. However, the present invention is not necessarily limited thereto, and various other techniques such as a peel-off technique can be used to remove the roughness reducing layer 53 and the side reflective layer 41 formed on the upper surface of the substrate 21 .

18 is a cross-sectional view illustrating a method of fabricating a light emitting diode 300 according to another embodiment of the present invention. Light emitting diode regions are formed on the substrate 21 as described above with reference to FIGS. 9 to 16, and mesa M and bump pads 39a and 39b are formed in each light emitting diode region.

18A, after the first and second bump pads 39a and 39b are formed, a masking material 51, for example, is coated on the substrate 21 on which the roughness R is formed. The masking material 51 may be formed on the substrate 21 using a technique such as spin coating.

Thereafter, a scribing line LS is formed on the upper surface side of the substrate 21, that is, inside the substrate 21 from the masking material 51 side. The scribing lines LS are formed in the divided regions of the light emitting diodes, so that a plurality of scribing lines LSs can be formed on the substrate 21 in a mesh shape. The scribing line may be formed by using a laser, and may be formed by removing a debris formed on the side surface of the substrate 21 and removing the debris from the surface of the substrate 21 generated by the laser, A chemical treatment such as treatment can be performed.

Referring to FIG. 18B, individual LED regions may be separated from each other by separating the individual LED regions on an expandable tape such as a blue tape, as described with reference to FIG. 17B. Thereafter, the separated individual light emitting diode regions are transferred and adhered onto the support 61.

On the other hand, the side surface of the substrate 21 of the individual light emitting diode region may be formed with a sloped surface formed by laser scribing and a vertical surface formed by braking.

Referring to FIG. 18C, a roughness reducing layer 53 and a side reflective layer 41 are deposited on the individual light emitting diode regions. The roughness reducing layer 53 may be deposited using a PECVD or sputtering technique and the side reflective layer 41 may be deposited using, for example, a sputtering technique. The roughness reducing layer 53 includes, for example, an ITO or SiO2 layer, and the side reflecting layer 41 includes a metal reflecting layer such as Ag or Al. Since the specific structure and material of the side reflective layer 41 are the same as those described with reference to FIGS. 1 and 2, detailed description thereof is omitted in order to avoid duplication.

The roughness reducing layer 53 and the side reflection layer 41 may be formed on the side surface of the substrate 21 with a substantially uniform thickness on the inclined side surface and the vertical side surface. The exposed surface of the first conductivity type semiconductor layer 23 is covered with the support 61 so that the roughness reducing layer 53 and the side reflection layer 41 are formed on the exposed surface of the first conductivity type semiconductor layer 23 . Therefore, it is possible to prevent the side reflective layer 41 from overlapping with the first pad metal layer 35a, and the roughness relaxed layer 53 is also horizontally spaced from the mesa M.

18D, the side reflective layer 41 formed on the substrate 21 can be removed by removing the masking material 51, and the light emitting diode 300 is completed by separating the side reflective layer 41 from the support 61.

On the other hand, in the present embodiment, the formation of the scribing line LS using a laser has been described. However, the scribing line LS may be formed using a blade. In this case, the inclination of the inclined surface of the side surface of the substrate 21 can be made more gentle.

Although the masking material 51 covers the entire surface of the substrate 21 in this embodiment, the masking material 51 may be patterned to expose the scribing line before performing the scribing process. You may. Thus, the upper surface of the substrate 21 can be exposed near the scribing line LS. As a result, the roughness reducing layer 53 and the side reflective layer 41 may cover the upper surface of the substrate 21 exposed along the edge of the substrate 21, and thus the light emitting diode 400 of FIG. 5 may be provided .

In the present embodiment, the removal of the roughness reducing layer 53 and the side reflective layer 41 deposited on the upper surface of the substrate 21 is explained by using the lift-off technique using the masking material 51, or may be removed using peel-off techniques.

19 is a schematic cross-sectional view illustrating a method of manufacturing a light emitting diode 600 according to another embodiment of the present invention.

Light emitting diode regions are formed on the substrate 21 as described above with reference to FIGS. 9 to 16, and mesa M and bump pads 39a and 39b are formed in each light emitting diode region. On the other hand, in this embodiment, the roughness R is omitted, but a roughness may be formed on the upper surface of the substrate 21.

19A, a scribing line LS is formed on the upper surface of the substrate 21 after the first and second bump pads 39a and 39b are formed. The scribing lines LS are formed in the divided regions of the light emitting diodes, so that a plurality of scribing lines LSs can be formed on the substrate 21 in a mesh shape.

Then, the roughness reducing layer 53 covers the upper surface of the substrate 21. The roughness reducing layer 53 is also formed in the scribing lines LS. The roughness reducing layer 53 may be formed using a PECVD or sputtering technique, for example, a SiO2 layer.

Then, for example, a masking material 51 is formed on the substrate 21. The masking material 51 may be formed on the substrate 21 using a technique such as spin coating and then patterned. For example, the masking material 51 may be formed of a photoresist pattern and may be formed to expose the scribing lines LS.

18, a scribing line LS is formed after the masking material 51 is formed. However, in this embodiment, the scribing line LS and the scribing line LS are formed before the masking material 51 is formed. There is a difference in that the roughness reducing layer 53 is formed.

Referring to FIG. 19B, the individual LED regions may be separated from each other by separating the individual LED regions on an expandable tape such as a blue tape, as shown in FIG. 17B. Thereafter, the separated individual light emitting diode regions are transferred and adhered onto the support 61.

On the other hand, the side surface of the substrate 21 of the individual light emitting diode region may be formed with a sloped surface formed by scribing and a vertical surface formed by braking.

Referring to FIG. 19C, a side reflective layer 41 is deposited on the individual light emitting diode regions. The side reflective layer 41 may be deposited using, for example, a sputtering technique. The side reflective layer 41 includes a metal reflective layer such as Ag or Al. Since the specific structure and material of the side reflective layer 41 are the same as those described with reference to FIGS. 1 and 2, detailed description thereof is omitted in order to avoid duplication.

The side reflecting layer 41 can directly contact the vertical side surface and covers the roughness reducing layer 53 on the inclined side surface. Further, the side reflective layer 41 partially covers the roughness reducing layer 53 along the upper surface edge of the substrate 21, and covers the masking material 51. On the other hand, since the exposed surface of the first conductivity type semiconductor layer 23 is covered with the support 61, the side reflective layer 41 is prevented from being formed on the exposed surface of the first conductivity type semiconductor layer 23. Therefore, it is possible to prevent the side reflective layer 41 from overlapping with the first pad metal layer 35a.

19D, the side reflective layer 41 formed on the substrate 21 can be removed by removing the masking material 51, and the light emitting diode 600 is completed by separating the side reflective layer 41 from the support 61.

The masking material 51 is patterned so that the side reflective layer 41 partially covers the roughness reducing layer 53 along the edge of the upper surface of the substrate 21. However, The upper surface of the substrate 21 may be entirely covered. Accordingly, the side reflective layer 41 can be provided with the light emitting diode 500 defined on the side surface of the substrate 21.

On the other hand, in the present embodiment, the formation of the scribing line LS using a laser has been described. However, the scribing line LS may be formed using a blade. In this case, the inclination of the inclined surface of the side surface of the substrate 21 can be made more gentle.

In the present embodiment, the side reflective layer 41 deposited on the upper surface of the substrate 21 is described as being removed using the lift-off technique, but it may also be removed using a peeling technique.

Various techniques for forming the side reflection layer 41 through laser scribing or blade scribing have been described above.

Meanwhile, the substrate 21 may be divided by using a stealth laser forming a focal point inside the substrate 21. In this case, the side surface of the substrate 21 is formed to have a vertical side surface. Therefore, the light emitting diode 700 of FIG. 8 can be manufactured by using the dicing technique using the stealth laser. The roughened surface and the smooth surface may be repeatedly formed up and down along the side surface of the substrate 21 by irradiation with the stealth laser. The roughness reducing layer 53 relaxes the roughness of the roughened surface, Thereby improving the reflectance of the light guide plate 41.

20 is a schematic cross-sectional view illustrating a light emitting module according to an embodiment of the present invention.

Referring to FIG. 20, the light emitting module includes a support substrate 71, a light emitting diode 100, and a wavelength converter 81. In addition, the light emitting module may also include a white barrier layer 75.

The light emitting diode 100 is a light emitting diode described above with reference to FIGS. 1 and 2. The light emitting diode 100 includes first and second bump pads 39a and 39b, Bonded on the support substrate 71 on which the first and second electrodes 73a and 73b are disposed. The support substrate 71 may be, for example, a submount, a printed circuit board, or a lead frame.

On the other hand, a white barrier wall (white wall) 75 may cover the side surface of the light emitting diode 100. The white barrier layer 75 may be formed by mixing, for example, a silicone resin, an epoxy resin, an epoxy molding compound (EMC), or a silicon molding compound (SMC) with TiO ₂ . The white barrier layer 75 may become defective such as cracks over time. Therefore, when the white barrier layer 75 is formed directly on the side surface of the light emitting diode without the side reflective layer 41, light leakage may be caused in which light emitted from the light emitting diode is emitted to the outside through the white barrier layer 75 . However, the present invention can provide the light emitting module without light leakage for a long time by forming the side reflective layer 41 on the side surface of the light emitting diode.

Meanwhile, the wavelength converter 81 may be disposed on the light emitting diode 100. The wavelength converter 81 may be a phosphor sheet, a wavelength converting plate, or the like, but is not limited thereto. The wavelength converter 81 may be formed directly on the light emitting diode 100 by mixing a resin and a phosphor. The wavelength conversion plate 81 may include a ceramic plate phosphor, and may include a phosphor in glass (PIG) or a SiC fluorescent material. Accordingly, the wavelength converter can be prevented from being discolored in a high temperature environment, and a wavelength converter that can be used for a long time can be provided.

The wavelength conversion plate 81 may be attached on the light emitting diode 100 using an adhesive, but it may be attached on the white barrier layer 75 or disposed on other components. Accordingly, the wavelength conversion plate 81 may be disposed above the light emitting diode 100, away from the light emitting diode 100.

In the present embodiment, the light emitting diode 100 is described as an example, but other light emitting diodes 200, 300, 400, 500, 600, or 700 may be used.

The light emitting module according to the present embodiment can be used in automobile head lamps, camera flashes, lights, and the like.

In this embodiment, the wavelength converter 81 is described as being disposed on the light emitting diode 100 in the light emitting module, but the wavelength converter 81 may be directly attached to the light emitting diode 100.

21 is a schematic plan view for explaining a light emitting diode 800 according to yet another embodiment of the present invention, and is a plan view seen from the side of the bump pads 39a and 39b, and Fig. 22 is a cross- Sectional view.

21 and 22, the light emitting diode 800 includes a substrate 21, a first conductive semiconductor layer 23, an active layer 25, a second conductive semiconductor layer 27, an ohmic reflective layer 31 A first pad metal layer 35a, a second pad metal layer 35b, an upper insulating layer 37, a first bump pad 39a, a second bump pad 39b, (41) and a protective layer (43). The light emitting diode 800 also includes a wavelength converter 81 and may include an adhesive 171. The first conductivity type semiconductor layer 23, the active layer 25, and the second conductivity type semiconductor layer 27 form a semiconductor laminate 30. Further, the light emitting diode 800 may further include a transparent ohmic layer 29.

The first conductive semiconductor layer 23, the active layer 25, the second conductive semiconductor layer 27, the ohmic reflective layer 31, the lower insulating layer 33, the first pad metal layer 35a The second pad metal layer 35b, the upper insulating layer 37, the first bump pad 39a, and the second bump pad 39b are similar to those described with reference to FIGS. 1 and 2, A detailed description thereof will be omitted. The mesa M is disposed on the first conductivity type semiconductor layer 23 and the mesa M is similar to that described with reference to FIGS. 1 and 2, and thus a detailed description thereof will be omitted.

On the other hand, the side reflective layer 41 is disposed on the side surfaces of the substrate 21. The side reflective layer 41 covers the vertical side as well as the inclined side of the substrate 21. The side reflective layer 41 may also cover the side surface of the first conductive type semiconductor layer 23. The side reflection layer 41 may cover all four sides of the substrate 21, but the present invention is not limited thereto and may cover one to three sides.

A part of the side reflecting layer 41 may cover the upper surface of the substrate 21 along the edge of the substrate 21, as shown in Fig. The portion of the side reflective layer 41 located on the upper surface of the substrate 21 may be located on the flat surface of the substrate 21 and the roughness R may be located within the region surrounded by the side reflective layer 41 .

On the other hand, as shown in the enlarged part of FIG. 22, the side reflective layer 41 is horizontally spaced from the first pad metal layer 35a. In particular, the side reflective layer 41 may be located above the upper surface of the mesa M and therefore above the exposed surface of the first conductive semiconductor layer 23 around the mesa M. For example, the lower end of the side reflective layer 41 may be parallel to the exposed surface of the first conductive type semiconductor layer 23, and may be positioned above the exposed surface of the first conductive type semiconductor layer 23, can do. A part of the exposed surface of the first conductivity type semiconductor layer 23 around the mesa M may be exposed to the outside between the side reflective layer 41 and the upper insulating layer 37. [

The side reflective layer 41 may comprise a metal reflective layer of Ag or Al, and a barrier layer such as Ni and / or Ti may be disposed on the metal reflective layer. Further, an oxidation preventing film such as Au may be disposed on the barrier layer for preventing oxidation. In addition, Ni and Mo may be included in the barrier layer. The metal reflection layer may have a thickness of 120 nm or more to have sufficient reflection characteristics. Further, an adhesive layer such as Ni or Ti may be disposed between the metal reflection layer and the substrate 21 to improve the adhesion property of the metal reflection layer. The side reflective layer 41 may be in ohmic contact with the substrate 21 and the first conductivity type semiconductor layer 23, but may also be in Schottky contact.

For example, the side reflective layer 41 may be made of Ni / Ag / Ni / Ti / Au, Ni / Ag / Ni / Mo / Ni / Mo, or Ag / Ni / Mo / Ag / SiO2. Furthermore, the side reflective layer 41 is not limited to the metal reflective layer. The side reflective layer 41 may comprise a distributed Bragg reflector (DBR) and may be an Omni directional reflector (ODR) including a transparent oxide layer between the metal reflective layer and the substrate 21. [

The side reflective layer 41 is disposed on the side surfaces of the substrate 21 and the first conductivity type semiconductor layer 23 to prevent the side reflective layer 41 from being directly connected to the first pad metal layer 35a Therefore, it is possible to reduce the electrical interference caused by the side reflective layer 41.

When the side reflection layer 41 includes a metal reflection layer and the metal reflection layer partially overlaps the first pad metal layer 35a, the side reflection layer 41 may be undesirably removed from the side reflection layer 41 may be electrically connected directly to the first pad metal layer 35a. In this case, the electrical characteristics of the light emitting diode, such as the forward voltage, can be drastically changed depending on whether the side reflective layer 41 and the first pad metal layer 35a are in contact with each other, Lt; / RTI > In contrast, according to the embodiment of the present invention, light emitting diodes having small electrical characteristic deviations can be manufactured in a large quantity by separating the side reflective layer 41 in the lateral direction from the mesa M and the first pad metal layer 35a.

On the other hand, the protective layer 43 is disposed on the side reflective layer 41. The protective layer 43 covers the side reflective layer 41 to prevent the wide side of the side reflective layer 41 from being exposed to the outside. The protective layer 43 may also cover a portion of the side reflective layer 41 that covers the edge of the substrate 21.

The protective layer 43 may be formed of an insulating layer such as, for example, SiO2, Si3N4 or TiO2, or a conductive oxide layer such as indium tin oxide (ITO). The insulating layer protects the side reflective layer 41 by blocking solder from bonding with the side reflective layer 41. Further, the conductive oxide layer such as ITO prevents the solder from migrating to the side surface of the light emitting diode 100 because the wettability of the solder is poor.

As shown in Fig. 22, the protective layer 43 has substantially the same shape as that of the side reflective layer 41. As shown in Fig. 22, the lower end of the protective layer 43 is also laterally spaced from the first pad metal layer 35a and the mesa M, similar to the side reflective layer 41. [ In particular, the lower end of the protective layer 43 may be parallel to the lower end of the side reflective layer 41.

The thickness of the protective layer 43 is not particularly limited as long as it can prevent the solder from penetrating. For example, the thickness of the protective layer 43 may be smaller or larger than the thickness of the side reflective layer 41. [

The wavelength converter 81 is disposed on the substrate 21. The wavelength converter 81 may be formed on the substrate 21 using a mixture of a resin and a phosphor or alternatively may be formed on the substrate 21 or on the upper surface of the substrate 21 using an adhesive 171 And may be attached on the side reflective layer 41 or the protective layer 43 formed.

The wavelength converter 81 may include a resin layer containing a phosphor, a wavelength conversion sheet or a ceramic plate phosphor, and may include a phosphor in glass (PIG) or SiC fluorescent material . The ceramic plate phosphor can be used for a long time because no discoloration occurs particularly at high temperatures.

On the other hand, the wavelength converter 81 may include one or more kinds of phosphors. For example, the wavelength converter 81 may include a phosphor that emits yellow, green, or red light by the light generated in the active layer 25. When blue light is emitted from the active layer 25, white light can be realized by a combination of light converted in the wavelength converter 81 and light generated in the active layer 25.

In this embodiment, the light emitting diode 100 that implements white light is described, but the color light of various colors is not limited to white light but may be implemented using the wavelength converter 81. [

23 is a schematic cross-sectional view for explaining a light emitting diode 900 according to another embodiment of the present invention.

23, the light emitting diode 900 according to the present embodiment is substantially similar to the light emitting diode 100 described with reference to FIGS. 21 and 22, except that the upper insulating layer 37 is inclined There is a difference in covering the side.

That is, the upper insulating layer 37 covers all of the first conductivity type semiconductor layer 23 exposed around the mesa M and further covers the side surface of the first conductivity type semiconductor layer 23 and the side surface of the substrate 21 Cover the side of the picture. However, the upper insulating layer 37 does not cover the vertical side of the substrate 21. [

On the other hand, the side reflective layer 41 covers the vertical side of the substrate 21 and covers the upper insulating layer 37 on the inclined side. In this case, the lower end of the side reflective layer 41 may be parallel to the exposed surface of the first conductive type semiconductor layer 23, but may be located lower than the exposed surface of the first conductive type semiconductor layer 23 as indicated by a dotted line. However, the lower end of the side reflective layer 41 is aligned with or above the horizontal plane of the upper insulating layer 37.

24 is a schematic cross-sectional view for explaining a light emitting diode 1000 according to another embodiment of the present invention.

24, the light emitting diode 1000 according to the present embodiment is substantially similar to the light emitting diode 100 described with reference to FIGS. 21 and 22, except that the side reflective layer 41 and the formation position of the protective layer 43 . 21 and 22, the side reflective layer 41 covers a part of the upper surface of the substrate 21, but in this embodiment, the side reflective layer 41 does not cover the upper surface of the substrate 21. Therefore, the upper end of the side reflecting layer 41 is aligned with the upper surface of the substrate 21 or below. The protective layer 43 also does not cover the upper surface of the substrate 21, and the upper end of the protective layer 43 is parallel to or below the upper surface of the substrate 21.

The orientation angle of the light emitting diode can be adjusted by adjusting the formation position of the side reflective layer 41. That is, when the side reflection layer 41 covers the upper surface of the substrate 21 as in the embodiment of FIG. 21, the directivity angle can be further reduced. As in the present embodiment, It is possible to increase the directivity angle in comparison with the embodiment of FIG.

25 is a schematic cross-sectional view for explaining a light emitting diode 1100 according to another embodiment of the present invention.

25, the light emitting diode 1100 according to the present embodiment is substantially similar to the light emitting diode 100 described with reference to FIGS. 21 and 22, except that the vertical and side surfaces of the substrate 21 . 21 and 22, the inclined side surface of the substrate 21 is positioned closer to the side of the bump pads 39a and 39b than the vertical side surface. However, in this embodiment, The photographic side is located closer to the upper surface side of the substrate 21 than the vertical side surface. Further, in this embodiment, the inclined side surface of the substrate 21 may be parallel to the upper surface of the substrate 21. [

On the other hand, the side reflection layer 41 may cover the vertical side surface and the inclined side surface of the substrate 21, and may partially cover the upper surface along the edge of the substrate 21. Further, the protective layer 43 is disposed on the side reflective layer 41 to cover the side reflective layer 41.

26 is a schematic cross-sectional view for explaining a light emitting diode 1200 according to another embodiment of the present invention.

26, the light emitting diode 1200 according to the present embodiment is substantially similar to the light emitting diode 1100 described with reference to FIG. 25, except that the side reflection layer 41 and the protective layer 43 are formed at different positions have. 25, the side reflection layer 41 covers a part of the upper surface of the substrate 21, but the side reflection layer 41 does not cover the upper surface of the substrate 21 in this embodiment. Therefore, the upper end of the side reflecting layer 41 is aligned with the upper surface of the substrate 21 or below. The protective layer 43 also does not cover the upper surface of the substrate 21, and the upper end of the protective layer 43 is parallel to or below the upper surface of the substrate 21.

27 is a schematic cross-sectional view for explaining a light emitting diode 1300 according to another embodiment of the present invention.

Referring to FIG. 27, the light emitting diode 1300 according to the present embodiment is substantially similar to the light emitting diode 100 described with reference to FIGS. 21 and 22, except that the protective layer 43 'is made of resin . The resin layer 43 'covers the side reflective layer 41. The resin layer 43 'may be relatively thicker than the protective layer 43 described above, and thus may be used as a support member of the light emitting diode. Since the resin layer 43 'is relatively thick, it is possible to prevent the solder from covering the side surface of the light emitting diode 1300.

The resin layer 43 'may include an epoxy resin, a silicone resin, an epoxy molding compound (EMC), or a silicone molding compound (SMC). In addition, the resin layer 43 'may be, for example, a white barrier layer. The white barrier layer 43 'may be formed, for example, by mixing silicon resin, epoxy resin, EMC or SMC with TiO ₂ . The white barrier layer 43 'may develop defects such as cracks therein over time. Therefore, when the white barrier layer 43 'is formed directly on the side surface of the light emitting diode 1300 without the side reflection layer 41, light emitted from the light emitting diode is emitted to the outside through the white barrier layer 43' Leakage may occur. However, the present invention can provide the light emitting element without light leakage for a long time by forming the side reflective layer 41 on the side surface of the light emitting diode 1300.

The wavelength converter 81 may be attached on the substrate 21 using an adhesive 171. [ 27, the wavelength converter 81 may be disposed on the resin layer 43 ', but not limited thereto, and the resin layer 43' may cover the side surface of the wavelength converter 81 have.

28 and 29 are plan views and sectional views for explaining a method of manufacturing the light emitting diode 800 according to an embodiment. FIG. 28A is a plan view, and FIG. 28B is a cross-sectional view taken along the cutting line A-A in FIG. 28A.

First, the substrate 21 is subjected to the steps described with reference to Figs. 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B, 15A and 15B, The semiconductor laminate 30 including the first conductivity type semiconductor layer 23, the active layer 25 and the second conductivity type semiconductor layer 27, the ohmic oxide layer 29, the mesa M, A first pad metal layer 35a, a second pad metal layer 35b, an upper insulating layer 37, a first bump pad 39a, and a second bump pad 39b .

28A and 28B, after the first and second bump pads 39a and 39b are formed, the lower surface of the substrate 21 is polished to reduce the thickness of the substrate 21, Thereby forming the roughness (R). The lower surface of the substrate 21 may be polished using a lapping and / or polishing technique, and a roughness R may be formed using dry and wet etching techniques.

The roughness R may be formed on the entire surface of the substrate 21 as described with reference to FIGS. 16A and 16B, but is not limited thereto. As shown in FIGS. 28A and 28B, . A mask may be used to define the area where the roughness R is formed. A flat surface can be formed around the region where the roughness R is formed.

In the present specification, the height of the roughness R is not particularly limited. For example, the roughness R may have a height of 1 um or more. Further, the roughness R is not necessarily required, and may be omitted.

Next, a description will be given of a technique of forming the side reflective layer 41 and the protective layer 43 on the side surface of the substrate 21 with reference to FIG. Although FIG. 29 shows two light emitting diode regions manufactured with reference to FIGS. 28A and 28B, a larger number of light emitting diode regions will be formed on the substrate 21, and mesas (M) and Bump pads 39a and 39b will be formed.

29A, a scribing line LS is formed inside the substrate 21 from the side of the first conductivity type semiconductor layer 21 after the first and second bump pads 39a and 39b are formed. The scribing lines LS are formed in the divided regions of the light emitting diodes, so that a plurality of scribing lines LSs can be formed on the substrate 21 in a mesh shape.

A photoresist pattern 51 is formed on the substrate 21 on which the roughness R is formed. The photoresist pattern 51 may be formed by forming a photoresist film on the substrate 21 using a technique such as spin coating and then patterning the photoresist film through photographic and development. Thus, flat regions on the upper surface of the substrate 21 can be exposed.

Referring to FIG. 29B, individual LED regions may be separated from each other on an elongatable tape, such as a blue tape, by stretching the individual LED regions. Thereafter, the separated individual light emitting diode regions are transferred and adhered onto the ultraviolet curing tape 61. At this time, the mesa M may be buried in the tape 61, so that the first conductive type semiconductor layer 23 exposed around the mesa M may be in contact with the upper surface of the tape 61. However, the present invention is not limited thereto, and a portion of the light emitting diode region in contact with the tape 61 can be adjusted, and a part of the thickness of the first conductivity type semiconductor layer 23 may be buried in the tape 61.

On the other hand, the side surface of the substrate 21 of the individual light emitting diode region may be formed with a sloped surface formed by scribing and a vertical surface formed by braking.

Referring to FIG. 29C, a side reflective layer 41 is deposited on the individual light emitting diode regions. The side reflective layer 41 may be deposited using, for example, a sputtering technique. The side reflective layer 41 includes a metal reflective layer such as Ag or Al. Since the specific structure and material of the side reflective layer 41 are the same as those described with reference to Figs. 21 and 22, detailed description is omitted in order to avoid duplication.

The side reflecting layer 41 is formed on the side surface of the substrate 21 with a substantially uniform thickness on the inclined side surface and the vertical side surface. The side reflective layer 41 covers the photoresist pattern 51 and covers the upper surface of the substrate 21 exposed by the photoresist pattern 51. In addition,

On the other hand, after the side reflective layer 41 is deposited, the protective layer 41 is continuously deposited. The protective layer 41 may be formed of an insulating layer or a conductive oxide layer, and may be formed using, for example, sputtering or chemical vapor deposition.

Since the exposed surface of the first conductivity type semiconductor layer 23 is covered with the tape 61, the side reflective layer 41 and the protective layer 41 are formed on the exposed surface of the first conductivity type semiconductor layer 23 Is prevented. Therefore, it is possible to prevent the side reflective layer 41 from overlapping with the first pad metal layer 35a.

29D, the photoresist pattern 51 is removed to remove the side reflective layer 41 and the protective layer 43 formed on the side surface and the upper surface of the substrate 21, The material layer and the protective material layer can be removed. Thus, the side reflective layer 41 and the protective layer 43 covering the side surface of the substrate 21 and covering a part of the upper surface can be formed.

Referring to Fig. 29E, a wavelength converter 81 is attached to the upper surface of the substrate 21. Fig. The wavelength converter 81 may be attached to the substrate 21 using an adhesive 171 or may be directly adhered onto the protective layer 43 formed on the upper surface of the substrate 21. [ Next, the light emitting diode 800 of FIG. 21 is completed by separating the individual light emitting diodes from the tape 61.

On the other hand, in the present embodiment, the formation of the scribing line LS using a laser has been described. However, the scribing line LS may be formed using a blade. In this case, the inclination of the inclined surface of the side surface of the substrate 21 can be made more gentle.

Although the scribing line LS is described as being formed after the first and second bump pads 39a and 39b are formed in the present embodiment, the scribing line LS may be formed on the upper insulating layer 37 may be formed. In this case, the upper insulating layer 37 may be formed inside the scribing line LS, and thus, the light emitting diode 900 such as the embodiment of FIG. 23 can be manufactured.

29A, a photoresist pattern 51 is formed to expose the upper surface region of the substrate 21. However, the photoresist may cover the entire upper surface of the substrate 21 In this case, the light emitting diode 1000 of FIG. 24 may be provided.

Although the scribing line LS has been described as being performed on the bottom side of the substrate 21, that is, on the side of the bump pads 39a and 39b in the foregoing embodiments, the scribing line LS May be performed on the upper surface side of the substrate 21. In this case, the light emitting diodes 1100 and 1200 according to Figs. 25 and 26 can be manufactured.

Further, although the protective layer 43 is described as being formed using an insulating layer or a conductive oxide layer, it may also be formed using a resin, whereby the light emitting diode 1300 of FIG. 27 can be manufactured.

The side surface reflection layer 41 and the protective layer 43 deposited on the upper surface of the substrate 21 are removed using the photoresist pattern 51 or the masking material. The reflective layer 41 and the protective layer 43 may be removed using other methods, such as peel-off techniques.

30 is a schematic plan view for explaining a light emitting diode 1300 according to another embodiment of the present invention, FIG. 31 is a sectional view taken along a tear line AA in FIG. 30, and FIGS. 32A and 32B are cross- Sectional enlarged sectional views for explaining various examples of diodes.

30 and 31, a light emitting diode 1300 according to the present embodiment includes a substrate 21, a first conductivity type semiconductor layer 23, an active layer 25, a second conductivity type semiconductor layer 27 The first pad metal layer 35a and the second pad metal layer 35b, the upper insulating layer 37, the first bump pad 39a, the second bump pad 39a, A light reflecting layer 39b, a light transmitting material layer 53 ', a side reflecting layer 41 and a capping layer 63. The light emitting diode 1300 may also include a wavelength converter and an adhesive 171 as described with reference to FIG. The first conductivity type semiconductor layer 23, the active layer 25, and the second conductivity type semiconductor layer 27 form a semiconductor laminate 30. Further, the light emitting diode 1300 may further include a transparent ohmic layer 29.

The first conductive semiconductor layer 23, the active layer 25, the second conductive semiconductor layer 27, the ohmic reflective layer 31, the lower insulating layer 33, the first pad metal layer 35a The second pad metal layer 35b, the upper insulating layer 37, the first bump pad 39a, and the second bump pad 39b are similar to those described with reference to FIGS. 1 and 2, A detailed description thereof will be omitted. The mesa M is disposed on the first conductivity type semiconductor layer 23 and the mesa M is similar to that described with reference to FIGS. 1 and 2, and thus a detailed description thereof will be omitted.

However, in the present embodiment, the upper surface of the substrate 21 may be a flat surface, and the roughness R may be omitted. However, the present invention is not limited thereto, and the roughness R may be formed entirely or partly on the upper surface of the substrate 21.

On the other hand, a light-transmissive material layer 53 'and a side reflective layer 41 are disposed on the sides of the substrate 21 on the side of the substrate 21. The light-permeable material layer 53 'and the side reflective layer 41 cover not only the vertical side but also the inclined side of the substrate 21. The light-transmitting material layer 53 'and the side reflective layer 41 may also cover the side surfaces of the first conductivity type semiconductor layer 23. The light-transmitting material layer 53 'and the side reflection layer 41 may cover all four sides of the substrate 21, but the present invention is not limited thereto and may cover one to three sides.

The light-transmitting material layer 53 'may be formed of the same material as the roughness reducing layer 53 described with reference to FIGS. For example, the light-transmitting material layer 53 'may be formed of a conductive oxide layer such as ITO, ZnO, or an insulating layer such as SiO2, SiNx, or SiON. In this embodiment, the light-permeable material layer 53 'may be formed to a thickness of 50 nm or less, and further, a thickness of 20 nm or less. The light-permeable material layer 53 'may be formed, for example, to a thickness of about 10 nm.

The layer of light-permeable material 53 'can be used to improve the adhesion of the side reflective layer 41, and it can also alleviate the roughness of the side surface of the substrate 21. Moreover, an omnidirectional reflector (ODR) can be formed by disposing a light-transmitting material layer 53 'between the side reflective layer 41 and the substrate 21.

On the other hand, the side reflection layer 41 is disposed on the side surface of the substrate 21 and is spaced from the upper surface of the substrate 21. [ Therefore, the light traveling to the upper surface of the substrate 21 can be emitted to the outside without being reflected by the side reflective layer 41. [

Further, as shown in the enlarged part of Fig. 31, the side reflective layer 41 is horizontally spaced from the first pad metal layer 35a. In particular, the side reflective layer 41 may be located above the upper surface of the mesa M and therefore above the exposed surface of the first conductive semiconductor layer 23 around the mesa M. For example, the lower end of the side reflective layer 41 may be parallel to the exposed surface of the first conductive type semiconductor layer 23, and may be positioned above the exposed surface of the first conductive type semiconductor layer 23, can do. A part of the exposed surface of the first conductivity type semiconductor layer 23 around the mesa M may be exposed to the outside between the side reflective layer 41 and the upper insulating layer 37. [ The light-transmissive material layer 53 'and the capping layer 63 are also horizontally spaced from the first pad metal layer 35a similar to the side reflective layer 41 and the first conductive semiconductor layer 23). ≪ / RTI >

Referring to FIG. 32A, the side reflective layer 41 may include a metal reflective layer 41a of Ag or Al, and a barrier layer 41b such as Ni and / or Ti may be disposed on the metal reflective layer. Further, an oxidation preventing film such as Au may be disposed on the barrier layer for preventing oxidation. In addition, Ni and Mo may be included in the barrier layer. The metal reflection layer 41a may have a thickness of 120 nm or more to have sufficient reflection characteristics.

For example, Ag / Ni / Mo / Ni / Mo or Ag / Ni / Mo / Ag / SiO2 may be used for the side reflective layer 41. Furthermore, the side reflective layer 41 is not limited to the metal reflective layer. The side reflective layer 41 may comprise a distributed Bragg reflector (DBR) and may be an Omni directional reflector (ODR) including a transparent oxide layer between the metal reflective layer and the substrate 21. [

The side reflective layer 41 is disposed on the side surfaces of the substrate 21 and the first conductivity type semiconductor layer 23 to prevent the side reflective layer 41 from being directly connected to the first pad metal layer 35a Therefore, it is possible to reduce the electrical interference caused by the side reflective layer 41.

When the side reflection layer 41 includes a metal reflection layer and the metal reflection layer partially overlaps the first pad metal layer 35a, the side reflection layer 41 may be undesirably removed from the side reflection layer 41 may be electrically connected directly to the first pad metal layer 35a. In this case, the electrical characteristics of the light emitting diode, such as the forward voltage, can be drastically changed depending on whether the side reflective layer 41 and the first pad metal layer 35a are in contact with each other, Lt; / RTI > In contrast, according to the embodiment of the present invention, light emitting diodes having small electrical characteristic deviations can be manufactured in a large quantity by separating the side reflective layer 41 in the lateral direction from the mesa M and the first pad metal layer 35a.

Furthermore, the heights of the upper end portions of the reflective layer 41a and the barrier layer 41b may be different from each other. The upper end of the reflective layer 41a is located at a substantially same height as the upper surface of the substrate 21 while the upper end of the barrier layer 41b is positioned at a position higher than the upper surface of the substrate 21 as shown in Figures 32A and 32B. Position.

On the other hand, the capping layer 63 is disposed on the side reflective layer 41 and covers the upper surface of the substrate 21. The capping layer 63 protects the side reflective layer 41 and the side surface reflective layer 41 from the external environment such as moisture by covering the upper surface of the substrate 21 and further firmly attaches the side reflective layer 41 to the substrate 21 Thereby preventing the side reflective layer 41 from being peeled off from the substrate 21. In particular, during formation of the side reflective layer 41, a gap may be formed between the upper end of the side reflective layer 41 and the side of the substrate 21. The gap formed between the side reflective layer 41 and the substrate 21 can be a starting point for causing the side reflective layer 41 to peel off. The capping layer 63 can cover not only the side reflective layer 41 but also the gap formed between the side reflective layer 41 and the substrate 21 so that the side reflective layer 41 Can be further prevented from being peeled off from the substrate 21.

The capping layer 63 according to the present embodiment is similar to the protective layer 43 described with reference to Figs. 21 and 22, except that the capping layer 63 covers the upper surface of the substrate 21, .

The capping layer 63 may be formed of an insulating layer such as, for example, a primer, SOG (spin-on glass), SiO2, SiNx, SiON or TiO2 or a conductive oxide layer such as ITO or ZnO. The insulating layer protects the side reflective layer 41 by blocking solder from bonding with the side reflective layer 41. Further, the conductive oxide layer such as ITO prevents the solder from migrating to the side surface of the light emitting diode 100 because the wettability of the solder is poor. Also, by using a material layer having a lower refractive index than the substrate 21 as the capping layer 63, the efficiency of light emission through the upper surface of the substrate 21 can be improved.

The capping layer 63 may have a height deviation at the upper surface edge portion of the substrate 21 due to the barrier layer 41b. Particularly, the height of the capping layer 63 at the outer portion of the substrate 21 along the edge of the upper surface of the substrate 21 becomes higher than the height of the capping layer 63 located on the upper surface of the substrate 21. This has the effect of preventing the adhesive from flowing down to the side surface of the substrate 21 when bonding the wavelength converter 81 with the adhesive 171 as in the above-described embodiments.

The capping layer 63 is formed by removing the light-transmitting material layer 53 'and the side reflective layer 41 formed on the upper surface of the substrate 21 using a lift-off technique or a peel-off technique, And an upper surface. The capping layer 63 may be formed using, for example, a sputtering deposition technique, an E-beam deposition technique, a spin coating technique, or the like.

32A, the capping layer 63 positioned on the side surface of the substrate 21 may have a substantially uniform thickness, and the thickness may be slightly smaller as the lower surface of the substrate 21 is closer to the bottom surface. For example, when the capping layer 63 is formed by sputtering or E-beam deposition, the thickness of the capping layer 63 formed on the upper surface of the substrate 21 is relatively thick. Alternatively, as shown in FIG. 32B, the capping layer 63 'may become thicker toward the lower surface of the substrate 21 on the side surface of the substrate 21. For example, when a silicon primer or a SOG (spin-on glass) is deposited using a technique such as spin coating, the thickness of the capping layer 63 'close to the upper surface of the substrate 21 The thickness of the capping layer 63 'closer to the lower surface of the substrate 21 is formed to be relatively larger. Accordingly, when the side surface of the light emitting diode is covered with the white barrier layer (for example, 75 in FIG. 20), moisture permeates through the interface between the white barrier layer and the light emitting diode from the lower surface side of the substrate 21, It is possible to effectively prevent damage. Further, since the capping layer 63 'is formed thicker on the lower surface of the substrate 21, the path of penetration of water from the lower surface side of the substrate 21 to the side reflective layer 41 and the light-permeable material layer 53' The side reflective layer 41 and the light-permeable material layer 53 'are prevented from being damaged by the light-transmissive material layer 53'.

33 is a schematic cross-sectional view illustrating a light source module according to an embodiment of the present invention.

Referring to FIG. 33, the light source module includes a support substrate 71, a light emitting diode 100, a wavelength converter 81, and a lens 91. The light emitting diode 100 is a light emitting diode 100 described above with reference to FIGS. 1 and 2. The light emitting diode 100 includes first and second bump pads 39a and 39b, 2 pads 73a and 73b may be flip-bonded on the supporting substrate 71 on which the two pads 73a and 73b are disposed. The supporting substrate 71 may be, for example, a printed circuit board.

On the other hand, a lens 91 is disposed above the light emitting diode 100. The lens 91 has a lower surface and an upper surface, and the lower surface includes a concave portion into which light emitted from the light emitting diode 100 is incident, and the upper surface has an exit surface for emitting light. The concave portion of the lower surface may be surrounded by a flat surface.

Further, as shown in the figure, the upper surface may include a concave portion located at the center and a convex portion located around the concave portion. The convex portion can surround the concave portion.

The lens 91 is a diffusion lens for dispersing light, but the present invention is not limited thereto. Various shapes of the lens 91 may be combined with the light emitting diode 100 to realize various light patterns.

Although the light source module in which the light emitting diode 100 is flip-bonded to the support substrate 71 is described in this embodiment, other light emitting diodes 200, 300, 400, 500, 600, 700, 800, 900, 1100, 1200, or 1300) may be mounted on the support substrate 71 and used.

The light source module can be suitably used, for example, for a large-sized TV, a camera flash, and the like.

34 is a schematic perspective view showing a vehicle 1500 equipped with a head lamp 1510 to which a light emitting diode according to embodiments of the present invention is applied.

Referring to FIG. 33, light emitting diodes 100 to 1300 according to an embodiment of the present invention are mounted in front of a vehicle 1500 and disposed in a head lamp unit 1510. In the embodiment, the vehicle headlamp section 1510 includes a head lamp, a fog lamp, and the like that ensure the driver's front night vision.

The vehicle headlamp portion 1510 may be mounted on the left and right sides of the vehicle 1500, respectively, and may have various shapes in consideration of the driver's taste. In addition, the head lamp units 1510 mounted on the front left and right sides may have a symmetrical structure with each other, but the present invention is not limited thereto and may have different structures.

The light emitting diode may be mounted in the head lamp unit 1500 in the form of a light emitting module as described with reference to FIG. 20, but the present invention is not limited thereto and may be mounted with various types of light emitting modules.

35 is a schematic perspective view showing a mobile device 2000 equipped with a camera flash 2300 to which a light emitting diode according to embodiments of the present invention is applied.

Referring to FIG. 35, the mobile device 2000 includes a camera module 2100 and a flash module 2300. The light emitting diodes 100 to 1300 according to an embodiment of the present invention are mounted in the flash module 2300. The flash module 2300 irradiates the subject with light when the camera module 2100 operates to photograph the subject.

The light emitting diode may be mounted in the camera module 2100 in the form of a light source module as described with reference to FIG. 32, but the present invention is not limited thereto, and various types of light source modules may be used.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, the elements or components described in relation to one embodiment can be applied to other embodiments without departing from the technical idea of the present invention.

Claims (20)

A substrate having a side surface;
A semiconductor stacked structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer interposed between the first conductive semiconductor layer and the second conductive semiconductor layer;
An ohmic reflective layer electrically connected to the second conductive semiconductor layer;
A first bump pad and a second bump pad disposed under the ohmic reflective layer and electrically connected to the first conductive semiconductor layer and the second conductive semiconductor layer, respectively;
A side reflective layer covering a side surface of the substrate; And
And a capping layer covering the upper surface of the substrate and the side reflective layer. The method according to claim 1,
And a light-transmissive material layer interposed between the side surface of the substrate and the side reflective layer. The method of claim 2,
Wherein the substrate comprises four sides,
Wherein the light-permeable material layer and the side reflective layer cover four sides of the substrate. The method of claim 2,
Wherein the light-transmissive material layer comprises ITO, ZnO, SiNx, SiON, or SiO2. The method of claim 2,
And the lower end of the light-transmissive material layer and the side reflective layer are parallel to each other. The method according to claim 1,
Wherein the side reflective layer comprises a reflective metal layer and a barrier layer. The method of claim 6,
And the upper end portions of the reflective metal layer and the barrier layer are located outside the upper surface of the substrate. The method of claim 7,
And an upper end of the barrier layer is positioned higher than an upper end of the reflective metal layer. The method according to claim 1,
Wherein the substrate includes a side surface perpendicular to an upper surface of the first conductive type semiconductor layer and a side surface inclined with respect to the vertical side surface,
Wherein the inclined side is further away from the top surface of the substrate than the vertical side. The method of claim 9,
The inclined side surface is a surface formed by a scribing process,
Wherein the vertical side is a surface formed by braking. The method according to claim 1,
Wherein the capping layer comprises SiO2, SiNx, SiON, ITO, primer, or SOG. The method according to claim 1,
And a mesa disposed on the first conductive semiconductor layer,
Wherein the mesa includes the active layer and the second conductivity type semiconductor layer,
The mesa is spaced from the sides,
Wherein the side reflective layer is spaced laterally from the mesa. The method of claim 12,
A lower insulating layer covering the ohmic reflective layer, the lower insulating layer including a first opening exposing the first conductivity type semiconductor layer and a second opening exposing the ohmic reflective layer;
A first pad metal layer disposed on the lower insulating layer and electrically connected to the first conductive semiconductor layer through the first opening;
A second pad metal layer disposed on the lower insulating layer and electrically connected to the ohmic reflective layer through the second opening; And
Further comprising an upper insulating layer covering the first pad metal layer and the second pad metal layer, the upper insulating layer including a first opening exposing the first pad metal layer and a second opening exposing the second pad metal layer,
And the first and second bump pads are disposed on the upper insulating layer and connected to the first pad metal layer and the second pad metal layer through the first opening and the second opening of the upper insulating layer, respectively. 14. The method of claim 13,
Wherein the mesa includes a through hole through the second conductivity type semiconductor layer and the active layer to expose the first conductivity type semiconductor layer,
And the first pad metal layer is electrically connected to the first conductive type semiconductor layer exposed through the through hole. 15. The method of claim 14,
The mesa further includes recesses that expose the first conductive semiconductor layer on the side surfaces,
Wherein the first pad metal layer is electrically connected to the first conductive type semiconductor layer exposed through the recesses. 16. The method of claim 15,
The mesa has a shape in which the edges are cut,
Wherein the first pad metal layer is electrically connected to the first conductivity type semiconductor layer near the edges of the mesa. The method according to claim 1,
And an ohmic oxide layer in ohmic contact with the second conductivity type semiconductor layer around the ohmic reflective layer. The method according to claim 1,
And a wavelength converter disposed on the substrate. 19. The method of claim 18,
Wherein the wavelength converter comprises a wavelength conversion sheet or a ceramic plate phosphor. 19. The method of claim 18,
Wherein the wavelength converter is bonded to the capping layer via an adhesive.

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