CN209471992U - Semiconductor chip - Google Patents
Semiconductor chip Download PDFInfo
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- CN209471992U CN209471992U CN201920191147.1U CN201920191147U CN209471992U CN 209471992 U CN209471992 U CN 209471992U CN 201920191147 U CN201920191147 U CN 201920191147U CN 209471992 U CN209471992 U CN 209471992U
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Abstract
The utility model discloses semiconductor chips, it includes the substrate stacked gradually, one n type semiconductor layer, one active area, one p type semiconductor layer, one transparency conducting layer, one insulating layer and a N-type electrode and a P-type electrode, wherein the column N-type electrode connection needle of the N-type electrode is electrically connected to the n type semiconductor layer after passing through the insulating layer, the column P-type electrode connection needle of the P-type electrode is electrically connected to the transparency conducting layer after passing through the insulating layer, and the line between the column P-type electrode connection needle and a column conduction position of the transparency conducting layer is curve, in this way, it can equably be extended when electric current is injected from the N-type electrode and the P-type electrode.
Description
Technical field
The utility model relates to semiconductor fields, in particular to semiconductor chip.
Background technique
The principle of luminosity of the semiconductor chip of light emitting diode (Light Emitting Diode, LED) is to utilize N-type half
Conductor layer and P-type semiconductor interlayer mobile energy difference releases energy in the form of light and shines, therefore, light emitting diode quilt
Referred to as cold light source.In addition, light emitting diode has the advantages that durability is high, the service life is long, light and handy, power consumption is low etc., therefore, now
Illumination market gives great expectations for light emitting diode, is regarded as the illuminations of a new generation.However, present semiconductor chip
Remain the low problem of luminous efficiency, therefore, how to improve semiconductor chip luminous efficiency become it is industry rs largest
One of research topic.In a semiconductor chip, an important factor for influencing semiconductor chip is effective light-emitting surface of semiconductor chip
Product is less than the real area of semiconductor chip, and the efficient lighting area of semiconductor chip is not only by electrode, electrode extension item
With the influence of the chip technologies such as MESA, and the influence of current expansion effect is also suffered from.For example, shown in fig. 1 existing
In semiconductor chip, semiconductor chip includes a substrate 1P, an epitaxial structure 2P for being grown on substrate 1P, is grown on this
A current barrier layer 3P of epitaxial structure 2P, an electrically conducting transparent for being grown on epitaxial structure 2P and current barrier layer 3P
Layer 4P, be grown on transparency conducting layer 4P a P-type electrode 5P, be grown on a N-type electrode 6P of epitaxial structure 2P with
And it is grown on an insulating protective layer 7P of transparency conducting layer 4P.Because epitaxial structure 2P p type semiconductor layer (such as but
Be not limited to P-GaN) conductivity it is poor, in order to improve the current expansion effect of p type semiconductor layer, it usually needs partly led in p-type
Transparency conducting layer 4P (such as ito film layer, ZnO film layer) is grown on body layer, can either be played transparent and current expansion
Effect can also be played the role of forming Ohmic contact with p type semiconductor layer.But semiconductor chip shown in fig. 1 is still deposited
In biggish defect.Specifically, due to the finite conductivity of transparency conducting layer 4P, at the edge close to semiconductor chip
Position, electric current is not easy to be extended, and then leads to the non-uniform light of semiconductor chip, appears in the middle part of semiconductor chip
The partially dark adverse effect of the brightness at partially bright and in semiconductor chip the edge of brightness.
Utility model content
One of the utility model is designed to provide semiconductor chip, wherein from the N-type electricity of the semiconductor chip
The electric current that pole and P-type electrode are injected can equably be extended, so that the middle part and edge of the semiconductor chip are equably
It shines, to be conducive to improve the light-emitting area and luminous efficiency of the semiconductor chip.
One of the utility model is designed to provide semiconductor chip, wherein the current expansion of the semiconductor chip
The problem of dead angle, can be effectively improved, to be conducive to increase the light-emitting area of the semiconductor chip.
One of the utility model is designed to provide semiconductor chip, wherein the P-type electrode and the semiconductor
Line between one column conduction position of the transparency conducting layer of chip is in bending state, in this way, from the p-type electricity
The electric current of pole injection can equably be extended to the middle part and edge of the semiconductor chip, so that the semiconductor chip
Middle part and edge can equably shine.
One of the utility model is designed to provide semiconductor chip, wherein the P-type electrode transparent is led with described
Electric layer has multiple conduction positions, and the area gradual change of multiple conduction positions of the P-type electrode and the transparency conducting layer becomes
Change, correspondingly, the extension unit n type semiconductor layer of the N-type electrode and the semiconductor chip has multiple conduction positions, and
The area gradual change of multiple conduction positions of the n type semiconductor layer of the N-type electrode and the extension unit changes, and passes through this
The mode of sample, the electric current injected from the P-type electrode and the N-type electrode can equably be extended to the semiconductor chip
Middle part and edge.
One of the utility model is designed to provide semiconductor chip, wherein the P-type electrode provides a P-type electrode
Pad and at least one extends feeler, and the P-type electrode pad and the extension feeler are adjacent and be electrically connected to the extension
The p type semiconductor layer of unit, in this way, the energy when electric current is injected the p type semiconductor layer from the P-type electrode
The bad phenomenon of current crowding is avoided, enough to advantageously ensure that electric current is equably extended.
According to the one aspect of the utility model, the utility model provides semiconductor chip comprising a substrate is laminated in
One n type semiconductor layer of the substrate, the active area for being laminated in the n type semiconductor layer, the P for being laminated in the active area
Type semiconductor layer, the transparency conducting layer for being laminated in the p type semiconductor layer, the insulating layer for being laminated in the transparency conducting layer
And it is respectively laminated on a N-type electrode and a P-type electrode for the insulating layer,
Wherein the N-type electrode further comprises a N-type electrode pad, at least N-type electrode extension item and at least one
Column N-type electrode connects needle, and the N-type electrode pad is electrically connected to the n type semiconductor layer, institute after passing through the insulating layer
It states first end direction of the N-type electrode extension item from the N-type electrode pad to the semiconductor chip to extend, a column N
Type electrode connection needle respectively extends from the N-type electrode extension item and is electrically connected to respectively after passing through the insulating layer described
N type semiconductor layer；
Wherein the P-type electrode further comprises a P-type electrode pad, at least P-type electrode extension item and at least one
Column P-type electrode connects needle, and the P-type electrode pad is electrically connected to the p type semiconductor layer, institute after passing through the insulating layer
It states the second end direction of the P-type electrode extension item from the P-type electrode pad to the semiconductor chip to extend, a column P
Type electrode connection needle respectively extends from the P-type electrode extension item and is electrically connected to respectively after passing through the insulating layer described
Transparency conducting layer, wherein a column conducting position of the column P-type electrode connection needle of the P-type electrode and the transparency conducting layer
Line between setting is curve.
One embodiment according to the present utility model, the column N-type electrode connection needle of the N-type electrode and the N
Line between one column conduction position of type semiconductor layer is straight line.
One embodiment according to the present utility model, the column P-type electrode connection needle of the P-type electrode and described
The conducting area gradual change of one column conduction position of bright conductive layer changes, correspondingly, a column N-type electrode of the N-type electrode
The conducting area gradual change for connecting a column conduction position of needle and the n type semiconductor layer changes.
One embodiment according to the present utility model, the column P-type electrode connection needle of the P-type electrode and described
The conducting area of one column conduction position of bright conductive layer from the P-type electrode pad to the second end of the semiconductor chip by
Cumulative to add, correspondingly, position is connected in the column N-type electrode connection needle of the N-type electrode and a column of the n type semiconductor layer
The conducting area set is gradually increased from the N-type electrode pad to the first end of the semiconductor chip.
One embodiment according to the present utility model, the column P-type electrode connection needle of the P-type electrode and described
Spacing gradual change variation in one column conduction position of bright conductive layer between two neighboring conduction position, correspondingly, the N-type electrode
Column N-type electrode connection needle and the n type semiconductor layer a column conduction position between two neighboring conduction position
Spacing gradual change variation.
One embodiment according to the present utility model, the column P-type electrode connection needle of the P-type electrode and described
Spacing in one column conduction position of bright conductive layer between two neighboring conduction position is partly led from the P-type electrode pad to described
The second end of body chip gradually becomes smaller, correspondingly, the column N-type electrode connection needle and the N-type half of the N-type electrode
Spacing in one column conduction position of conductor layer between two neighboring conduction position is from the N-type electrode pad to the semiconductor
The first end of chip gradually becomes smaller.
One embodiment according to the present utility model, the section face of a column of the P-type electrode P-type electrode connection needle
Product is gradually increased from the P-type electrode pad to the second end of the semiconductor chip, correspondingly, the one of the N-type electrode
The area of section of N-type electrode connection needle is arranged from the N-type electrode pad to the first end of the semiconductor chip gradually
Increase.
One embodiment according to the present utility model, the P-type electrode further comprises at least one extension feeler, described to prolong
It is adjacent with the P-type electrode pad to stretch feeler, wherein the extension feeler extends the P-type electrode pad and across described
The transparency conducting layer is electrically connected to after insulating layer.
One embodiment according to the present utility model, the N-type electrode include a N-type electrode pad, an institute
N-type electrode extension item and the column N-type electrode connection needle are stated, wherein the N-type electrode pad is in the semiconductor chip
The second end be overlappingly formed in a corner of the insulating layer, the N-type electrode extension item is in the insulating layer
First end direction of the edge from the N-type electrode pad to the semiconductor chip extends, and a column N-type electrode connects needle
Respectively the n type semiconductor layer is extended to and is electrically connected to behind the edge for passing through the insulating layer；Correspondingly, the p-type
Electrode includes that a P-type electrode pad, a P-type electrode extension item and a column P-type electrode connect needle, wherein institute
It states P-type electrode pad and is overlappingly formed in the insulating layer, the P-type electrode extension in the first end of the semiconductor chip
The second end direction of the item from the P-type electrode pad to the semiconductor chip extends, and the column P-type electrode connection needle exists
The transparency conducting layer is extended to and is electrically connected to after the insulating layer.
One embodiment according to the present utility model, the N-type electrode include a N-type electrode pad, an institute
N-type electrode extension item and the column N-type electrode connection needle are stated, wherein the N-type electrode pad is in the semiconductor chip
The second end be overlappingly formed in the middle part of the insulating layer, the N-type electrode extension item the middle part of the insulating layer from
The N-type electrode pad extends to the first end direction of the semiconductor chip, and the column N-type electrode connection needle exists respectively
The n type semiconductor layer is extended to and is electrically connected to behind the middle part of the insulating layer；Correspondingly, the P-type electrode packet
A P-type electrode pad, two P-type electrode extension items and the two column P-type electrode connection needle are included, wherein the p-type
Electrode pad is overlappingly formed in the insulating layer, two P-type electrode extensions in the first end of the semiconductor chip
Item is in a manner of being spaced apart from each other at the edge of the insulating layer from the P-type electrode pad to the second end of the semiconductor chip
Portion direction extends, and the connection needle of P-type electrode described in each column extends to and be electrically connected to after passing through the insulating layer described transparent
Conductive layer.
According to the other side of the utility model, the utility model further provides for the manufacturing method of semiconductor chip,
Wherein the manufacturing method includes the following steps:
(a) insulating layer is etched, to form a N-type pad channel and from N-type pad channel to semiconductor chip
At least column N-type that extends of first end direction connect needle passageway, wherein N-type pad channel and a column N-type connect
It connects needle passageway and extends respectively to a n type semiconductor layer；
(b) insulating layer is etched, in curved manner with one p-type pad channel of formation and from p-type pad channel
At least column p-type extended to the second end direction of the semiconductor chip connects needle passageway, wherein p-type pad channel
A p type semiconductor layer is extended to, the column p-type connection needle passageway extends to a transparency conducting layer；And
(c) from one N-type electrode of insulating layer growth and a P-type electrode, wherein the N-type electrode is through the N-type pad
Channel connects needle passageway with a column N-type and extends to and be electrically connected to the n type semiconductor layer, wherein the P-type electrode
The p type semiconductor layer is extended to and be electrically connected to through p-type pad channel, connects needle passageway with through a column p-type
The transparency conducting layer is extended to and is electrically connected to, the semiconductor chip is made.
One embodiment according to the present utility model, the step (a) and the step (b) are in the same etching step
It completes.
One embodiment according to the present utility model, in the above-mentioned methods, in the position in neighbouring p-type pad channel,
An at least feeler aperture is formed in the insulating layer, wherein the feeler aperture extends to the p type semiconductor layer, wherein described
P-type electrode extends to and is electrically connected to the p type semiconductor layer through the feeler aperture.
One embodiment according to the present utility model, in the above-mentioned methods, in the position in neighbouring p-type pad channel,
An at least feeler aperture is formed in the insulating layer, wherein the feeler aperture extends to the transparency conducting layer, wherein the P
Type electrode extends to and is electrically connected to the transparency conducting layer through the feeler aperture.
One embodiment according to the present utility model, the column P-type electrode connection needle of the P-type electrode and described
The conducting area gradual change of one column conduction position of bright conductive layer changes, correspondingly, a column N-type electrode of the N-type electrode
The conducting area gradual change for connecting a column conduction position of needle and the n type semiconductor layer changes.
One embodiment according to the present utility model, the column P-type electrode connection needle of the P-type electrode and described
The conducting area of one column conduction position of bright conductive layer from the P-type electrode pad to the second end of the semiconductor chip by
Cumulative to add, correspondingly, position is connected in the column N-type electrode connection needle of the N-type electrode and a column of the n type semiconductor layer
The conducting area set is gradually increased from the N-type electrode pad to the first end of the semiconductor chip.
Detailed description of the invention
Fig. 1 is the schematic cross-sectional view of the semiconductor chip of the prior art.
Fig. 2A and Fig. 2 B is walked according to the manufacture of the semiconductor chip of the above-mentioned preferred embodiment of the utility model respectively
One of rapid schematic diagram.
Fig. 3 A and Fig. 3 B are walked according to the manufacture of the semiconductor chip of the above-mentioned preferred embodiment of the utility model respectively
Two rapid schematic diagram.
Fig. 4 A and Fig. 4 B are walked according to the manufacture of the semiconductor chip of the above-mentioned preferred embodiment of the utility model respectively
Three rapid schematic diagram.
Fig. 5 A and Fig. 5 B are walked according to the manufacture of the semiconductor chip of the above-mentioned preferred embodiment of the utility model respectively
Four rapid schematic diagram.
Fig. 6 A and Fig. 6 B are walked according to the manufacture of the semiconductor chip of the above-mentioned preferred embodiment of the utility model respectively
Five rapid schematic diagram.
Fig. 7 A and Fig. 7 B are walked according to the manufacture of the semiconductor chip of the above-mentioned preferred embodiment of the utility model respectively
Six rapid schematic diagram, wherein Fig. 7 A describes the section view state of the semiconductor chip, and Fig. 7 B describes the semiconductor core
The overlooking state of piece.
Fig. 8 is a variant embodiment according to the semiconductor chip of the above-mentioned preferred embodiment of the utility model
Schematic top plan view.
Specific embodiment
It is described below for disclosing the utility model so that those skilled in the art can be realized the utility model.It retouches below
Preferred embodiment in stating is only used as illustrating, it may occur to persons skilled in the art that other obvious modifications.It is retouched following
The basic principle of the utility model defined in stating can be applied to other embodiments, deformation scheme, improvement project, etc. Tongfangs
The other technologies scheme of case and the spirit and scope without departing from the utility model.
It will be understood by those skilled in the art that in the exposure of the utility model, term " longitudinal direction ", " transverse direction ", "upper",
The orientation of the instructions such as "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom" "inner", "outside" or position are closed
System is to be based on the orientation or positional relationship shown in the drawings, and is merely for convenience of describing the present invention and simplifying the description, without
It is that the device of indication or suggestion meaning or element must have a particular orientation, be constructed and operated in a specific orientation, therefore on
Stating term should not be understood as limiting the present invention.
It is understood that term " one " is interpreted as " at least one " or " one or more ", i.e., in one embodiment,
The quantity of one element can be one, and in a further embodiment, the quantity of the element can be it is multiple, term " one " is no
It can be interpreted as the limitation to quantity.
With reference to the attached drawing 2A to Fig. 7 B of the Figure of description of the utility model, according to a preferred embodiment of the utility model
Semiconductor chip is disclosed for and is set forth in following description, wherein the semiconductor chip includes an extension unit
10, a transparency conducting layer 20, an insulating layer 30, a N-type electrode 40 and a P-type electrode 50.
With continued reference to attached drawing 2A to Fig. 3 B, the extension unit 10 has including a substrate 11, a n type semiconductor layer 12, one
Source region 13 and a p type semiconductor layer 14, wherein the substrate 11, the n type semiconductor layer 12, the active area 13 and described
P type semiconductor layer 14 stacks gradually.
Specifically, in this preferable examples of the semiconductor chip of the utility model, the n type semiconductor layer
12 are grown on the substrate 11, so that the n type semiconductor layer 12 is laminated in the substrate 11；The active area 13 is grown on institute
N type semiconductor layer 12 is stated, so that the active area 13 is laminated in the n type semiconductor layer 12；The p type semiconductor layer 14 is grown
In the active area 13, so that the p type semiconductor layer 14 is laminated in the active area 13.
Optionally, in a modified example of the semiconductor chip of the utility model, the n type semiconductor layer 12
It can also be laminated in the substrate 11 indirectly, for example, a buffer layer is grown first in the substrate 11, N described in secondary growth
Type semiconductor layer 12 is in the buffer layer, so that the buffer layer is maintained at the n type semiconductor layer 12 and the substrate 11
Between, so that the n type semiconductor layer 12 and the substrate 11 are laminated indirectly.Correspondingly, in the institute of the utility model
It states in other modified examples of semiconductor chip, the active area 13 can also be laminated in the n type semiconductor layer indirectly
12 or the p type semiconductor layer 14 can also be laminated in the active area 13 indirectly.
It is noted that the semiconductor of the type of the substrate 11 of the extension unit 10 in the utility model
It is unrestricted in chip, for example, the substrate 11 can be but not limited to Sapphire Substrate, silicon substrate, silicon carbide substrates etc..Separately
Outside, institute of the type of the n type semiconductor layer 12 of the extension unit 10 and the p type semiconductor layer 14 in the utility model
Stating can also be unrestricted in semiconductor chip, for example, the n type semiconductor layer 12 can be but not limited to gallium nitride layer, phase
Ying Di, the p type semiconductor layer 14 can be but not limited to gallium nitride layer.
With continued reference to attached drawing 4A and Fig. 4 B, the extension unit 10 has at least exposed portion 15 of semiconductor, wherein described
Semiconductor bare portion 15 extends to the n type semiconductor layer 12 through the active area 13 from the p type semiconductor layer 14, with exposure
A part of surface of the n type semiconductor layer 12 is in the semiconductor bare portion 15 of the extension unit 10.
Preferably, in this preferable examples of the semiconductor chip shown in attached drawing 2A to Fig. 7 B, by etching institute
The mode for stating a part of thickness of p type semiconductor layer 14, the active area 13 and the n type semiconductor layer 12 is capable of forming from institute
State the semiconductor bare portion 15 that p type semiconductor layer 14 extends to the n type semiconductor layer 12 through the active area 13.Also
It is to say, the thickness of the part corresponding to the semiconductor bare portion 15 of the n type semiconductor layer 12 is less than the N-type half
The thickness of the part for being laminated with the active area 13 of conductor layer 12.
Optionally, in other examples of the semiconductor chip of the utility model, by etching the P-type semiconductor
The mode of layer 14 and the active area 13, which is capable of forming from the p type semiconductor layer 14, extends to the N through the active area 13
The semiconductor bare portion 15 of type semiconductor layer 12.That is, the utility model the semiconductor chip it is some
In example, the n type semiconductor layer 12 can be not etched and the extension unit 10 is allowed to form the semiconductor bare portion
15。
With continued reference to attached drawing 4A and Fig. 4 B, the semiconductor bare portion 15 of the extension unit 10 is by the exposed portion of a pad
151 form at least one exposed portion 152 of extension item for being connected to the exposed portion 151 of the pad, wherein the extension unit 10
The exposed portion 151 of pad is formed in a second end 102 of the semiconductor chip, the extension of the extension unit 10
A first end 101 direction of the exposed portion 152 of item from the exposed portion 151 of the pad to the semiconductor chip extends.Described
The thickness direction of semiconductor chip, the exposed portion 151 of the pad of the extension unit 10 and the exposed portion 152 of extension item divide
The n type semiconductor layer 12 is not extended to through the active area 13 from the p type semiconductor layer 14, is partly led with the exposure N-type
A part of surface of body layer 12 is in the exposed portion 151 of the pad and the exposed portion 152 of extension item of the extension unit 10.
Preferably, in this preferable examples of the semiconductor chip shown in attached drawing 4A and Fig. 4 B, the extension list
The exposed portion 151 of the pad of member 10 is formed in the semiconductor chip in the second end 102 of the semiconductor chip
A corner, the exposed portion 152 of the extension item of the extension unit 10 is along the edge of the semiconductor chip from institute
The exposed portion 151 of pad is stated to extend to 101 direction of the first end of the semiconductor chip.
With reference to attached drawing 5A and Fig. 5 B, the transparency conducting layer 20 has a first passage 21 and a second channel 22, wherein
The transparency conducting layer 20 is laminated in the p type semiconductor layer 14 of the extension unit 10, and the extension unit 10
The semiconductor bare portion 15 corresponds to and is connected to the first passage 21 of the transparency conducting layer 20 and described transparent leads
The second channel 22 of electric layer 20 corresponds to the p type semiconductor layer 14 of the extension unit 10, with the exposure p-type half
A part of surface of conductor layer 14 is in the second channel 22 of the transparency conducting layer 20.
Preferably, the shape of the first passage 21 of the transparency conducting layer 20 and described the half of the extension unit 10
The shape in the exposed portion 15 of conductor is consistent.It is highly preferred that the size of the first passage 21 of the transparency conducting layer 20 is slightly larger than
The size in the semiconductor bare portion 15 of the extension unit 10, to make the P-type semiconductor of the extension unit 10
A part of surface of layer 14 is exposed to the first passage 21 of the transparency conducting layer 20.
Specifically, firstly, depositing an electrically conducting transparent base in the extension unit 10, so that the electrically conducting transparent base
It is laminated in the p type semiconductor layer 14 and the n type semiconductor layer 12 of the extension unit 10.It is noted that being formed
The material of the electrically conducting transparent base can be but not limited to tin indium oxide, thus, the electrically conducting transparent base can be but not
It is limited to indium tin oxide layer.Preferably, the thickness range of the electrically conducting transparent base is 100 angstroms -2000 angstroms (including 100 angstroms
With 2000 angstroms).For example, in a specific example of the semiconductor chip of the utility model, can by but it is unlimited
The electrically conducting transparent base is deposited in the extension unit 10, so that the electrically conducting transparent base in the mode of sputtering or vapor deposition
It is laminated in the p type semiconductor layer 14 and the n type semiconductor layer 12 of the extension unit 10.
Secondly, being laminated in the electrically conducting transparent base in the extension unit 10 depositing the electrically conducting transparent base
After the p type semiconductor layer 14 and the n type semiconductor layer 12 of the extension unit 10, to the electrically conducting transparent base into
The operation of row alloy.For example, when carrying out alloy operation to the electrically conducting transparent base board that uses be quick anneal oven (RTA) or
Person's alloy furnace tubes by adopting, alloy temperature range are 500 DEG C -600 DEG C (including 500 DEG C and 600 DEG C).It needs to be passed through during alloy
Oxygen and nitrogen, wherein the property of the adjustable electrically conducting transparent base of mode by adjusting the content of oxygen.
Then, etching figure is identified in the electrically conducting transparent base using the photoresist layer for being laminated in the electrically conducting transparent base
Case, and the electrically conducting transparent base is etched according to etched pattern by way of wet etching, so that the electrically conducting transparent base
It forms the transparency conducting layer 20 for being laminated in the p type semiconductor layer 14 of the extension unit 10 and forms described transparent lead
The first passage 21 and the second channel 22 of electric layer 20.Finally, removal photoresist.Preferably, it is lost according to etched pattern
The solution used when carving the electrically conducting transparent base can be but not limited to the mixed solution of ferric trichloride and hydrochloric acid.
Optionally, in a modified example of the semiconductor chip of the utility model, the transparency conducting layer 20
The second channel 22 can not formed.
With reference to attached drawing 6A and Fig. 6 B, the insulating layer 30 have a N-type pad channel 31, a column N-type connection needle passageway 32,
One p-type pad channel 33 and a column p-type connect needle passageway 34.
The insulating layer 30 is laminated in the transparency conducting layer 20, and the insulating layer 30 is through the transparency conducting layer 20
The first passage 21 extend to the n type semiconductor layer 12 of the extension unit 10 and through the transparency conducting layer 20
The second channel 22 extends to the p type semiconductor layer 14 of the extension unit 10.
The N-type pad channel 31 of the insulating layer 30 corresponds to the exposed portion of the pad of the extension unit 10
151, wherein the N-type pad channel 31 of the insulating layer 30 extends to the n type semiconductor layer of the extension unit 10
12, with a part of surface of the exposure n type semiconductor layer 12 in the N-type pad channel 31 of the insulating layer 30.
One column of the insulating layer 30 N-type connection needle passageway 32 corresponds to the extension item of the extension unit 10
Exposed portion 152 a, wherein column of the insulating layer 30 N-type connection needle passageway 32 extends respectively to the extension unit 10
The n type semiconductor layer 12, with a part of surface of the exposure n type semiconductor layer 12 in the insulating layer 30 one column described in
N-type connects needle passageway 32, wherein a column N-type of the insulating layer 30 connects needle passageway 32 from N-type pad channel 31
Extend to 101 direction of the first end of the semiconductor chip.
The p-type pad channel 33 of the insulating layer 30 corresponds to the second channel of the transparency conducting layer 20
22, wherein the p-type pad channel 33 of the insulating layer 30 extends to the p type semiconductor layer of the extension unit 10
14, with a part of surface of the exposure p type semiconductor layer 14 in the p-type pad channel 33 of the insulating layer 30.
One column of the insulating layer 30 p-type connection needle passageway 34 is from p-type pad channel 33 to the semiconductor
102 direction of the second end of chip extends, wherein a column of the insulating layer 30 p-type connection needle passageway 34 prolongs respectively
The transparency conducting layer 20 is extended to, institute is arranged in the one of the insulating layer 30 with a part of surface of the exposure transparency conducting layer 20
State p-type connection needle passageway 34.In this preferable examples of the semiconductor chip shown in attached drawing 2A to Fig. 7 B, the insulation
One column of the layer 30 p-type connection needle passageway 34 is in curved manner in 101 He of the first end of the semiconductor chip
Extend between the second end 102.
Specifically, and allowing the insulated substrate through institute firstly, deposit an insulated substrate in the transparency conducting layer 20
The first passage 21 for stating transparency conducting layer 20 extends to the n type semiconductor layer 12 of the extension unit 10 and through institute
The second channel 22 for stating transparency conducting layer 20 extends to the p type semiconductor layer 14 of the extension unit 10.
It is noted that the material of the insulated substrate can be but not limited to SiO2 (silica).Preferably, sharp
With the vapour deposition process of plasma enhanced chemical (Plasma Enhanced Chemical Vapor Deposition,
PECVD) precipitate one layer of SiO2 in the transparency conducting layer 20, wherein the thickness range of the insulated substrate be 600 angstroms-
3000 angstroms (including 600 angstroms and 3000 angstroms).
Secondly, identifying etching figure on the surface of the insulated substrate using the photoresist layer for being laminated in the insulated substrate
Case, and the insulated substrate is etched according to etched pattern by way of wet etching so that the insulated substrate formed it is described
Insulating layer 30 connects needle passageway 32, the p-type with the N-type pad channel 31 of the formation insulating layer 30, each N-type
Pad channel 33, each p-type connect needle passageway 34.Finally, removal photoresist layer.Preferably, it is etched according to etched pattern
The solution used when the insulated substrate can be but not limited to the mixed solution of ammonium fluoride and hydrofluoric acid.
With reference to attached drawing 7A and Fig. 7 B, the N-type electrode 40 is laminated in the insulating layer 30, and the N-type electrode 40 passes through
The N-type pad channel 31 of the insulating layer 30 connects needle passageway 32 with a column N-type and extends to and be electrically connected to institute
State the n type semiconductor layer 12 of extension unit 10.
Specifically, the N-type electrode 40 includes a N-type electrode pad 41, N-type electrode extension item 42 and a column N
Type electrode connects needle 43, wherein the N-type electrode pad 41 of the N-type electrode 40 is described the second of the semiconductor chip
End 102 is laminated in the insulating layer 30, and the N-type pad channel 31 through the insulating layer 30 extends to and is electrically connected
In the n type semiconductor layer 12 of the extension unit 10, wherein the N-type electrode extension item 42 of the N-type electrode 40 is certainly
The N-type electrode pad 41 extends to 101 direction of the first end of the semiconductor chip, wherein the N-type electrode 40
Column N-type electrode connection needle 43 respectively extend from the N-type electrode extension item 42, and the one of the N-type electrode 40
A column of the N-type electrode connection needle 43 respectively through the insulating layer 30 N-type connection needle passageway 32 is arranged to extend to and electric
It is connected to the n type semiconductor layer 12 of the extension unit 10.Optionally, the N-type electrode pad of the N-type electrode 40
41 can also not be laminated in the insulating layer 30.
Preferably, described in the N-type electrode pad 41 of the N-type electrode 40, N-type electrode extension item 42 and a column
N-type electrode connection needle 43 is integrally formed, so that N-type electrode extension item 42 integrally extends the N-type electrode
Pad 41 integrally extends the N-type electrode extension item 42 with making the column N-type electrode connect needle 43 respectively.For example,
In a preferable examples of the semiconductor chip of the utility model, first using negtive photoresist on the surface of the insulating layer 30
N-type electrode figure is made, secondly the exposed position for needing to precipitate the N-type electrode 40 uses metal evaporation board evaporation metal
Layer, the mode for reusing metal-stripping remove extra metal layer, to form the N-type electricity for being laminated in the insulating layer 30
Pole 40.
Correspondingly, with continued reference to attached drawing 7A and Fig. 7 B, the P-type electrode 50 is laminated in the insulating layer 30, and the P
Type electrode 50 extends to and is electrically connected to the institute of the extension unit 10 through the p-type pad channel 33 of the insulating layer 30
It states p type semiconductor layer 14 and the P-type electrode 50 and connects needle passageway 34 through a column p-type of the insulating layer 30 and extend to
Be electrically connected to the transparency conducting layer 20.
Specifically, the P-type electrode 50 includes a P-type electrode pad 51, P-type electrode extension item 52 and a column P
Type electrode connects needle 53, wherein the P-type electrode pad 51 of the P-type electrode 50 is described the first of the semiconductor chip
End 101 is laminated in the insulating layer 30, and the p-type pad channel 33 through the insulating layer 30 extends to and is electrically connected
In the p type semiconductor layer 14 of the extension unit 10, wherein the P-type electrode extension item 52 of the P-type electrode 50 is certainly
The P-type electrode pad 51 extends in curved manner to 102 direction of the second end of the semiconductor chip, wherein institute
The column P-type electrode connection needle 53 for stating P-type electrode 50 respectively extends from the P-type electrode extension item 52, and the p-type
The column p-type connection needle passageway 34 of one column of the electrode 50 P-type electrode connection needle 53 respectively through the insulating layer 30 prolongs
Extend to and be electrically connected to the transparency conducting layer 20.Optionally, the P-type electrode pad 51 of the P-type electrode 50 can also
Not to be laminated in the insulating layer 30.
Preferably, described in the P-type electrode pad 51 of the P-type electrode 50, P-type electrode extension item 52 and a column
P-type electrode connection needle 53 is integrally formed, so that P-type electrode extension item 52 integrally extends the P-type electrode
Pad 51 integrally extends the P-type electrode extension item 52 with making the column P-type electrode connect needle 53 respectively.For example,
In a preferable examples of the semiconductor chip of the utility model, first using negtive photoresist on the surface of the insulating layer 30
P-type electrode figure is made, secondly the exposed position for needing to precipitate the P-type electrode 50 uses metal evaporation board evaporation metal
Layer, the mode for reusing metal-stripping remove extra metal layer, to form the p-type electricity for being laminated in the insulating layer 30
Pole 50.
Preferably, the N-type electrode 40 and the P-type electrode 50 of the semiconductor chip are by the same step shape
At.That is, the N-type electrode 40 and the P-type electrode 50 can be laminated simultaneously in the same step in the insulation
Layer 30.
It is noted that in this preferable examples of the semiconductor chip shown in attached drawing 2A to Fig. 7 B, the N
One column of the n type semiconductor layer 12 of the column N-type electrode connection needle 43 and extension unit 10 of type electrode 40 are led
Line between logical position connects needle 53 and the electrically conducting transparent with a column P-type electrode of the P-type electrode 50 for straight line
Line between one column conduction position of layer 20 is curve, in this way, when electric current is respectively from 40 He of N-type electrode
After the P-type electrode 50 is injected, electric current can equably be extended and be distributed with can be compound in the active area 13 and produce
Third contact of a total solar or lunar eclipse line so that the medium position of the semiconductor chip is consistent with the brightness of marginal position, and then is conducive to expand described half
The light-emitting area of conductor chip and the luminous efficiency for improving the semiconductor chip.
Although in a preferable examples of the semiconductor chip of the utility model shown in attached drawing 2A to Fig. 7 B, institute
State the company between the column P-type electrode connection needle 53 of P-type electrode 50 and a column conduction position of the transparency conducting layer 20
The curve type of line is camber line, in some modified examples of the semiconductor chip of the utility model, the P-type electrode 50
Column P-type electrode connection needle 53 and a column conduction position of the transparency conducting layer 20 between line curve type
It can be sigmoid curve.
Preferably, with continued reference to attached drawing 7A and Fig. 7 B, in the semiconductor chip of the utility model, the N-type electricity
One column conducting position of the n type semiconductor layer 12 of the column N-type electrode connection needle 43 and extension unit 10 of pole 40
One column of the area gradual change variation and the P-type electrode 50 the set P-type electrode connection needle 53 and the transparency conducting layer 20
The area gradual change of one column conduction position changes, and in this way, is conducive to be further ensured that from the N-type electrode 40 and institute
The electric current for stating the injection of P-type electrode 50 is equably extended.Specifically, in the semiconductor chip shown in attached drawing 7A and Fig. 7 B
This specific example in, the area of section gradual change variation of the column N-type electrode connection needle 43 of the N-type electrode 40, and
The area of section gradual change variation of one column of the P-type electrode 50 P-type electrode connection needle 53, in this way, favorably
In be further ensured that from the N-type electrode 40 and the P-type electrode 50 injection electric current equably extended.For example, in attached drawing
In this preferable examples of the semiconductor chip shown in 7A and Fig. 7 B, a column N-type electrode of the N-type electrode 40 connects
Connect the first end 101 direction of the area of section of needle 43 from the N-type electrode pad 41 to the semiconductor chip gradually
Increase connected with the one of the P-type electrode 50 column P-type electrode area of section of needle 53 from the P-type electrode pad 51 to
102 direction of the second end of the semiconductor chip gradually increases.Optionally, in the semiconductor core of the utility model
In other examples of piece, the area of section of the column N-type electrode connection needle 43 of the N-type electrode 40 is from the N-type electrode
Pad 41 to 101 direction of the first end of the semiconductor chip be gradually reduced and the P-type electrode 50 one column described in
P-type electrode connects the second end 102 of the area of section of needle 53 from the P-type electrode pad 51 to the semiconductor chip
Direction is gradually reduced.
Optionally, the N of a column of the N-type electrode 40 N-type electrode the connection needle 43 and the extension unit 10
Spacing gradual change variation between the adjacent conduction position of type semiconductor layer 12, correspondingly, a column P of the P-type electrode 50
Type electrode, which connects the spacing gradual change between needle 53 and the adjacent conduction position of the transparency conducting layer 20, to be changed, side in this way
Formula is conducive to be further ensured that the electric current from the N-type electrode 40 and the injection of the P-type electrode 50 is equably extended.Specifically
Ground is said, in this specific example of the semiconductor chip shown in attached drawing 7A and Fig. 7 B, a column institute of the N-type electrode 40
State the spacing gradual change variation in N-type electrode connection needle 43 between the two neighboring N-type electrode connection needle 43 and p-type electricity
Spacing gradual change variation in one column of the pole 50 P-type electrode connection needle 53 between the two neighboring P-type electrode connection needle 53,
In this way, be conducive to be further ensured that uniform from the electric current of the N-type electrode 40 and the injection of the P-type electrode 50
Ground extension.For example, in some examples of the semiconductor chip of the utility model, a column N of the N-type electrode 40
Type electrode connects the spacing in needle 43 between the two neighboring N-type electrode connection needle 43 from the N-type electrode pad 41 to institute
The first end 101 for stating semiconductor chip, which is gradually increased, connects needle with a column P-type electrode of the P-type electrode 50
Spacing in 53 between the two neighboring P-type electrode connection needle 53 is from the P-type electrode pad 51 to the semiconductor chip
The second end 102 gradually increase.In other examples of the semiconductor chip of the utility model, the N-type
The two neighboring N-type electrode connects the spacing between needle 43 from the N in one column of the electrode 40 N-type electrode connection needle 43
Type electrode pad 41 is gradually reduced to the first end 101 of the semiconductor chip and a column institute of the P-type electrode 50
State spacing in P-type electrode connection needle 53 between two neighboring P-type electrode connection needle 53 from the P-type electrode pad 51 to
The second end 102 of the semiconductor chip is gradually reduced.
With continued reference to attached drawing 2A to Fig. 7 B, the insulating layer 30 further has an at least feeler aperture 35, wherein described
Feeler aperture 35 is adjacent with p-type pad channel 33, and the feeler aperture 35 extends to the transparency conducting layer 20, with
A part of surface of the exposure transparency conducting layer 20 is in the feeler aperture 35 of the insulating layer 30.Correspondingly, the p-type
Electrode 50 includes at least one extension feeler 54, wherein the extension feeler 54 integrally extends the P-type electrode pad 51, and
And the extension feeler 54 extends to and is electrically connected to the electrically conducting transparent through the feeler aperture 35 of the insulating layer 30
Layer 20, in this way, the electric current injected from the P-type electrode 50 further can equably be extended.
Optionally, in other examples of the semiconductor chip of the utility model, the transparency conducting layer 20 has
There is at least one perforation, the feeler aperture 35 of the insulating layer 30 corresponds to and is connected to the described of the transparency conducting layer 20
Perforation, with the p type semiconductor layer 14 of the exposure extension unit 10 in the feeler aperture 35 of the insulating layer 30.Institute
The extension feeler 54 of P-type electrode 50 is stated through the feeler aperture 35 of the insulating layer 30 and the transparency conducting layer 20
The perforation extends to and is electrically connected to the p type semiconductor layer 14, in this way, from 50 note of P-type electrode
The electric current entered further can equably be extended.Also, the extension feeler 54 of the P-type electrode 50 passes through in the P
The mode that the p type semiconductor layer 14 is extended near type electrode pad 51, the energy when electric current is injected from the P-type electrode 50
Electric current is enough avoided to cause crowded bad phenomenon near the P-type electrode pad 51.
Attached drawing 8 shows a modified example of the semiconductor chip of the utility model, shows with attached drawing 2A to Fig. 7 B
It is described outer in this specific example of the semiconductor chip shown in attached drawing 8 unlike the semiconductor chip out
Prolong unit 10 with an exposed portion 151 of pad and an exposed portion 152 of extension item, wherein the exposed portion of the pad
151 prolong from the p type semiconductor layer 14 through the active area 13 in the middle part of the second end 102 of the semiconductor chip
The n type semiconductor layer 12 is extended to, with a part of surface of the exposure n type semiconductor layer 12 in the exposed portion 151 of the pad,
Wherein the extension exposed portion 152 of item is at the middle part of the extension unit 10 from the exposed portion 151 of the pad to the semiconductor
101 direction of the first end of chip extends, and the exposed portion 152 of extension item from the p type semiconductor layer 14 through institute
It states active area 13 and extends to the n type semiconductor layer 12, with a part of surface of the exposure n type semiconductor layer 12 in the expansion
Open up the exposed portion 152 of item.
There is the insulating layer 30 column N-type connection needle passageway 32 to connect needle passageway 34 with the two column p-types.It is described
One column of the insulating layer 30 N-type connection needle passageway 32 is at the middle part of the insulating layer 30 from N-type pad channel 31 to institute
101 direction of the first end for stating semiconductor chip extends, and in the thickness direction of the semiconductor chip, described in a column
N-type connection needle passageway 32 extends respectively to the n type semiconductor layer 12 of the extension unit 10, is partly led with the exposure N-type
A part of surface of body layer 12 connects needle passageway 32 in a column N-type of the insulating layer 30.30 liang of column institutes of the insulating layer
P-type connection needle passageway 34 is stated in symmetrical mode respectively at the edge of the insulating layer 30 from p-type pad channel 33
Extend to 102 direction of the second end of the semiconductor chip, and in the thickness direction of the semiconductor chip, each column
The p-type connection needle passageway 34 extends respectively to the transparency conducting layer 20, with a part of the exposure transparency conducting layer 20
Surface p-type described in each column of the insulating layer 30 connects needle passageway 34.
The N-type electrode 40 includes that a N-type electrode pad 41, one N-type electrode extends item 42 and one
The N-type electrode connection needle 43 is arranged, wherein the N-type electrode pad 41 of the N-type electrode 40 is in the semiconductor chip
The second end 102 is laminated in the insulating layer 30, and the N-type pad channel 31 through the insulating layer 30 extend to and
It is electrically connected to the n type semiconductor layer 12 of the extension unit 10, wherein the N-type electrode of the N-type electrode 40 expands
Open up the first end of the item 42 at the middle part of the insulating layer 30 from the N-type electrode pad 41 to the semiconductor chip
101 directions extend, wherein a column of the N-type electrode 40 N-type electrode connection needle 43 respectively extends from the N-type electrode and expands
Open up item 42, and the column N-type electrode connection needle 43 of the N-type electrode 40 is respectively described in the column through the insulating layer 30
N-type connection needle passageway 32 extends to and is electrically connected to the n type semiconductor layer 12 of the extension unit 10.
The P-type electrode 50 includes that 51, two P-type electrode extension items 52 of a P-type electrode pad and two column P-type electrodes connect
Needle 53 is connect, wherein the first end 101 of the P-type electrode pad 51 of the P-type electrode 50 in the semiconductor chip
Be laminated in the insulating layer 30, and the p-type pad channel 33 through the insulating layer 30 extend to and be electrically connected to it is described
The p type semiconductor layer 14 of extension unit 10, wherein each of described P-type electrode 50 P-type electrode extension item 52 is with phase
Mutually symmetrical mode is respectively at the edge of the insulating layer 30 from the P-type electrode pad 51 to described in the semiconductor chip
102 direction of the second end extends in curved manner, wherein the connection needle 53 of P-type electrode described in each column of the P-type electrode 50 divides
Each P-type electrode extension item 52 is not extended, and the connection needle 53 of P-type electrode described in each column of the P-type electrode 50 divides
The connection needle passageway 34 of p-type described in each column not through the insulating layer 30 extends to and is electrically connected to the transparency conducting layer 20.
According to the other side of the utility model, the utility model further provides for the manufacturer of the semiconductor chip
Method, wherein the manufacturing method includes the following steps:
(d) insulating layer 30 is etched, to form N-type pad channel 31 and from N-type pad channel 31 to institute
At least one column N-type connection needle passageway 32 that 101 direction of the first end of semiconductor chip extends is stated, wherein the N
Type pad channel 31 connects needle passageway 32 with a column N-type and extends respectively to the n type semiconductor layer 12；
(e) insulating layer 30 is etched, to form p-type pad channel 33 and from p-type pad channel 33 with curved
At least one column that bent mode extends to 102 direction of the second end of the semiconductor chip p-type connection needle passageway
34, wherein p-type pad channel 34 extends to the p type semiconductor layer 14, the column p-type connection needle passageway 34 is extended to
The transparency conducting layer 20；And
(f) N-type electrode 40 and the P-type electrode 50 are grown from the insulating layer 30, wherein the N-type electrode 40 passes through
N-type pad channel 31 connects needle passageway 32 with a column N-type and extends to and be electrically connected to the n type semiconductor layer
12, wherein the P-type electrode 50 extends to and is electrically connected to the p type semiconductor layer 14 through p-type pad channel 33, and
The transparency conducting layer 20 is extended to and is electrically connected to through the column p-type connection needle passageway 34, the semiconductor is made
Chip.
Preferably, the step (a) and the step (b) are completed in the same etching step.
It is worth noting that, " stacking " involved in the present invention can be direct stacking, it is also possible to indirectly
Stacking.For example, the n type semiconductor layer 12 of the extension unit 10, which is laminated in the substrate 11, can refer to the N-type half
Conductor layer 12 is directly laminated in the substrate 11, that is, directly grows the n type semiconductor layer from the surface of the substrate 11
12, so that the n type semiconductor layer 12 is laminated in the substrate 11；12 layers of the n type semiconductor layer of the extension unit 10
Being laminated on the substrate 11 may also mean that the n type semiconductor layer 12 is laminated in the substrate 11 indirectly, that is, in the substrate
Other layers, such as, but not limited to buffer layer are also provided between 11 and the n type semiconductor layer 12, that is, first described
Then the surface grown buffer layer of substrate 11 grows the n type semiconductor layer 12 on the surface of buffer layer again, so that the N
Type semiconductor layer 12 is laminated in the substrate 11.
It is worth noting that, showing the substrate of the semiconductor chip in the Figure of description of the utility model
11, the n type semiconductor layer 12, the active area 13, the p type semiconductor layer 14, the transparency conducting layer 20, the insulation
The thickness of layer 30, the N-type electrode 40 and the P-type electrode 50 is merely illustrative, is not offered as the substrate 11, the N-type
Semiconductor layer 12, the active area 13, the p type semiconductor layer 14, the transparency conducting layer 20, the insulating layer 30, the N
The actual thickness of type electrode 40 and the P-type electrode 50.Also, it is the substrate 11, the n type semiconductor layer 12, described active
Area 13, the p type semiconductor layer 14, the transparency conducting layer 20, the insulating layer 30, the N-type electrode 40 and p-type electricity
Actual proportions relationship between pole 50 is also unlike shown in the accompanying drawings.
It will be appreciated by those skilled in the art that above embodiments are only for example, wherein the feature of different embodiments
It can be combined with each other, do not explicitly pointed out in the accompanying drawings with obtaining being readily conceivable that according to the content that the utility model discloses
Embodiment.
It should be understood by those skilled in the art that foregoing description and the embodiments of the present invention shown in the drawings are only used as
It illustrates and is not intended to limit the utility model.The purpose of this utility model completely and effectively realizes.The function of the utility model
Energy and structural principle show and illustrate in embodiment, under without departing from the principle, the embodiments of the present invention
Can there are any deformation or modification.
Claims (15)
1. semiconductor chip, which is characterized in that including a substrate, the n type semiconductor layer that is laminated in the substrate, be laminated in
One active area of the n type semiconductor layer, is laminated in the P-type semiconductor at the p type semiconductor layer for being laminated in the active area
One transparency conducting layer of layer is laminated in an insulating layer of the transparency conducting layer and is respectively laminated on a N of the insulating layer
Type electrode and a P-type electrode,
Wherein the N-type electrode further comprises a N-type electrode pad, at least N-type electrode extension item and an at least column N-type
Electrode connects needle, and the N-type electrode pad is electrically connected to the n type semiconductor layer, the N-type after passing through the insulating layer
First end direction of the electrode extension item from the N-type electrode pad to the semiconductor chip extends, a column N-type electrode
Connection needle respectively extends from the N-type electrode extension item and is electrically connected to the N-type half respectively after passing through the insulating layer
Conductor layer；
Wherein the P-type electrode further comprises a P-type electrode pad, at least P-type electrode extension item and an at least column p-type
Electrode connects needle, and the P-type electrode pad is electrically connected to the p type semiconductor layer, the p-type after passing through the insulating layer
The second end direction of the electrode extension item from the P-type electrode pad to the semiconductor chip extends, a column P-type electrode
Connection needle respectively extends from P-type electrode extension item and is electrically connected to described transparent lead respectively after passing through the insulating layer
Electric layer, wherein between a column of the P-type electrode P-type electrode connection needle and a column conduction position of the transparency conducting layer
Line be curve.
2. semiconductor chip according to claim 1, wherein a column of the N-type electrode N-type electrode connection needle with
Line between one column conduction position of the n type semiconductor layer is straight line.
3. semiconductor chip according to claim 2, wherein a column of the P-type electrode P-type electrode connection needle with
The conducting area gradual change of one column conduction position of the transparency conducting layer changes, correspondingly, a column N of the N-type electrode
The conducting area gradual change that type electrode connects a column conduction position of needle and the n type semiconductor layer changes.
4. semiconductor chip as claimed in claim 3 a, wherein column of the P-type electrode P-type electrode connection needle and institute
The conducting area of a column conduction position of transparency conducting layer is stated from the P-type electrode pad to the second end of the semiconductor chip
Portion gradually increases, and correspondingly, a column of a column of the N-type electrode N-type electrode connection needle and the n type semiconductor layer are led
The conducting area of logical position is gradually increased from the N-type electrode pad to the first end of the semiconductor chip.
5. semiconductor chip according to claim 2, wherein a column of the P-type electrode P-type electrode connection needle with
Spacing gradual change variation in one column conduction position of the transparency conducting layer between two neighboring conduction position, correspondingly, the N
Two neighboring conducting position in the column N-type electrode connection needle of type electrode and a column conduction position of the n type semiconductor layer
Spacing gradual change variation between setting.
6. semiconductor chip according to claim 3, wherein a column of the P-type electrode P-type electrode connection needle with
Spacing gradual change variation in one column conduction position of the transparency conducting layer between two neighboring conduction position, correspondingly, the N
Two neighboring conducting position in the column N-type electrode connection needle of type electrode and a column conduction position of the n type semiconductor layer
Spacing gradual change variation between setting.
7. semiconductor chip according to claim 4, wherein a column of the P-type electrode P-type electrode connection needle with
Spacing gradual change variation in one column conduction position of the transparency conducting layer between two neighboring conduction position, correspondingly, the N
Two neighboring conducting position in the column N-type electrode connection needle of type electrode and a column conduction position of the n type semiconductor layer
Spacing gradual change variation between setting.
8. semiconductor chip according to claim 5, wherein a column of the P-type electrode P-type electrode connection needle with
Spacing in one column conduction position of the transparency conducting layer between two neighboring conduction position is from the P-type electrode pad to institute
The second end for stating semiconductor chip gradually becomes smaller, correspondingly, a column of the N-type electrode N-type electrode connection needle and institute
The spacing in a column conduction position of n type semiconductor layer between two neighboring conduction position is stated from the N-type electrode pad to institute
The first end for stating semiconductor chip gradually becomes smaller.
9. semiconductor chip according to claim 7, wherein a column of the P-type electrode P-type electrode connection needle with
Spacing in one column conduction position of the transparency conducting layer between two neighboring conduction position is from the P-type electrode pad to institute
The second end for stating semiconductor chip gradually becomes smaller, correspondingly, a column of the N-type electrode N-type electrode connection needle and institute
The spacing in a column conduction position of n type semiconductor layer between two neighboring conduction position is stated from the N-type electrode pad to institute
The first end for stating semiconductor chip gradually becomes smaller.
10. semiconductor chip according to claim 4, wherein a column of the P-type electrode P-type electrode connection needle
Area of section is gradually increased from the P-type electrode pad to the second end of the semiconductor chip, correspondingly, the N-type electricity
The area of section of one column of the pole N-type electrode connection needle is from the N-type electrode pad to the first end of the semiconductor chip
Portion gradually increases.
11. according to claim 1 to any semiconductor chip in 10, wherein the P-type electrode further comprises at least
One extends feeler, and the extension feeler is adjacent with the P-type electrode pad, wherein the extension feeler extends the p-type electricity
Pole pad and pass through the insulating layer after be electrically connected to the transparency conducting layer.
12. according to claim 1 to any semiconductor chip in 10, wherein the P-type electrode further comprises at least
One extends feeler, and the extension feeler is adjacent with the P-type electrode pad, wherein the extension feeler extends the p-type electricity
Pole pad and pass through the insulating layer after be electrically connected to the p type semiconductor layer.
13. according to claim 1 to any semiconductor chip in 10, wherein the N-type electrode includes a N-type
Electrode pad, a N-type electrode extension item and a column N-type electrode connect needle, wherein the N-type electrode pad in
The second end of the semiconductor chip is overlappingly formed in a corner of the insulating layer, and the N-type electrode extends item
Extend in first end direction of the edge of the insulating layer from the N-type electrode pad to the semiconductor chip, a column institute
It states N-type electrode connection needle and extends to and be electrically connected to the n type semiconductor layer behind the edge for passing through the insulating layer respectively；
Correspondingly, the P-type electrode includes a P-type electrode pad, a P-type electrode extension item and the column p-type electricity
Pole connects needle, wherein the P-type electrode pad is overlappingly formed in the insulating layer in the first end of the semiconductor chip,
The second end direction of the P-type electrode extension item from the P-type electrode pad to the semiconductor chip extends, described in a column
P-type electrode connects needle and extends to and be electrically connected to the transparency conducting layer after passing through the insulating layer.
14. semiconductor chip according to claim 11, wherein the N-type electrode include a N-type electrode pad,
One N-type electrode extension item and a column N-type electrode connect needle, wherein the N-type electrode pad is partly led in described
The second end of body chip is overlappingly formed in a corner of the insulating layer, and the N-type electrode extension item is described exhausted
First end direction of the edge of edge layer from the N-type electrode pad to the semiconductor chip extends, a column N-type electrode
Connection needle extends to and is electrically connected to the n type semiconductor layer behind the edge for passing through the insulating layer respectively；Correspondingly, institute
Stating P-type electrode includes that a P-type electrode pad, a P-type electrode extension item and a column P-type electrode connect needle,
Wherein the P-type electrode pad is overlappingly formed in the insulating layer, the p-type electricity in the first end of the semiconductor chip
Pole extends the second end direction of the item from the P-type electrode pad to the semiconductor chip and extends, and a column P-type electrode connects
It connects needle and extends to and be electrically connected to the transparency conducting layer after passing through the insulating layer.
15. according to claim 1 to any semiconductor chip in 10, wherein the N-type electrode includes a N-type
Electrode pad, a N-type electrode extension item and a column N-type electrode connect needle, wherein the N-type electrode pad in
The second end of the semiconductor chip is overlappingly formed in the middle part of the insulating layer, and the N-type electrode extension item is described
First end direction of the middle part of insulating layer from the N-type electrode pad to the semiconductor chip extends, the column N-type electricity
Connection needle in pole extends to and is electrically connected to the n type semiconductor layer behind the middle part for passing through the insulating layer respectively；Correspondingly,
The P-type electrode includes a P-type electrode pad, two P-type electrode extension items and the P-type electrode connection of two column
Needle, wherein the P-type electrode pad is overlappingly formed in the insulating layer, two institutes in the first end of the semiconductor chip
P-type electrode extension item is stated partly to lead at the edge of the insulating layer from the P-type electrode pad to described in a manner of being spaced apart from each other
The second end direction of body chip extends, and the connection needle of P-type electrode described in each column extends to and electric after passing through the insulating layer
It is connected to the transparency conducting layer.
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Effective date of registration: 20221024 Address after: Room 420-10, South Building, Torch Plaza, No. 56-58, Torch Road, Torch Park, Torch High-tech Zone, Xiamen, Fujian 361006 Patentee after: Xiamen Future Display Technology Research Institute Co.,Ltd. Address before: No. 259-269, xiangtian Road, industrial zone, torch hi tech Zone (Xiang'an), Xiamen City, Fujian Province, 361101 Patentee before: Xiamen Changelight Co.,Ltd. |
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