CN116646435A - Flip light-emitting diode chip and preparation method thereof - Google Patents
Flip light-emitting diode chip and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/10—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
Abstract
The invention relates to the technical field of semiconductor devices, in particular to a flip-chip light-emitting diode chip and a preparation method thereof, wherein the flip-chip light-emitting diode chip comprises a substrate, an epitaxial layer, a current blocking layer, a current expansion layer, an electrode layer, a Bragg reflection layer, a connection layer, a first insulating protection layer, a metal protection layer, a second insulating protection layer and a bonding pad layer which are sequentially laminated on the substrate; the connecting layer comprises a plurality of P-type connecting layers and a plurality of N-type connecting layers which are identical in structure, wherein the P-type connecting layers are formed by sequentially stacking a high-reflection metal layer, a protective metal layer and a current transmission layer, and the high-reflection metal layer is an Al layer or an Ag layer; the current transmission layer comprises at least two transmission sublayers which are sequentially laminated, the transmission sublayers are composed of a plurality of groups of periodically laminated TiW layers and Au layers, and the ratio of the thickness of the TiW layers to the thickness of the Au layers in different transmission sublayers along the growth direction of the chip is linearly increased. The LED chip of the invention has uniformly diffused current and can increase the maximum current which can be used by the LED chip.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a flip LED chip and a preparation method thereof.
Background
The flip LED chip is widely applied with the advantages of strong back light emitting capability, strong heat radiation capability, good welding performance, large thrust, strong reliability and the like, and people use the Bragg reflection layer as a reflector to enable the flip LED to emit light from the back, and in recent years, people start to increase high-reflectivity metal on the Bragg reflection layer to form a total reflection mirror in cooperation with the Bragg reflection layer, so that the reflectivity of the Bragg reflection layer is improved, and finally the external quantum efficiency of the flip LED chip is improved.
The metal on the Bragg reflection layer not only has the effect of matching the Bragg reflection layer to form a total reflection mirror, but also needs to transmit current to a plurality of electrodes below the Bragg reflection layer so that the current can be diffused to the whole LED chip, but when the current is injected into the metal on the Bragg reflection layer, most of the current can vertically flow into the electrode layer below the current injection opening through the reflection metal instead of being transversely transmitted to the electrode layer of the whole LED chip. In this way, current diffusion is uneven, so that the working voltage of the LED chip is high, and when the LED chip is used under high current, heat is mainly concentrated in the LED chip area below the current injection opening, so that the LED chip is at risk of burning; resulting in the LED chip not being used for a long time under a large current.
Disclosure of Invention
In order to solve the technical problems, the invention provides a flip LED chip and a preparation method thereof.
The invention adopts the following technical scheme: a flip LED chip comprises a substrate, an epitaxial layer, a current blocking layer, a current expansion layer, an electrode layer, a Bragg reflection layer, a connection layer, a first insulating protection layer, a metal protection layer, a second insulating protection layer and a bonding pad layer which are sequentially laminated on the substrate;
the connecting layer comprises a plurality of P-type connecting layers and a plurality of N-type connecting layers with the same structure, the P-type connecting layers comprise a high-reflection metal layer, a protective metal layer and a current transmission layer which are sequentially laminated, the high-reflection metal layer is an Al layer or an Ag layer, and the protective metal layer is formed by laminating one or more of a Ti layer, a Pt layer, a Ni layer, a Cr layer and a Pb layer;
the current transmission layer comprises at least two transmission sublayers which are sequentially laminated, wherein each transmission sublayer consists of 3-5 groups of periodically laminated TiW layers and Au layers, the thickness ratio of the TiW layers in different transmission sublayers is 10% -40% of the thickness of the Au layers, and the thickness ratio of the TiW layers in different transmission sublayers along the growth direction of the chip is linearly increased;
the distance from the edge of the P-type connecting layer to the edge of the N-type connecting layer is 20-40 mu m.
According to the flip LED chip provided by the embodiment of the invention, the high-reflection metal layer can be matched with the Bragg reflection layer to form total reflection, so that the reflectivity is ensured, and the high-reflection metal layer can be prevented from migration and oxidization by the protective metal layer; the current transmission layer is provided with a plurality of transmission sublayers consisting of a TiW layer and an Au layer which are periodically laminated, and the proportion of the thickness of the TiW layer to the thickness of the Au layer in different transmission sublayers along the growth direction of the chip is linearly increased, so that current is firstly transmitted transversely and then transmitted vertically when being injected into the connection layer, the current of the LED chip is uniformly diffused, and the usable maximum current of the LED chip can be increased; and if the distance from the edge of the P-type connecting layer to the edge of the N-type connecting layer is smaller than 20 mu m, under the condition that the LED chip is electrified, electromigration is very easy to occur between the edge of the P-type connecting layer and the edge of the N-type connecting layer to cause short circuit of the LED chip, and if the distance is too large, the whole area of the P-type connecting layer and the N-type connecting layer is smaller, so that the total reflection effect formed by the connecting layer and the Bragg reflection layer is influenced, and therefore, the moderate distance from the edge of the P-type connecting layer to the edge of the N-type connecting layer can ensure the stable work of the LED chip and has good luminous effect.
Further, the epitaxial layer comprises an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer which are sequentially laminated on the substrate, isolation grooves are formed in the periphery of the N-type semiconductor layer, and the Bragg reflection layer, the first insulating protection layer and the second insulating protection layer are all extended and covered on the isolation grooves.
Further, the current blocking layer is a plurality of SiO with the diameter of 20-50 μm 2 Discs or Al 2 O 3 And the discs are arranged on the P-type semiconductor layer.
Further, the current expansion layer covers and extends the current blocking layer to the P-type semiconductor layer, and the distance from the edge of the current expansion layer to the edge of the P-type semiconductor layer is 3-10 μm.
Further, the electrode layer comprises a plurality of P-type electrode layers and a plurality of N-type electrode layers, the P-type electrode layers and the N-type electrode layers are all metal discs with the diameters of 10-30 μm, and the P-type electrode layers are positioned on the current expansion layer and concentric with the current blocking layer; the distance from the edge of the P-type electrode layer to the edge of the current blocking layer is 5-15 mu m; the N-type electrode layer is positioned on the N-type semiconductor layer and is electrically connected with the N-type semiconductor layer, and the distance from the edge of the N-type electrode layer to the edge of the P-type semiconductor layer is 7-10 mu m.
Further, the Bragg reflection layer is formed by periodically laminating 20-40 groups of TiO 2 Layer and SiO 2 The Bragg reflection layer is provided with a plurality of first through holes, the connecting layer is connected with the electrode layer through the first through holes, and the distance from the edge of the first through holes to the edge of the electrode layer is 2-10 mu m.
Further, the first insulating protection layer and the second insulating protection layer are both SiO 2 Layer, al 2 O 3 A layer or SiN layer, the first insulating protection layer and the second insulating protection layer are respectively provided with a second through hole penetrating through the first insulating protection layer and the second insulating protection layer, and the bonding pad layer is electrically connected with the connecting layer through the second through holesAnd the distance from the edge of the second through hole to the edge of the connecting layer is 10-15 mu m.
Further, the pad layer is disposed on the second insulating protection layer, and includes a P-type pad layer and an N-type pad layer, where a distance from an edge of the P-type pad layer to an edge of the N-type pad layer is between 200 μm and 300 μm.
Further, the metal protection layer comprises a P-type metal protection layer, an N-type metal protection layer and an anti-thimble layer, wherein the P-type metal protection layer is arranged between the first insulating protection layer and the second insulating protection layer above the N-type connection layer on one side of the P-type bonding pad layer, the projection width of the P-type metal protection layer on the substrate is larger than the projection width of the N-type connection layer on the substrate, and the distance from the projection edge of the P-type metal protection layer on the substrate to the projection edge of the N-type connection layer on the substrate is 5-15 μm;
the N-type metal protection layer is arranged between the first insulating protection layer and the second insulating protection layer on the P-type connection layer at one side of the N-type bonding pad layer, the projection width of the N-type metal protection layer on the substrate is larger than that of the P-type connection layer on the substrate, and the distance from the projection edge of the N-type metal protection layer on the substrate to the projection edge of the P-type connection layer on the substrate is 5-15 mu m;
the thimble preventing layer is arranged between the first insulating protective layer and the second insulating protective layer at the center of the flip LED chip, and the thimble preventing layer is a disc with the diameter of 50-100 mu m.
Correspondingly, the invention also provides a preparation method of the flip LED chip, which is used for preparing the flip LED chip, and comprises the following steps:
providing a substrate;
depositing an epitaxial layer on the substrate, wherein the epitaxial layer comprises an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer;
preparing an isolation groove on the N-type semiconductor layer;
depositing a current blocking layer on the P-type semiconductor layer, wherein the current blocking layer extends to the N-type semiconductor layer and covers the isolation groove;
depositing a current spreading layer on the current blocking layer;
depositing an electrode layer on the current expansion layer and the N-type semiconductor layer, wherein the electrode layer comprises a P-type electrode layer positioned on the current expansion layer and an N-type electrode layer positioned on the N-type semiconductor layer;
depositing a Bragg reflection layer on the electrode layer;
depositing a connecting layer on the Bragg reflection layer, wherein the connecting layer comprises a P-type connecting layer electrically connected with the P-type electrode layer and an N-type connecting layer electrically connected with the N-type electrode layer;
depositing a first insulating protection layer on the connection layer;
depositing a metal protection layer on the first insulating protection layer;
depositing a second insulating protective layer on the metal protective layer;
and depositing a bonding pad layer on the second insulating protective layer, wherein the bonding pad layer comprises a P-type bonding pad electrically connected with the P-type connecting layer and an N-type bonding pad electrically connected with the N-type connecting layer.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic view of a flip-chip led chip according to a first embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view of a flip-chip LED chip along line AA in FIG. 1 according to a first embodiment of the present invention;
fig. 3 is a schematic cross-sectional view of a flip-chip led chip according to a first embodiment of the present invention along the line BB in fig. 1;
fig. 4 is a flowchart of a method for manufacturing a flip-chip light emitting diode chip according to a second embodiment of the present invention.
Reference numerals illustrate:
10. a substrate; 11. an epitaxial layer; 111. an N-type semiconductor layer; 112. an active light emitting layer; 113. a P-type semiconductor layer; 114. an isolation groove; 12. a current blocking layer; 13. a current spreading layer; 14. an electrode layer; 141. a P-type electrode layer; 142. an N-type electrode layer; 15. a Bragg reflection layer; 151. a first through hole; 152. p-type Bragg through holes; 153. an N-type Bragg via; 16. a connection layer; 161. a P-type connection layer; 162. an N-type connection layer; 163. a highly reflective metal layer; 164. a protective metal layer; 165. a current transport layer; 166. a transmission sub-layer; 1661. a first sub-layer; 1662. a second sub-layer; 17. a first insulating protective layer; 18. a metal protective layer; 181. a P-type metal protection layer; 182. an N-type metal protection layer; 183. an anti-thimble layer; 19. a second insulating protective layer; 191. a second through hole; 192. p-type insulating protective layer through holes, 193, N-type insulating protective layer through holes; 20. a pad layer; 201. a P-type bonding pad layer; 202. an N-type bonding pad layer.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and intended to illustrate embodiments of the invention and should not be construed as limiting the invention.
In the description of the embodiments of the present invention, it should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the embodiments of the present invention and simplify description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present invention, the meaning of "plurality" is two or more, unless explicitly defined otherwise.
In the embodiments of the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured" and the like are to be construed broadly and include, for example, either permanently connected, removably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the embodiments of the present invention will be understood by those of ordinary skill in the art according to specific circumstances.
Example 1
Referring to fig. 1 to 3, a flip-chip light emitting diode chip according to a first embodiment of the present invention includes a substrate 10, and an epitaxial layer 11, a current blocking layer 12, a current spreading layer 13, an electrode layer 14, a bragg reflection layer 15, a connection layer 16, a first insulating protection layer 17, a metal protection layer 18, a second insulating protection layer 19, and a pad layer 20 sequentially stacked on the substrate 10;
the connection layer 16 comprises a plurality of P-type connection layers 161 and a plurality of N-type connection layers 162 with the same structure, the P-type connection layers 161 are composed of a high reflection metal layer 163, a protection metal layer 164 and a current transmission layer 165 which are sequentially stacked, the high reflection metal layer 163 is an Al layer or an Ag layer, and the protection metal layer 164 is one or a plurality of stacked layers of a Ti layer, a Pt layer, a Ni layer, a Cr layer and a Pb layer;
the current transmission layer 165 comprises at least two transmission sublayers 166 which are sequentially laminated, the transmission sublayers 166 are composed of 3-5 groups of periodically laminated TiW layers and Au layers, the ratio of the thickness of the TiW layers in the different transmission sublayers 166 to the thickness of the Au layers is 10% -40%, and the ratio of the thickness of the TiW layers in the different transmission sublayers 166 along the growth direction of the chip to the thickness of the Au layers is linearly increased;
the distance e from the edge of the P-type connection layer 161 to the edge of the N-type connection layer 162 is 20 μm-40 μm.
In this embodiment, the highly reflective metal layer 163 is an Ag layer, and the protective metal layer 164 is a Ti layer; the current transmission layer 165 comprises two transmission sublayers 166 which are sequentially laminated and are divided into a first sublayer 1661 and a second sublayer 1662, wherein the two transmission sublayers 166 are composed of 3 groups of periodically laminated TiW layers and Au layers, the thickness of each TiW layer in the first sublayer 1661 is 10% of the thickness of each Au layer, and the thickness of each TiW layer in the second sublayer 1662 is 20% of the thickness of each Au layer; in specific implementation, the current transmission layer 165 may include four transmission sublayers 166 stacked in sequence, where the thickness of each TiW layer in the third transmission sublayer 166 is 30% of the thickness of each Au layer, and the thickness of each TiW layer in the fourth transmission sublayer 166 is 40% of the thickness of each Au layer, and the method is not limited thereto; the distance e from the edge of the P-type connection layer 161 to the edge of the N-type connection layer 162 is 30 μm.
In the flip-chip light emitting diode chip of the embodiment of the invention, the high-reflection metal layer 163 can be matched with the Bragg reflection layer 15 to form total reflection, so that the reflectivity is ensured, and the protective metal layer 164 can protect the high-reflection metal layer 163 from migration and oxidization; the current transmission layer 165 has a plurality of transmission sublayers 166 composed of periodically laminated TiW layers and Au layers, and the ratio of the thickness of the TiW layers to the thickness of the Au layers in different transmission sublayers 166 along the growth direction of the chip increases linearly, so that current is firstly transmitted transversely and then transmitted vertically when being injected into the connection layer 16, the current of the LED chip is uniformly diffused, and the available maximum current of the LED chip can be increased; and if the distance from the edge of the P-type connection layer 161 to the edge of the N-type connection layer 162 is less than 20 μm, under the condition that the LED chip is electrified, electromigration is very easy to occur between the edge of the P-type connection layer 161 and the edge of the N-type connection layer 162 to cause short circuit of the LED chip, if the distance is too large, the overall area of the P-type connection layer 161 and the N-type connection layer 162 is smaller, and the total reflection effect formed by the connection layer 16 and the bragg reflection layer 15 is affected, so that the distance from the edge of the P-type connection layer 161 to the edge of the N-type connection layer 162 is moderate, the stable operation of the LED chip can be ensured, and the LED chip has good luminous effect.
The epitaxial layer 11 comprises an N-type semiconductor layer 111, an active light emitting layer 112 and a P-type semiconductor layer 113 which are sequentially stacked on the substrate 10, an isolation groove 114 is formed around the N-type semiconductor layer 111, and the bragg reflection layer 15, the first insulating protection layer 17 and the second insulating protection layer 19 extend and cover the isolation groove 114, so that external water vapor can be effectively prevented from oxidizing the epitaxial layer 11.
The current blocking layer 12 is a plurality of SiO layers with diameters of 20 μm to 50 μm 2 Discs or Al 2 O 3 A disk, all disposed on the P-type semiconductor layer 113; if the diameter of the current blocking layer 12 is smaller than 20 μm, the ESD resistance of the LED chip will be deteriorated, and if the diameter is larger, the ESD resistance is better, but if the diameter is larger than 50 μm, the operation voltage of the LED chip will be increased sharply; in the present embodiment, the current blocking layer 12 is a plurality of SiO layers having a diameter of 35 μm 2 The number of the discs is determined according to the size of the chip.
The current expansion layer 13 covers and extends the current blocking layer 12 onto the P-type semiconductor layer 113, and the distance a from the edge of the current expansion layer 13 to the edge of the P-type semiconductor layer 113 is 3 μm-10 μm; if the distance between the edge of the current expansion layer 13 and the edge of the P-type semiconductor layer 113 is less than 3 μm, the current expansion layer 13 is easily contacted with the side wall of the P-type semiconductor layer 113, so that the LED chip is conducted under reverse current, the LED chip is invalid, the area of the current expansion layer 13 is too small if the distance is too large, the current expansion is difficult, and the working voltage of the LED chip is too high; in this embodiment, the distance a from the edge of the current spreading layer 13 to the edge of the P-type semiconductor layer 113 is 6 μm, and the area of the current spreading layer 13 is 50% -98% of the area of the P-type semiconductor layer 113, and in a specific implementation, the area of the current spreading layer 13 is 70% of the area of the P-type semiconductor layer 113.
The electrode layer 14 comprises a plurality of P-type electrode layers 141 and a plurality of N-type electrode layers 142, the P-type electrode layers 141 and the N-type electrode layers 142 are all metal discs with diameters of 10 μm-30 μm, and the P-type electrode layers 141 are positioned on the current expansion layer 13 and concentric with the current blocking layer 12; the distance b from the edge of the P-type electrode layer 141 to the edge of the current blocking layer 12 is 5 μm to 15 μm; the N-type electrode layer 142 is located on the N-type semiconductor layer 111 and electrically connected with the N-type semiconductor layer 111, and the distance c from the edge of the N-type electrode layer 142 to the edge of the P-type semiconductor layer 113 is 7 μm-10 μm; the diameters of the P-type electrode layer 141 and the N-type electrode layer 142 are too small to cause the working voltage of the LED chip to rise, and too large to cause the brightness to drop, between 10 μm and 30 μm, so that the working voltage and the brightness can be balanced; the distance from the edge of the P-type electrode layer 141 to the edge of the current blocking layer 12 is set to enhance the anti-static breakdown capability of the LED chip, the larger the distance is, the better the effect is, but the larger the distance is, the larger the operating voltage of the LED chip is, the higher the operating voltage of the LED chip is; the distance from the edge of the N-type electrode layer 142 to the edge of the P-type semiconductor layer 113 is set to avoid the short circuit failure of the LED chip caused by the migration of the metal of the N-type electrode to the P-type semiconductor under the condition of power on; in this embodiment, the number of the P-type electrode layers 141 is the same as the number of the current blocking layers 12, the area of the P-type electrode layers 141 is smaller than the area of the current blocking layers 12, and the metal disc of the electrode layer 14 may be one or more of a Cr layer, a Ni layer, an Al layer, an AlCu layer, a Ti layer, a Pt layer, an Au layer, an Ag layer, and a Cu layer; the P-type electrode layer 141 is a metal disk having a diameter of 20 μm, the N-type electrode layer 142 is a metal disk having a diameter of 25 μm, the distance b from the edge of the P-type electrode layer 141 to the edge of the current blocking layer 12 is 10 μm, and the distance c from the edge of the N-type electrode layer 142 to the edge of the P-type semiconductor layer 113 is 9 μm.
The Bragg reflection layer 15 is a periodically laminated TiO of 20-40 groups 2 Layer and SiO 2 The Bragg reflection layer 15 is provided with a plurality of first through holes 151, the connection layer 16 is connected with the electrode layer 14 through the first through holes 151, and the distance d between the edge of the first through holes 151 and the edge of the electrode layer 14 is 2-10 mu m; the diameter of the first through hole 151 is smaller than that of the electrode layer 14, so that the electrode layer 14 in the first through hole 151 cannot be completely covered by the connecting layer 16, and the chip reliability of the LED chip is effectively improved; in this embodiment, the Bragg reflection layer 15 is 28 groups of periodically stacked TiO 2 Layer and SiO 2 The layer composition, the first through hole 151 projects into a circle of 4 μm-20 μm, and projects into a concentric circle with the electrode layer 14, the first through hole 151 disposed on the P-type electrode layer 141 is a P-type Bragg through hole 152, the first through hole 151 disposed on the N-type electrode layer 142 is an N-type Bragg through hole 153, and in specific implementation, the first through hole 151 projects into a circle of 15 μm; edge of first through hole 151The distance d to the edge of the electrode layer 14 is 5 μm.
The first insulating protective layer 17 and the second insulating protective layer 19 are both SiO 2 Layer, al 2 O 3 The layer or SiN layer is provided with a second through hole 191 penetrating through the first insulating protective layer 17 and the second insulating protective layer 19, the bonding pad layer 20 is electrically connected with the connecting layer 16 through the second through hole 191, and the distance f from the edge of the second through hole 191 to the edge of the connecting layer 16 is 10-15 mu m; the pad layer 20 is disposed on the second insulating protective layer 19 and includes a P-type pad layer 201 and an N-type pad layer 202, and a distance h between an edge of the P-type pad layer 201 and an edge of the N-type pad layer 202 is 200 μm to 300 μm.
The distance from the edge of the second through hole 191 to the edge of the connection layer 16 can prevent the bonding pad layer 20 from forming a cavity at the edge of the connection layer 16 when the bonding pad layer 20 is connected with the edge of the connection layer 16 through the second through hole 191, and finally the reliability of the LED chip is reduced; the second through hole 191 disposed on the P-type connection layer 161 is a P-type insulation protection layer through hole 192, and the second through hole 191 disposed on the N-type connection layer 162 is an N-type insulation protection layer through hole 193; the distance from the edge of the P-type bonding pad layer 201 to the edge of the N-type bonding pad layer 202 is used for avoiding the problem that in the subsequent packaging process, a bonding pad arranged on the P-type bonding pad layer 201 and a bonding pad arranged on the N-type bonding pad layer 202 are connected together in the reflow process to cause short circuit failure of an LED chip, the distance is required to be larger than 200 mu m, the larger the effect is, but the larger the effect is, the larger the corresponding area of the P-type bonding pad layer 201 and the N-type bonding pad layer 202 is, the problem that the bonding force between the P-type bonding pad layer 201 and the N-type bonding pad layer 202 is reduced is caused, so the maximum distance is set to be 300 mu m; in the present embodiment, the first insulating protection layer 17 and the second insulating protection layer 19 are both SiO 2 The P-type bonding pad layer 201 is electrically connected with the P-type connecting layer 161 through the P-type insulating protection layer through hole 192, and the N-type bonding pad layer 202 is electrically connected with the N-type connecting layer 162 through the N-type insulating protection layer through hole 193; the edge-to-edge distance f from the second via 191 to the connection layer 16 is 10 μm, and the edge-to-edge distance h from the P-type pad layer 201 to the N-type pad layer 202 is 200 μm; the bonding pad layer 20 may be one or more of an Al layer, a Ti layer, a Pt layer, a Ni layer, an Au layer, a Sn layer, and an AuSn layer, and in particular, the bonding pad layer 20 is an Au layer.
The metal protection layer 18 comprises a P-type metal protection layer 181, an N-type metal protection layer 182 and an anti-thimble layer 183, the P-type metal protection layer 181 is arranged between the first insulation protection layer 17 and the second insulation protection layer 19 on the N-type connection layer 162 on one side of the P-type bonding pad layer 201, the projection width of the P-type metal protection layer 181 on the substrate 10 is larger than the projection width of the N-type connection layer 162 on the substrate 10, and the projection distance g1 from the projection edge of the P-type metal protection layer 181 on the substrate 10 to the projection edge of the N-type connection layer 162 on the substrate 10 is between 5 μm and 15 μm; the N-type metal protection layer 182 is disposed between the first insulating protection layer 17 and the second insulating protection layer 19 above the P-type connection layer 161 on one side of the N-type pad layer 202, and the projected width of the N-type metal protection layer 182 on the substrate 10 is greater than the projected width of the P-type connection layer 161 on the substrate 10, and the distance g2 from the projected edge of the N-type metal protection layer 182 on the substrate 10 to the projected edge of the P-type connection layer 161 on the substrate 10 is between 5 μm and 15 μm; the thimble preventing layer 183 is arranged between the first insulating protection layer 17 and the second insulating protection layer 19 at the center of the flip LED chip, and the thimble preventing layer 183 is a disc with the diameter of 50-100 μm.
The distance from the projection edge of the P-type metal protection layer 181 on the substrate 10 to the projection edge of the N-type connection layer 162 on the substrate 10 is set to ensure that the projection of the P-type metal protection layer 181 on the substrate 10 completely covers the N-type connection layer 162 of the part; the distance from the projection edge of the N-type metal protection layer 182 on the substrate 10 to the projection edge of the P-type connection layer 161 on the substrate 10 is set to ensure that the projection of the N-type metal protection layer 182 on the substrate 10 completely covers the P-type connection layer 161; the thimble preventing layer 183 can prevent the sorting thimble from propping the LED chip during the sorting process of the LED chip, the diameter of 50-100 μm is set as the searching precision of the thimble, the thimble is prevented from propping off, and the thimble does not prop against the disc of the thimble preventing layer 183; in this embodiment, the metal protection layer 18 may Be one or more of inert metals such as an Al layer, a Cr layer, a Ni layer, an Sb layer, and a Be layer, and in the specific implementation, the metal protection layer 18 is a Ni layer; the distance g1 from the projection edge of the P-type metal protection layer 181 to the projection edge of the N-type connection layer 162 is 12 μm, the distance g2 from the projection edge of the N-type metal protection layer 182 to the projection edge of the P-type connection layer 161 is 12 μm, and the anti-thimble layer 183 is a disk with a diameter of 75 μm.
Example 2
Referring to fig. 4, correspondingly, the invention further provides a preparation method of the flip-chip light emitting diode chip, which is used for preparing the flip-chip light emitting diode chip, and comprises the following steps:
s1: providing a substrate 10; the substrate 10 is made of light-transmitting material, and may be a GaN layer, an AlN layer, or Al 2 O 3 A layer; in this embodiment, the substrate 10 is a GaN layer.
S2: depositing an epitaxial layer 11 on the substrate 10, the epitaxial layer 11 including an N-type semiconductor layer 111, an active light emitting layer 112, a P-type semiconductor layer 113; in this embodiment, an N-type semiconductor layer 111, an active light emitting layer 112, and a P-type semiconductor layer 113 are grown in this order using an MOCVD (metal organic chemical vapor deposition) process.
S3: an isolation trench 114 is prepared on the N-type semiconductor layer 111; specifically, photoresist is coated on the P-type semiconductor layer 113, then part of the photoresist is removed by exposure and development, part of the P-type semiconductor layer 113 around and inside the LED chip is exposed, then the exposed P-type semiconductor layer 113 and the active light emitting layer 112 below the part of the P-type semiconductor layer 113 are removed by utilizing an inductively coupled plasma etching process, the N-type semiconductor layer 111 is exposed, and then the rest of the photoresist is removed, so that the P-type semiconductor layer 113, the active light emitting layer 112 and the N-type semiconductor layer 111 of the LED chip are obtained; then, photoresist is coated on the surfaces of the N-type semiconductor layer 111 and the P-type semiconductor layer 113, then part of the photoresist is removed by exposure and development, part of the N-type semiconductor layer 111 around the LED chip is exposed, then the exposed N-type semiconductor layer 111 is removed by inductively coupled plasma etching, the substrate 10 is exposed, isolation grooves 114 are formed, and then the rest of the photoresist is removed.
S4: depositing a current blocking layer 12 on the P-type semiconductor layer 113, the current blocking layer 12 extending onto the N-type semiconductor layer 111 and covering the isolation trench 114; specifically, a PECVD (plasma enhanced chemical vapor deposition) process is used to deposit SiO (silicon dioxide) on the surfaces of the P-type semiconductor layer 113, the N-type semiconductor layer 111 and the isolation groove 114 2 Then at SiO 2 Coating photoresist on the surface, exposing and developingRemoving part of the photoresist to expose part of SiO 2 Then the exposed SiO is corroded by using BOE corrosive liquid 2 The photoresist is then removed to form a current blocking layer 12, the current blocking layer 12 having a disk structure with a diameter of 35 μm.
S5: depositing a current spreading layer 13 on the current blocking layer 12; specifically, ITO (indium tin oxide) is then deposited on the surfaces of the P-type semiconductor layer 113, the N-type semiconductor layer 111, the isolation groove 114, and the current blocking layer 12 by using a dispenser (magnetron sputtering) process, then a photoresist is coated on the ITO surface, then a part of the photoresist is removed by exposure and development, a part of the ITO is exposed, and then FeCl is used 3 Etching the exposed ITO by the mixed solution of HCl and photoresist to form a current expansion layer 13; the distance between the edge of the current spreading layer 13 and the edge of the P-type semiconductor layer 113 is equal to 6 μm.
S6: depositing an electrode layer 14 on the current spreading layer 13 and the N-type semiconductor layer 111, wherein the electrode layer 14 comprises a P-type electrode layer 141 on the current spreading layer 13 and an N-type electrode layer 142 on the N-type semiconductor layer 111; specifically, negative photoresist is coated on the surfaces of the isolation groove 114, the N-type semiconductor layer 111 and the current expansion layer 13, then part of the photoresist is exposed and developed to expose part of the N-type semiconductor layer 111 and part of the current expansion layer 13, then Cr/Al/Ti/Pt/Ni/Au metal is evaporated by utilizing an electron beam evaporation process, then the metal on the residual photoresist is removed by utilizing a blue film stripping technology, and then the residual photoresist is removed to obtain a P-type electrode layer 141 and an N-type electrode layer 142; the P-type electrode layer 141 has a diameter of 20 μm, the N-type electrode layer 142 has a diameter of 25 μm, the edge of the P-type electrode layer 141 is spaced apart from the edge of the current blocking layer 12 by a distance equal to 10 μm, and the edge of the N-type electrode layer 142 is spaced apart from the edge of the P-type semiconductor layer 113 by a distance equal to 9 μm.
S7: depositing a bragg reflection layer 15 on the electrode layer 14; specifically, 28 groups of SiO are periodically stacked in this order on the surfaces of the isolation trench 114, the N-type semiconductor layer 111, the current spreading layer 13, and the electrode layer 14 by using the electron beam vapor deposition technique 2 And TiO 2 The Bragg reflection layer 15 is formed, then photoresist is coated on the surface of the Bragg reflection layer 15, then part of the photoresist is removed by exposure and development, and then inductive coupling and the like are utilizedThe exposed Bragg reflection layer 15 is removed by an ion etching process, and then the residual photoresist is removed to form a P-type Bragg through hole 152 and an N-type Bragg through hole 153; the distance between the edge of the P-type Bragg via 152 or the N-type Bragg via 153 and the edge of the electrode layer 14 is equal to 5 μm.
S8: depositing a connection layer 16 on the Bragg reflection layer 15, wherein the connection layer 16 comprises a P-type connection layer 161 electrically connected with the P-type electrode layer 141 and an N-type connection layer 162 electrically connected with the N-type electrode layer 142; specifically, a negative photoresist is coated on the surface of the Bragg reflection layer 15, then part of the photoresist is removed by exposure and development, and then the high reflection metal layer 163, the protection metal layer 164 and the current transmission layer 165 of the connection layer 16 are sequentially evaporated by utilizing an electron beam evaporation technology, wherein the current transmission layer 165 comprises a first sub-layer 1661 and a second sub-layer 1662; the high-reflection metal layer 163 is a metal Ag layer, the protection metal layer 164 is a Ti layer, the first sub-layer 1661 is a periodic lamination of 3 groups of TiW layers and Au layers, wherein the thickness of the TiW layers is 10% of that of the Au layers; second sub-layer 1662 is a stack of 3 groups of TiW layers and Au layers, wherein the thickness of the TiW layers is 20% of the Au layers; the edge-to-N connection layer 162 edge distance of P-type connection layer 161 is equal to 30 μm.
S9: depositing a first insulating protection layer 17 on the connection layer 16; specifically, a PECVD process is used to deposit SiO on the surface of the connection layer 16 and the Bragg reflection layer 15 uncovered by the connection layer 16 2 A first insulating protective layer 17 is formed.
S10: depositing a metal protection layer 18 on the first insulating protection layer 17; specifically, a negative photoresist is coated on the surface of the first insulating protection layer 17, then part of the photoresist is removed by exposure and development, then an Ni layer is evaporated by an electron beam evaporation process, then metal on the residual photoresist is removed by a blue film stripping process, and then the residual photoresist is removed to obtain a metal protection layer 18, wherein the metal protection layer 18 comprises a P-type metal protection layer 181, an N-type metal protection layer 182 and an anti-thimble layer 183, the distance from the edge of the P-type metal protection layer 181 to the N-type connection layer 162 is equal to 12 mu m, and the distance from the edge of the N-type metal protection layer 182 to the P-type connection layer 161 is equal to 12 mu m.
S11: depositing a second insulating protective layer 19 on the metal protective layer 18; specifically, in the metal protection layer 18 and the non-alloy layerThe surface of the first insulating protective layer 17 covered by the protective layer 18 is deposited with SiO by PECVD process 2 And (3) obtaining a second insulating protection layer 19, coating photoresist on the surface of the second insulating protection layer 19, removing part of the photoresist to expose part of the second insulating protection layer 19, and removing the exposed second insulating protection layer 19 and the first insulating protection layer 17 below the second insulating protection layer by using an inductively coupled plasma etching process to form a P-type insulating protection layer through hole 192 and an N-type insulating protection layer through hole 193, wherein the distance from the edge of the P-type insulating protection layer through hole 192 or the N-type insulating protection layer through hole 193 to the edge of the connecting layer 16 is equal to 10 mu m.
S12: depositing a pad layer 20 on the second insulating protection layer 19, the pad layer 20 including a P-type pad electrically connected to the P-type connection layer 161 and an N-type pad electrically connected to the N-type connection layer 162; specifically, negative photoresist is coated on the surfaces of the second insulating protection layer 19, the P-type insulating protection layer through hole 192 and the N-type insulating protection layer through hole 193, then part of the photoresist is removed by exposure and development, then an Au layer is evaporated, then the metal on the rest of the photoresist is removed by a blue film stripping process, then the photoresist is removed, and a P-type pad layer 201 and an N-type pad layer 202 are obtained, wherein the distance from the edge of the P-type pad layer 201 to the edge of the N-type pad layer 202 is equal to 200 mu m.
According to the preparation method of the flip LED chip, the high-reflection metal layer 163 can be matched with the Bragg reflection layer 15 to form total reflection, so that the reflectivity is ensured, and the protective metal layer 164 can protect the high-reflection metal layer 163 from migration and oxidization; the current transmission layer 165 has a plurality of transmission sublayers 166 composed of periodically laminated TiW layers and Au layers, and the ratio of the thickness of the TiW layers to the thickness of the Au layers in different transmission sublayers 166 along the growth direction of the chip increases linearly, so that current is firstly transmitted transversely and then transmitted vertically when being injected into the connection layer 16, the current of the LED chip is uniformly diffused, and the available maximum current of the LED chip can be increased; and if the distance from the edge of the P-type connection layer 161 to the edge of the N-type connection layer 162 is less than 20 μm, under the condition that the LED chip is electrified, electromigration is very easy to occur between the edge of the P-type connection layer 161 and the edge of the N-type connection layer 162 to cause short circuit of the LED chip, if the distance is too large, the overall area of the P-type connection layer 161 and the N-type connection layer 162 is smaller, and the total reflection effect formed by the connection layer 16 and the bragg reflection layer 15 is affected, so that the distance from the edge of the P-type connection layer 161 to the edge of the N-type connection layer 162 is moderate, the stable operation of the LED chip can be ensured, and the LED chip has good luminous effect.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above additional technical features can be freely combined and superimposed by a person skilled in the art without conflict.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (10)
1. The flip LED chip is characterized by comprising a substrate, an epitaxial layer, a current blocking layer, a current expansion layer, an electrode layer, a Bragg reflection layer, a connection layer, a first insulating protection layer, a metal protection layer, a second insulating protection layer and a bonding pad layer which are sequentially laminated on the substrate;
the connecting layer comprises a plurality of P-type connecting layers and a plurality of N-type connecting layers with the same structure, the P-type connecting layers comprise a high-reflection metal layer, a protective metal layer and a current transmission layer which are sequentially laminated, the high-reflection metal layer is an Al layer or an Ag layer, and the protective metal layer is formed by laminating one or more of a Ti layer, a Pt layer, a Ni layer, a Cr layer and a Pb layer;
the current transmission layer comprises at least two transmission sublayers which are sequentially laminated, wherein each transmission sublayer consists of 3-5 groups of periodically laminated TiW layers and Au layers, the thickness ratio of the TiW layers in different transmission sublayers is 10% -40% of the thickness of the Au layers, and the thickness ratio of the TiW layers in different transmission sublayers along the growth direction of the chip is linearly increased;
the distance from the edge of the P-type connecting layer to the edge of the N-type connecting layer is 20-40 mu m.
2. The flip-chip light emitting diode chip of claim 1, wherein the epitaxial layer comprises an N-type semiconductor layer, an active light emitting layer and a P-type semiconductor layer sequentially stacked on the substrate, isolation grooves are formed around the N-type semiconductor layer, and the bragg reflection layer, the first insulating protection layer and the second insulating protection layer are all extended and covered on the isolation grooves.
3. The flip-chip light emitting diode chip of claim 2, wherein the current blocking layer is a plurality of SiO with a diameter of 20-50 μm 2 Discs or Al 2 O 3 And the discs are arranged on the P-type semiconductor layer.
4. The flip-chip light emitting diode chip of claim 2, wherein the current spreading layer covers and extends the current blocking layer onto the P-type semiconductor layer, and a distance from an edge of the current spreading layer to an edge of the P-type semiconductor layer is between 3 μm and 10 μm.
5. The flip-chip light emitting diode chip of claim 3, wherein the electrode layers comprise a plurality of P-type electrode layers and a plurality of N-type electrode layers, the P-type electrode layers and the N-type electrode layers are each a metal disk having a diameter of 10 μm-30 μm, and the P-type electrode layers are located on the current spreading layer and concentric with the current blocking layer; the distance from the edge of the P-type electrode layer to the edge of the current blocking layer is 5-15 mu m; the N-type electrode layer is positioned on the N-type semiconductor layer and is electrically connected with the N-type semiconductor layer, and the distance from the edge of the N-type electrode layer to the edge of the P-type semiconductor layer is 7-10 mu m.
6. The flip-chip light emitting diode chip of claim 1, wherein the bragg reflector layer is a periodically layered TiO of 20-40 groups 2 Layer and SiO 2 The Bragg reflection layer is provided with a plurality of first through holes, the connecting layer is connected with the electrode layer through the first through holes, and the distance from the edge of the first through holes to the edge of the electrode layer is 2-10 mu m.
7. The flip-chip led chip of claim 1, wherein said first and second insulating protective layers are both SiO 2 Layer, al 2 O 3 And the first insulating protection layer and the second insulating protection layer are respectively provided with a second through hole penetrating through the first insulating protection layer and the second insulating protection layer, the bonding pad layer is electrically connected with the connecting layer through the second through holes, and the distance from the edge of the second through holes to the edge of the connecting layer is 10-15 mu m.
8. The flip-chip light emitting diode chip of claim 1, wherein the pad layer is disposed on the second insulating protective layer and comprises a P-type pad layer and an N-type pad layer, and wherein a distance from an edge of the P-type pad layer to an edge of the N-type pad layer is between 200 μm and 300 μm.
9. The flip-chip light emitting diode chip of claim 8, wherein the metal protection layer comprises a P-type metal protection layer, an N-type metal protection layer and an anti-thimble layer, the P-type metal protection layer is disposed between the first insulating protection layer and the second insulating protection layer above the N-type connection layer on one side of the P-type pad layer, a projection width of the P-type metal protection layer on the substrate is greater than a projection width of the N-type connection layer on the substrate, and a projection edge distance from a projection edge of the P-type metal protection layer on the substrate to a projection edge of the N-type connection layer on the substrate is 5 μm-15 μm;
the N-type metal protection layer is arranged between the first insulating protection layer and the second insulating protection layer on the P-type connection layer at one side of the N-type bonding pad layer, the projection width of the N-type metal protection layer on the substrate is larger than that of the P-type connection layer on the substrate, and the distance from the projection edge of the N-type metal protection layer on the substrate to the projection edge of the P-type connection layer on the substrate is 5-15 mu m;
the thimble preventing layer is arranged between the first insulating protective layer and the second insulating protective layer at the center of the flip LED chip, and the thimble preventing layer is a disc with the diameter of 50-100 mu m.
10. A method of manufacturing a flip-chip light emitting diode chip as claimed in any one of claims 1 to 9, comprising:
providing a substrate;
depositing an epitaxial layer on the substrate, wherein the epitaxial layer comprises an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer;
preparing an isolation groove on the N-type semiconductor layer;
depositing a current blocking layer on the P-type semiconductor layer, wherein the current blocking layer extends to the N-type semiconductor layer and covers the isolation groove;
depositing a current spreading layer on the current blocking layer;
depositing an electrode layer on the current expansion layer and the N-type semiconductor layer, wherein the electrode layer comprises a P-type electrode layer positioned on the current expansion layer and an N-type electrode layer positioned on the N-type semiconductor layer;
depositing a Bragg reflection layer on the electrode layer;
depositing a connecting layer on the Bragg reflection layer, wherein the connecting layer comprises a P-type connecting layer electrically connected with the P-type electrode layer and an N-type connecting layer electrically connected with the N-type electrode layer;
depositing a first insulating protection layer on the connection layer;
depositing a metal protection layer on the first insulating protection layer;
depositing a second insulating protective layer on the metal protective layer;
and depositing a bonding pad layer on the second insulating protective layer, wherein the bonding pad layer comprises a P-type bonding pad electrically connected with the P-type connecting layer and an N-type bonding pad electrically connected with the N-type connecting layer.
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| CN117393680A (en) * | 2023-12-12 | 2024-01-12 | 江西兆驰半导体有限公司 | Flip light-emitting diode chip and preparation method thereof |
| CN117712245A (en) * | 2024-02-05 | 2024-03-15 | 江西兆驰半导体有限公司 | Flip LED chip and preparation method thereof |
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