CN113921676B

CN113921676B - Light emitting diode and light emitting module

Info

Publication number: CN113921676B
Application number: CN202111076849.3A
Authority: CN
Inventors: 朱秀山; 李燕
Original assignee: Xiamen Sanan Optoelectronics Technology Co Ltd
Current assignee: Xiamen Sanan Optoelectronics Technology Co Ltd
Priority date: 2021-09-14
Filing date: 2021-09-14
Publication date: 2023-06-20
Anticipated expiration: 2041-09-14
Also published as: CN113921676A; CN116885072A

Abstract

The invention provides a light emitting diode and a photoelectric module, wherein the light emitting diode comprises: an epitaxial structure including a first conductivity type semiconductor layer, a light emitting layer, and a second conductivity type semiconductor layer stacked in order; the transparent conductive layer is positioned on the second conductive type semiconductor layer and provided with a plurality of first through holes; the first insulating layer at least covers the edge area and the side wall of the epitaxial structure and is provided with a plurality of second through holes which are staggered with the first through holes; and a reflective electrode layer formed on the first insulating layer or the transparent conductive layer. Wherein, a second via hole nearest to the edge of the lower surface of the sidewall of the reflective electrode layer is located at a certain interval between the edge of the upper surface of the first insulating layer and the edge of the lower surface of the reflective electrode layer, and the interval is greater than 5 μm.

Description

Light emitting diode and light emitting module

Technical Field

The present invention relates to a light emitting diode, and more particularly to a light emitting diode and a light emitting module having the same.

Background

A light emitting diode (LED for short, english Light Emitting Diode) includes different light emitting materials and light emitting components, and is a solid semiconductor light emitting element. The LED display device has the advantages of low cost, low power consumption, high light efficiency, small volume, energy conservation, environmental protection, good photoelectric property and the like, and is widely applied to various scenes such as illumination, visible light communication, luminous display and the like.

Disclosure of Invention

To achieve at least one advantage and other advantages, an embodiment of the present invention provides a light emitting diode, including: an epitaxial structure including a first conductivity type semiconductor layer and a second conductivity type semiconductor layer stacked in order; a transparent conductive layer on the second conductive type semiconductor layer; the first insulating layer at least covers the edge area and the side wall of the epitaxial structure and is provided with a plurality of second through holes; and a reflective electrode layer formed on the transparent conductive layer or the first insulating layer; and the second through hole closest to the edge of the lower surface of the side wall of the reflecting electrode layer is positioned at a distance of more than or equal to 5 mu m and less than or equal to 50 mu m between the edge of the upper surface of the first insulating layer and the edge of the lower surface of the reflecting electrode layer.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

For a clearer description of embodiments of the invention or of the solutions of the prior art, the following description of the embodiments or of the drawings used in the prior art will be given for simplicity, it being obvious that the drawings in the following description are some embodiments of the invention, and that other drawings can be obtained according to these drawings, without the need for inventive effort, for a person skilled in the art; the positional relationships described in the drawings in the following description are based on the orientation of the elements shown in the drawings unless otherwise specified.

FIG. 1 is a schematic top view of a first embodiment of a light emitting diode according to the present invention;

FIG. 2 is a schematic cross-sectional view of the first embodiment of FIG. 1 taken along the X-X direction;

FIG. 3 is an enlarged schematic view of area A of FIG. 2;

FIG. 4 is a schematic cross-sectional view of a modified embodiment of the LED of FIG. 2;

FIG. 5 is a schematic top view of a second embodiment of the LED according to the present invention;

FIG. 6 is an enlarged schematic view of area D of FIG. 5;

FIG. 7 is an enlarged schematic view of area E of FIG. 5;

FIG. 8 is a schematic cross-sectional view of the LED of FIG. 5 taken along the Z-Z direction;

FIG. 9 is an enlarged schematic view of D1 in the region B' of FIG. 8;

FIG. 10 is an enlarged schematic view of region b4 of FIG. 9;

FIG. 11 is an enlarged schematic view of D2 in the region B' of FIG. 8;

FIG. 12 is an enlarged schematic view of D3 in the region B' of FIG. 8;

FIG. 13 is an enlarged schematic view of region b5 of FIG. 12;

FIG. 14 is an enlarged schematic view of D8 in the region B' of FIG. 8;

FIG. 15 is an enlarged schematic view of region b6 of FIG. 14;

FIG. 16 is an enlarged schematic view of D12, a7, a8 in the region B' of FIG. 8;

FIG. 17 is an enlarged schematic view of D14 in the region B' of FIG. 8;

FIG. 18 is a schematic cross-sectional view of a first variant embodiment of the LED of FIG. 8;

FIG. 19 is an enlarged schematic view of D5 in the region H' of FIG. 18;

FIG. 20 is an enlarged schematic view of D6 in the region H' of FIG. 18;

FIG. 21 is an enlarged schematic view of D14 in the region H' of FIG. 18;

FIG. 22 is a schematic cross-sectional view of a second variant embodiment of the LED of FIG. 8;

FIG. 23 is an enlarged schematic view of D10, a9 in region I' of FIG. 22;

FIG. 24 is an enlarged schematic view of D11, a9 in the J' region of FIG. 22;

FIG. 25 is a schematic top view of a third embodiment of a light emitting diode according to the present invention;

FIG. 26 is an enlarged schematic view of D4 in area F of FIG. 25;

FIG. 27 is an enlarged schematic view of D8 in region G of FIG. 25;

FIG. 28 is a schematic cross-sectional view of the LED of FIG. 25 taken along the Y-Y direction;

FIG. 29 is an enlarged schematic view of D1 in area B of FIG. 28;

FIG. 30 is an enlarged schematic view of region b1 of FIG. 29;

FIG. 31 is an enlarged schematic view of D2 in area B of FIG. 28;

FIG. 32 is an enlarged schematic view of D3 in area B of FIG. 28;

FIG. 33 is an enlarged schematic view of region b2 of FIG. 32;

FIG. 34 is an enlarged schematic view of D4 in area B of FIG. 28;

FIG. 35 is an enlarged schematic view of D4 in area C of FIG. 28;

FIG. 36 is an enlarged schematic view of D7 in area B of FIG. 28;

FIG. 37 is an enlarged schematic view of D8 in area B of FIG. 28;

FIG. 38 is an enlarged schematic view of region b3 of FIG. 37;

FIG. 39 is an enlarged schematic view of D9 in area B of FIG. 28;

FIG. 40 is an enlarged schematic view of D12, a7, a8 in area B of FIG. 28;

FIG. 41 is an enlarged schematic view of D14 in area B of FIG. 28;

FIG. 42 is a schematic cross-sectional view of a first variant embodiment of the LED of FIG. 28;

FIG. 43 is an enlarged schematic view of D5 in area H of FIG. 42;

FIG. 44 is an enlarged schematic view of D6 in region H of FIG. 42;

FIG. 45 is an enlarged schematic view of D14 in region H of FIG. 42;

FIG. 46 is a schematic cross-sectional view of a second variant embodiment of the LED of FIG. 28;

FIG. 47 is an enlarged schematic view of D10, a9 in region I of FIG. 46;

FIG. 48 is an enlarged schematic view of D11, a9 in region J of FIG. 46;

FIG. 49 is a schematic cross-sectional view of a third variant embodiment of the LED of FIG. 28;

FIG. 50 is an enlarged schematic view of region K of FIG. 49;

FIG. 51 is a schematic view showing the distribution of the first and second through holes in FIG. 50;

FIGS. 52 to 57 are schematic cross-sectional views of the LED of FIG. 25 taken along the different directions of FIG. 52;

FIGS. 58 and 59 are schematic cross-sectional views of various embodiments of solder layers in a light emitting diode of the present invention; and

FIG. 60 is a schematic diagram of a partial structure of a light emitting diode according to the present invention in an actual manufacturing process.

Reference numerals:

1-light emitting diode 10-substrate 20-epitaxial structure

21-first conductivity type semiconductor layer 22-light emitting layer 23-second conductivity type semiconductor layer

210-first electrode 211-first connection electrode 212-first pad electrode

230-second electrode 231-second connection electrode 232-second pad electrode

233-conductive via 30-insulating layer 31-conductive opening

32-first insulating layer 320-second via 33-second insulating layer

40-transparent conductive layer 41-first via 50-reflective electrode layer

60-electrode coating/metal extension layer 70-third insulating layer 71-first opening

72-second openings 321, 331-side 214, 234-solder layer

M, N edge region

D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14-spacing

a1, a2, a3, a4, a5, a6, a7, a8, a 9-internal angle/inclination angle

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention; the technical features designed in the different embodiments of the invention described below can be combined with each other as long as they do not conflict with each other; all other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the protection of the invention.

In the description of the present invention, it should be noted that all terms used in the present invention (including technical terms and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs and are not to be construed as limiting the present invention; it will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Referring to fig. 1 and 2, fig. 1 is a schematic top view of a first embodiment of a light emitting diode according to the present invention, and fig. 2 is a schematic cross-sectional view of the first embodiment of fig. 1 taken along the X-X direction. To achieve at least one of the advantages and other advantages, an embodiment of the present invention provides a light emitting diode 1 (or light emitting diode chip 1), which may include at least a substrate 10, an epitaxial structure 20, and an insulating layer 30. The epitaxial structure 20 includes a first conductivity type semiconductor layer 21, a light emitting layer 22 (or active layer 22, active layer 22), and a second conductivity type semiconductor layer 23 sequentially stacked on the substrate 10 in a stacking direction. The insulating layer 30 is located on the second conductive type semiconductor layer 23.

The substrate 10 may be an insulating substrate, and preferably may be made of a transparent material or a translucent material or a non-transparent material. In the illustrated embodiment, the substrate 10 is sapphire (Al ₂ O ₃ ) A substrate. In some embodiments, substrate 10 may be a patterned sapphire substrate, but is not limited thereto. The substrate 10 may also be made of a conductive or semiconductor material. For example, the substrate 10 may be silicon carbide (SiC), silicon (Si), magnesium aluminum oxide (MgAl) ₂ O ₄ ) Magnesium oxide (MgO), lithium aluminum oxide (LiAlO) ₂ ) Aluminum gallium oxide (LiGaO) ₂ ) And at least one of gallium nitride (GaN). In some embodiments, the substrate 10 may be thinned or removed to form a thin film LED chip.

In some embodiments, the upper surface of the substrate 10 may have a patterned structure (not shown) that may improve the external light extraction efficiency and crystallinity of the epitaxial structure 20. Alternatively, the upper surface patterned structure of the substrate 10 may be formed in various shapes, such as a platform, cone, pyramid,Hexagonal pyramid, conical-like, triangular pyramid-like or hexagonal pyramid-like, etc. In addition, the upper surface patterning structure of the substrate 10 may be selectively formed at the respective regions or may be omitted. The patterned structure may be the same material as the substrate 10 or may be different from the substrate 10. For example, the patterned structure may be made of a material having a refractive index lower than that of the substrate 10 to facilitate light extraction, and may be SiO ₂ Etc.

Further, the upper and lower positions are defined by the positions of the substrate 10 in the present specification. Assume that the direction approaching the substrate 10 is downward and the direction away from the substrate 10 is upward. The setting of the vertical position in the present specification is limited to the explanation of the positional relationship of the respective components in the illustrated embodiment, and does not represent an instruction or suggestion that it is necessary to have a specific orientation.

The epitaxial structure 20 may be formed on the substrate 10 by Metal Organic Chemical Vapor Deposition (MOCVD), molecular Beam Epitaxy (MBE), hydride vapor deposition (HVPE), physical Vapor Deposition (PVD), or ion plating. Specifically, the substrate 10 has opposite upper and lower surfaces, and the epitaxial structure 20 is formed on the upper surface of the substrate 10. Wherein the first conductive type semiconductor layer 21 may be grown from the upper surface of the substrate 10, and the light emitting layer 22 (or active layer 22, active layer 22) and the second conductive type semiconductor layer 23 are sequentially grown on the upper surface of the first conductive type semiconductor layer 21 in a stacked manner. In other embodiments, the epitaxial structure 20 may also be formed on the substrate 10 by a bonding layer, preferably of a light transmissive material.

The epitaxial structure 20 may provide light of a particular center emission wavelength, such as blue, green, or red, or violet, or ultraviolet light. The present embodiment is described with respect to the epitaxial structure 20 providing blue light. In the illustrated embodiment, the first conductivity type semiconductor layer 21 in the epitaxial structure 20 is an N-type semiconductor layer, and electrons can be supplied to the light emitting layer 22 by a power supply. In some embodiments, the N-type semiconductor layer in the first conductive type semiconductor layer 21 includes an N-type doped nitride layer. The N-doped nitride layer may include one or more N-type impurities of a group IV element. The N-type impurity may be one of Si, ge, sn, or a combination thereof.

In some embodiments, the light emitting layer 22 (or active layer 22, active layer 22) may be a multiple quantum well (multiple quantum wells, abbreviated as MQWs) structure that is alternately stacked by quantum well layers and quantum barrier layers. The light emitting layer 22 may be a single quantum well structure or a multiple quantum well structure. The quantum barrier layer may be a GaN layer or an AlGaN layer. In some embodiments, the light emitting layer 22 may include a multiple quantum well structure of GaN/AlGaN, inAlGaN/InAlGaN or InGaN/AlGaN. To increase the light emitting efficiency of the light emitting layer 22, this may be achieved by varying the depth of the quantum wells, the number of layers, thickness and/or other characteristics of the pairs of quantum wells and quantum barriers in the light emitting layer 22.

In the illustrated embodiment, the second conductivity type semiconductor layer 23 in the epitaxial structure 20 is a P-type semiconductor layer, and holes can be provided to the light emitting layer 22 under the power supply. In some embodiments, the P-type semiconductor layer in the second conductive type semiconductor layer 23 includes a P-type doped nitride layer. The P-doped nitride layer may include one or more P-type impurities of a group II element. The P-type impurity may Be one of Mg, zn, be, or a combination thereof. The second conductivity type semiconductor layer 23 may have a single-layer structure or a multi-layer structure having different compositions. The arrangement of the epitaxial structure 20 is not limited thereto, and other types of epitaxial structures 20 may be selected according to practical requirements.

In some embodiments, a buffer layer (not shown) may be provided between the substrate 10 and the epitaxial structure 20 in the light emitting diode 1 to mitigate lattice mismatch between the substrate 10 and the first conductivity type semiconductor layer 21. In some embodiments, the buffer layer may include an unintentionally doped GaN layer (u-GaN for short) or an unintentionally doped AlGaN layer (u-AlGaN for short).

The buffer layer may be a single layer or multiple layers. The buffer layer may be formed by metal organic chemical vapor deposition, molecular beam epitaxy, or physical vapor deposition (Physical Vapour Deposition, abbreviated as PVD). Wherein, the deposition of the physical vapor phase can comprise sputtering (sputtering), such as reactive sputtering, or evaporation; such as electron beam evaporation or thermal evaporation. In one embodiment, the buffer layer may include an aluminum nitride (AlN) buffer layer formed by a sputtering method on the substrate 10 having a patterned structural surface. Sputtering can form a dense buffer layer with high uniformity, so that an aluminum nitride buffer layer can be deposited on the patterned structured surface of the substrate 10.

Further, the epitaxial structure 20 has a plurality of mesas (mesa) which allow a portion of the second conductivity type semiconductor layer 23 and the light emitting layer 22 to be removed, exposing a portion of the upper surface of the first conductivity type semiconductor layer 21. The mesa may be used as an electrode mesa. The electrode mesas may be located inside the epitaxial structure 20, or at an edge region of the epitaxial structure 20, or both inside and at the edge region of the epitaxial structure 20. Further, the total area of the mesa surfaces is smaller than the area of the first conductivity type semiconductor layer 21, and the mesa surfaces may expose a portion of the upper surface of the first conductivity type semiconductor layer 21 to realize electrode connection of the first conductivity type semiconductor layer 21. In addition, the mesa arrangement may be such that the side surfaces or sidewalls of the first conductive type semiconductor layer 21 have an inclination angle when formed.

Referring to fig. 3 in conjunction with fig. 1 and 2, fig. 3 is an enlarged schematic view of the area a in fig. 2. An insulating layer 30 is located on the second conductivity type semiconductor layer 23 of the epitaxial structure 20 and covers the sidewalls of the epitaxial structure 20 and the sidewalls of the electrode mesa. The insulating layer 30 is provided with conductive openings 31 at positions of the electrode mesas, exposing a portion of the upper surface of the first conductive type semiconductor layer 21, and one ends of the conductive openings 31 are connected to the first conductive type semiconductor layer 21. Specifically, the first conductive type semiconductor layer 21 is electrically connected through the exposed upper surface at the conductive opening 31. The conductive opening 31 has a certain distance D1 from the edge of the upper surface of the second conductive type semiconductor layer 23. The arrangement of the distance D1 can realize better insulation protection and anti-creeping performance.

In some embodiments, a distance D1 between an edge of the conductive opening 31 provided in the insulating layer 30 and an edge of the upper surface of the second conductive type semiconductor layer 23 is 1 μm or more and 12 μm or less. In some embodiments, the edge of the conductive opening 31 provided in the insulating layer 30 and the edge of the upper surface of the second conductive type semiconductor layer 23 have a certain distance D1 therebetween of more than 2 μm. In general, the thickness of the insulating layer 30 at the sidewall of the epitaxial structure 20 is thinner, and in this embodiment, a film platform is formed on the insulating layer 30 of the light emitting diode 1 near the upper surface of the first conductivity type semiconductor layer 21 after etching treatment. The spacing D1 of the insulating layer 30 may enable the insulating layer 30 having a sufficient thickness between the edge of the conductive opening 31 at the upper surface of the first conductivity type semiconductor layer 21 and the sidewall of the epitaxial structure 20 to achieve sufficient insulation protection for the epitaxial structure 20, so that the light emitting diode 1 has better insulation protection, water vapor resistance and anti-leakage performance. If the upper surface of the first conductivity type semiconductor layer 21 has no insulating layer film platform, the thickness of the insulating layer at the side wall of the epitaxial structure 20 is obviously reduced due to the thinner side wall and the lateral corrosion of the BOE during the deposition of the insulating layer, and meanwhile, the subsequent metal layer coverage will be uneven, so that the risk of chip leakage and package leakage is increased, and the water vapor resistance is reduced.

The upper surface of the insulating layer 30 may be provided with a first electrode 210 and a second electrode 230. In the illustrated example, the first electrode 210 may be an N electrode and the second electrode 230 may be a P electrode. The first electrode 210 and the second electrode 230 have a certain interval therebetween, so that the P electrode and the N electrode in the light emitting diode 1 are separated from each other. The first electrode 210 may be connected to the first conductive type semiconductor layer 21 through the conductive opening 31. The second electrode 230 may be partially connected to the second conductive type semiconductor layer 23.

The photoelectric performance of the light emitting diode 1 and the contact area of the N electrode with the N-type semiconductor layer (the first conductivity type semiconductor layer 21 in the illustrated example) are related to the area of the conductive opening 31. The contact area of the N electrode affects the voltage of the led 1, and the area of the N electrode can be adjusted according to the driving current density in practical product design. Depending on the design purpose or use of the product, the optoelectronic performance of the led 1 is not affected by the shape of the conductive openings 31, and is related to the size and number of the conductive openings 31. Thus, the conductive openings 31 may have any regular shape, such as circular or square. The conductive openings 31 are through holes penetrating the insulating layer 30 and are connected to the first conductive type semiconductor layer 21. The diameter of each conductive opening 31 is preferably greater than 8 μm. If the diameter of the conductive opening 31 is too small, a current crowding effect is easily caused, resulting in a voltage rise. In some embodiments, the diameter of each conductive aperture 31 may be 12 μm. The total area of the conductive openings 31 is preferably greater than 0.2% of the total area of the epitaxial structure 20, so that the contact area between the N electrode and the N-type semiconductor layer can be ensured, and the voltage can be reduced, so that the light emitting diode 1 has good photo-electric performance.

In some embodiments, the insulating layer 30 may be a reflective insulating layer, which is located on the second conductivity type semiconductor layer 23 of the epitaxial structure 20 and covers the sidewall of the epitaxial structure 20, and may be used to reflect light and block different electrodes, such as P-electrode and N-electrode, in the light emitting diode 1. The first insulating layer 32 may comprise SiO ₂ 、SiN、SiO _x N _y 、TiO ₂ 、Si ₃ N ₄ 、 Al ₂ O ₃ 、TiN、AlN、ZrO ₂ 、TiAlN、TiSiN、HfO ₂ 、TaO ₂ And MgF ₂ At least one of them. In the illustrated embodiment, the material of the insulating layer 30 may include SiO ₂ 。

Referring to fig. 4 in conjunction with fig. 1, fig. 4 is a schematic cross-sectional view of a modified embodiment of the led shown in fig. 2. In some embodiments, the insulating layer 30 may include a first insulating layer 32 and a second insulating layer 33. The first insulating layer 32 is disposed on the second conductivity type semiconductor layer 23 of the epitaxial structure 20 and covers the sidewall of the epitaxial structure 20, which may be SiO ₂ 、SiN、Al ₂ O ₃ Etc., the preparation method may include PECVD (plasma deposition), ALD (atomic layer deposition), etc. In the illustrated embodiment, the material of the first insulating layer 32 includes SiO ₂ . The second insulating layer 33 is located on the first insulating layer 32, and covers the upper surface and the sidewalls of the first insulating layer 32. The second insulating layer 33 may be made of SiO ₂ 、SiN、 SiO _x N _y 、TiO ₂ 、Si ₃ N ₄ 、Al ₂ O ₃ 、TiN、AlN、ZrO ₂ 、TiAlN、TiSiN、HfO ₂ 、TaO ₂ And MgF ₂ At least one of them. The conductive openings 31 penetrate through the sidewalls of the second insulating layer 33 and the first insulating layer 32 and are connected to the first conductive type semiconductor layer 21. In order to provide the insulating layer 30 with better insulation protection and anti-creeping properties, in some embodiments, the thickness of the first insulating layer 32 and the second insulating layer 33 is preferably greater than or equal to 800nm.

In some embodiments, the refractive index of the first insulating layer 32 is greater than 1.4. The first insulating layer 32 may be SiO ₂ 、SiN、 Al ₂ O ₃ One or a combination thereof. The thickness of the first insulating layer 32 is between 300nm and 1500 nm. The second insulating layer 33 is an insulating reflective layer, and may have a multilayer film structure in which dielectric films having different high refractive indices and dielectric films having different low refractive indices are alternately stacked. Wherein the material of the dielectric film with high refractive index can be TiO ₂ 、NB ₂ O ₅ 、TA ₂ O ₅ 、HfO ₂ 、ZrO ₂ Etc.; the material of the low-refraction dielectric film can be SiO ₂ 、MgF ₂ 、Al ₂ O ₅ SiON, etc. By this arrangement, the second insulating layer 33 has better reflection performance, and the light emitting diode 1 has better photoelectric performance.

The second insulating layer 33 needs to ensure good insulating properties to block different conductive materials, such as P-metal and N-metal, in the led 1. In some embodiments, the second insulating layer 33 may have a single-layer structure or a multi-layer structure, and the thickness thereof is between 500nm and 1500 nm. In other embodiments, the second insulating layer 33 may be a bragg reflector (DBR), specifically a multilayer film structure formed by alternately stacking different dielectric films with high refractive index and different dielectric films with low refractive index, and the thickness of the multilayer film structure is between 3000nm and 5000 nm.

Referring to fig. 1 to 4, please refer to fig. 8 to 24 in conjunction with fig. 5 to 7. Fig. 5 is a schematic top view of a second embodiment of the led according to the present invention, and fig. 6 and fig. 7 are respectively enlarged schematic views of a region D, E in fig. 5. Fig. 8 to 17 are schematic cross-sectional views of the led shown in fig. 5 taken along the Z-Z direction and related enlarged schematic views. Fig. 18 to 21 and fig. 22 to 24 are schematic cross-sectional views and enlarged schematic views of different variants of the led shown in fig. 8, respectively.

Referring to fig. 8 in conjunction with fig. 5, in some embodiments, the light emitting diode 1 may further include: a transparent conductive layer 40 on the second conductive type semiconductor layer 23 of the epitaxial structure 20; the first insulating layer 32 covers at least the edge region M and the sidewall of the epitaxial structure 20, and the sidewall of the electrode mesa; the reflective electrode layer 50 is formed on the transparent conductive layer 40, and the electrode coating layer 60 is formed on the reflective electrode layer 50 and covers a portion of the upper surface of the first insulating layer 32; a second insulating layer 33 is positioned on the first insulating layer 32 and covers the first insulating layer 32, the reflective electrode layer 50, and the electrode coating layer 60; a third insulating layer 70 is positioned on the second insulating layer 33 and covers the second insulating layer 33; at least one first connection electrode 211, a first pad electrode 212, and a second pad electrode 232, the first pad electrode 212 and the second pad electrode 232 being located above the third insulating layer 70 and partially penetrating the third insulating layer 70, the first connection electrode 211 being disposed between the second insulating layer 33 and the third insulating layer 70 and electrically connected to the first pad electrode 212. The third insulating layer 70 may be made of SiO ₂ 、SiN、Al ₂ O ₃ And Bragg reflection layers (DBR), etc., which may be prepared by plasma deposition, atomic layer deposition, sputtering, etc.

Further, the light emitting diode 1 may further include at least one second connection electrode 231 disposed between the third insulating layer 70 and the second insulating layer 33. One end (upper surface in the drawing) of the second connection electrode 231 is connected to the second pad electrode 232. The second connection electrode 231 has a plurality of conductive vias 233 at an end thereof remote from the second pad electrode 232. The conductive vias 233 penetrate the second insulating layer 33 and are connected to the electrode coating layer 60. In this case, the second pad electrode 232 is electrically connected to the electrode coating layer 60 through the second connection electrode 231 after passing through the third insulating layer 70. At this time, the first electrode 210 may be formed of the first connection electrode 211 and the first pad electrode 212, and the second electrode 230 may be formed of the second pad electrode 232 and the second connection electrode 231. The first electrode 210 may be an N electrode, and the second electrode 230 may be a P electrode.

In some embodiments, as can be understood with reference to fig. 8 in comparison with fig. 4, the light emitting diode 1 may not be provided with the second connection electrode 231. At this time, the third insulating layer 70 is positioned on the second insulating layer 33 and covers the second insulating layer 33 and the electrode coating layer 60. The second pad electrode 232 may be electrically connected to the electrode coating layer 60 after partially passing through the third insulating layer 70 and the second insulating layer 33. The first electrode 210 may be composed of the first connection electrode 211 and the first pad electrode 212, and the second electrode 230 may be composed of only the second pad electrode 232. The first electrode 210 may be an N electrode, and the second electrode 230 may be a P electrode.

The second connection electrode 231 has at least one conductive via 233. In the embodiment shown in fig. 5, 25, 55, 57, three conductive vias 233 are provided in the second connection electrode 231. The upper surface of the second connection electrode 231 is connected to the second pad electrode 232, and the lower surface of the second connection electrode 231 is electrically connected to the electrode coating layer 60 through the three conductive vias 233. Thereby realizing the electrical connection of the P electrode. The number of the conductive vias 233 on the second connection electrode 231 is not limited thereto. In the design process of different products, the number of the conductive vias 233 on the second connection electrode 231 may be two or more than four according to the requirements and the arrangement of the adjacent structures of the second connection electrode 231.

As will be understood with reference to fig. 8, in some embodiments, the first insulating layer 32 covers the edge region M and the sidewalls of the epitaxial structure 20, and the sidewalls of the electrode mesa, wherein the edge region M of the epitaxial structure 20 includes the edge region N of the second conductivity type semiconductor layer 23, and a certain space or gap is formed between the transparent conductive layer 40 and the first insulating layer 32, and the reflective electrode layer 50 is directly formed on the transparent conductive layer 40 and covers the gap between the transparent conductive layer 40 and the first insulating layer 32. The arrangement is such that the reflective electrode layer 50 covering the transparent conductive layer 40 is in contact with the epitaxial structure 20 at the edge thereof, wherein the reflective electrode layer 50 is in contact with a portion of the upper surface of the second conductive type semiconductor layer 23, and the transparent conductive layer 40 is covered by the reflective electrode layer 50 except for the portion in contact with the second conductive type semiconductor layer 23. The distance of the transparent conductive layer 40 from the edge of the epitaxial structure 20 (also known as the edge of the upper surface of the second conductivity type semiconductor layer 23) is greater than the distance of the reflective electrode layer 50 from the edge of the epitaxial structure 20 (also known as the edge of the upper surface of the second conductivity type semiconductor layer 23). The reflective electrode layer 50 includes at least Ag, and in view of the fact that the adhesion between Ag and the second conductive type semiconductor layer 23 in the reflective electrode layer 50 is higher than that between Ag and the transparent conductive layer 40, the reflective electrode layer 50 may be partially contacted with the second conductive type semiconductor layer 23 while completely covering the transparent conductive layer 40 to increase the adhesion of the reflective electrode layer 50, which may prevent the reflective electrode layer 50 from peeling or peeling off (peeling) at the edge.

There may be no gap between the transparent conductive layer 40 and the first insulating layer 32, for example, in some embodiments, the reflective electrode layer 50 may be disposed under the Ag reflective layer as an adhesion layer with a thin metal layer of Ti, cr, etc. The first insulating layer 32 may partially cover the edges of the transparent conductive layer 40 according to different processes and design requirements.

In the illustrated embodiment, the first connection electrode 211 and the first pad electrode 212 constitute a first electrode 210. The second pad electrode 232 and the second connection electrode 231 form a second electrode 230. The first electrode 210 is an N electrode, and the second electrode 230 is a P electrode. The first connection electrode 211 fills the conductive opening 31, thereby electrically connecting the first conductive type semiconductor layer 21, the first connection electrode 211, and the first pad electrode 212. The second pad electrode 232 is electrically connected to the electrode coating layer 60 through the second connection electrode 231 and the conductive vias 233.

The conductive openings 31 may be distributed in different areas of the led 1, such as area D, E in fig. 5. The region D is an outer peripheral region of the light emitting diode 1, and the region E is an inner region of the light emitting diode 1. When the conductive opening 31 is located in the outer peripheral region (e.g., region D in fig. 5) of the light emitting diode 1, the distance D1 between it and the edge of the upper surface of the second conductivity type semiconductor layer 23 and the distribution relationship with the transparent conductive layer 40, the reflective electrode layer 50 and the electrode coating layer 60 are as shown in fig. 6. When the conductive openings 31 are located in the inner region (e.g., region E in fig. 5) of the light emitting diode 1, the distribution of the distance D1 between them and the edge of the upper surface of the second conductivity type semiconductor layer 23 is as shown in fig. 7.

Specifically, the spacing D1 between the edge of the conductive opening 31 and the edge of the upper surface of the second conductivity type semiconductor layer 23 is preferably 1 μm or more. In some embodiments, the distance D1 between the edge of the conductive opening 31 and the edge of the upper surface of the second conductive type semiconductor layer 23 is 2 μm or more, and may be 2 to 12 μm or 1 to 8 μm, for example. In the design of the light emitting diode 1, the insulating layer 30 is etched to form a film mesa on the upper surface of the insulating layer adjacent to the first conductivity type semiconductor layer 21. The spacing D1 of the insulating layer 30 may enable the insulating layer 30 having a sufficient thickness between the edge of the conductive opening 31 on the upper surface of the first conductivity type semiconductor layer 21 and the sidewall of the epitaxial structure 20 to achieve sufficient insulation protection for the epitaxial structure 20, so that the light emitting diode 1 has better insulation protection, water vapor resistance and anti-leakage performance. If the upper surface of the first conductivity type semiconductor layer 21 has no insulating layer film platform, the thickness of the insulating layer at the side wall of the epitaxial structure is obviously reduced due to the thinner side wall and the lateral corrosion of the BOE during the deposition of the insulating layer, and meanwhile, the subsequent metal layer coverage is uneven, so that the risks of chip leakage and package leakage are increased, and the water vapor resistance is weakened.

Referring to fig. 9 in conjunction with fig. 6 and 7, in the example of fig. 8, the conductive opening 31 penetrates the first insulating layer 32 and the second insulating layer 33, so that the connection between the first insulating layer 32 and the second insulating layer 33 and the conductive opening 31 forms an inclined side.

In some embodiments, the conductive aperture 31 has an inclined side surface that is inclined at an angle of no greater than (or less than or equal to) 50 °. As shown in fig. 9 and 10, in the led 1, the connection between the first insulating layer 32 and the conductive opening 31 has an inclined side 321, and an internal angle a1 formed by the side 321 is not greater than (or equal to) 50 °. The connection between the second insulating layer 33 and the conductive opening 31 has an inclined side 331, and an internal angle a2 formed by the side 331 is not greater than (or equal to) 50 °. In this way, the first insulating layer 32 and the second insulating layer 33 in the region of the conductive opening 31 can be ensured to have sufficient thickness after etching, so that the epitaxial structure 20 has sufficient insulation protection and anti-leakage performance. In some embodiments, the inner angle a1 formed by the inclined side surface of the first insulating layer 32 may be 30 ° or less. The arrangement and limitation of the inner corners of the first insulating layer 32 and the second insulating layer 33 are beneficial to the cladding and morphology of different structural layers (such as a metal layer, a dielectric layer and the like) in the subsequent process, so that the overall photoelectric performance of the light emitting diode 1 is improved. If the inner angles of the first insulating layer 32 and the second insulating layer 33 are excessively large, there is a risk that the metal layer and the third insulating layer 70 are broken while being covered on the inclined surface.

The transparent conductive layer 40 facilitates current spreading or diffusion, and can prevent current from being concentrated in one or more regions of the second conductive type semiconductor layer 23, thereby effectively uniformly distributing current in the second conductive type semiconductor layer 23. The transparent conductive layer 40 may include at least one of Indium Tin Oxide (ITO), zinc-doped indium tin oxide (ZITO), zinc-indium oxide (ZIO), gallium-indium oxide (GIO), zinc-tin oxide (ZTO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO). The transparent conductive layer 40 may be an ITO (indium tin oxide semiconductor transparent conductive film) transparent conductive layer formed by vapor deposition or sputtering process, or may be made of other materials, such as ZnO, graphene, etc.

In addition, in some embodiments, the method may further include a step of forming a patterned roughness structure on the surface of the transparent conductive layer 40, where the patterned roughness structure may reduce the amount of light absorbed by the transparent conductive layer 40, so as to further improve the light extraction efficiency of the transparent conductive layer 40. The thickness of the transparent conductive layer 40 may be 5 to 150nm. The thickness of the transparent conductive layer 40 may have various alternative embodiments according to the application scenario of the product and the requirements of the design. In some embodiments, the thickness of the transparent conductive layer 40 is 10-60 nm, and the forward voltage of the LED chip can reach a more stable state in this range, and the light absorption effect of the transparent conductive layer 40 is lower. When the thickness of the transparent conductive layer 40 is higher than 60nm, the light absorption effect thereof is significantly increased, thereby affecting the luminous efficiency of the LED chip. In some embodiments, the thickness of the transparent conductive layer 40 is 20-30 nm, and the voltage and the brightness of the device can be better considered. In some embodiments, the transparent conductive layer 40 has a thickness of 40-50 nm, at which time the forward voltage of the LED device is lower.

Referring to fig. 11 in conjunction with fig. 8, in some embodiments, the transparent conductive layer 40 may be disposed to have a certain distance D2 from an edge of the upper surface of the second conductive type semiconductor layer 23. In other words, the transparent conductive layer 40 covers a part of the second conductivity type semiconductor layer 23 as a whole at this time. This arrangement reduces the risk of leakage (also referred to as reverse leakage; abbreviated IR) and electrostatic discharge (ESD) anomalies in the light-emitting diode 1. In the illustrated embodiment, indium Tin Oxide (ITO) may be included in transparent conductive layer 40. The distance D2 between the edge of the upper surface of the transparent conductive layer 40 and the edge of the upper surface of the second conductive type semiconductor layer 23 is greater than 2 μm.

As shown in fig. 11, in some embodiments, a distance D2 between an edge of the upper surface of the transparent conductive layer 40 and an edge of the upper surface of the second conductive type semiconductor layer 23 may be 10 μm or more and 16 μm or less. By this arrangement, the area of the transparent conductive layer 40 can be increased as much as possible while ensuring that the reflective electrode layer 50 is in contact with the second conductive type semiconductor layer 23, the P-plane ohmic contact can be increased, and the voltage can be reduced, thereby reducing the risk of occurrence of electric leakage and abnormal electrostatic discharge of the light emitting diode 1.

Referring to fig. 12 in conjunction with fig. 8 or fig. 32 in conjunction with fig. 28, in some embodiments, the transparent conductive layer 40 may be disposed to have a certain distance D3 from the edge where the first connection electrode 211 and the first conductive type semiconductor layer 21 are connected. With this arrangement, the light emitting diode 1 can be prevented from generating leakage (IR) and electrostatic discharge (ESD) abnormality. As shown in fig. 12 and 32, the first connection electrode 211 and the first conductive type semiconductor layer 21 are connected by the conductive opening 31, and in this example, a distance D3 between an end point or an edge of the upper surface of the transparent conductive layer 40 and an edge of the conductive opening 31 is 4 μm or more, preferably 6 μm or more. When the distance D3 is too small, the distance between the P electrode and the N electrode in the light emitting diode 1 is relatively short, and leakage easily occurs.

In some embodiments, as shown in fig. 12 and 32, a distance D3 between an end point or an edge of the upper surface of the transparent conductive layer 40 and an edge of the conductive opening 31 is 4 μm or more and 10 μm or less. The distance D3 between the end point or edge of the upper surface of the transparent conductive layer 40 and the edge of the conductive opening 31 includes a distance of 2 μm or more between the conductive opening 31 and the edge of the upper surface of the second conductive type semiconductor layer 23, and a distance of 1 μm or more between the opening of the second insulating layer 33 (where it is connected to the conductive opening 31) and the edge of the upper surface of the second conductive type semiconductor layer 23. By setting in this way, a certain distance between the transparent conductive layer 40 and the mesa on the epitaxial structure 20 can be ensured, and the occurrence of electric leakage and ESD abnormality of the light emitting diode 1 can be prevented. Meanwhile, a certain distance between the second insulating layer 33 and the table top on the epitaxial structure 20 can be ensured, so that the second insulating layer 33 with enough thickness is etched on the side wall of the epitaxial structure 20, and the light emitting diode 1 is ensured to have better insulation protection and anti-leakage performance.

The reflective electrode layer 50 may comprise a metal reflective layer, ensuring particularly good optoelectronic properties of the light emitting diode 1. In some embodiments, the reflective electrode layer 50 may include a metal reflective layer and at least one diffusion barrier layer stacked sequentially from bottom to top. The metal reflective layer may include at least one of Ag and Al. The diffusion barrier layer may be one of Ni, ti, W, pt or an alloy of any combination thereof or a stack of any combination thereof. The total thickness of the stack of diffusion barrier layers is greater than 200nm.

In the illustrated embodiment, the reflective electrode layer 50 comprises a highly reflective metal layer, which may include Ag or Al. In some embodiments, the reflective electrode layer 50 may be stacked from Ag, tiWTi, niTiW. Wherein, ag can be used as a metal reflecting layer, and TiWTi and NiTiW can be used as diffusion barrier layers to prevent diffusion of the metal reflecting layer. In other words, at this time, the arrangement of the reflective electrode layer 50 structure has an effect of coating Ag from the self. In some embodiments, the reflective electrode layer 50 is at least partially in contact with the transparent conductive layer 40. In some embodiments, the bottommost layer of the reflective electrode layer 50 may comprise Ti, cr as an adhesion layer between the reflective electrode layer 50 and the transparent conductive layer 40 to enhance adhesion between the reflective electrode layer 50 and the transparent conductive layer 40. At this time, the reflective electrode layer 50 is formed by stacking Ti or Cr, ag, tiWTi. For example, the bottom layer of the reflective electrode layer 50 contains Ti, and the top of the bottom layer is formed by stacking Ag and TiWTi.

In some embodiments, the reflective electrode layer 50 may be disposed in contact with the first insulating layer 32. At this time, the first layer of the reflective electrode layer 50 contacting the first insulating layer 32 is Cr, ti, or a combination thereof to enhance the adhesion of the reflective electrode layer 50 to the first insulating layer 32. In some embodiments, as shown in fig. 13, the reflectivity of the reflective electrode layer 50 is greater than or equal to 93%, the internal angle a3 formed by the sidewall of the reflective electrode layer 50 and the lower surface thereof is not greater than (or equal to) 30 °, the reflectivity of the electrode coating layer 60 is not greater than or equal to 60%, and the internal angle a4 formed by the sidewall of the electrode coating layer 60 and the lower surface thereof is not greater than (or equal to) 60 °.

Referring again to fig. 8 and 12, during the process, an electrode coating layer 60 is formed on the reflective electrode layer 50 and covers a portion of the upper surface of the first insulating layer 32. The projected area of the electrode coating 60 on the epitaxial structure 20 is outside the reflective electrode layer 50. At this time, the electrode coating layer 60 may cover the upper surface and a portion of the sidewall of the reflective electrode layer 50, and may cover Ag in the reflective electrode layer 50. The electrode coating layer 60 may be a metal protection layer and covers the reflective electrode layer 50 to protect Ag or Al in the reflective electrode layer 50 from migration and diffusion of Ag or Al.

In other embodiments, for example, when the light emitting diode 1 is a low current product element, the electrode coating 60 may not be provided. Depending on the use scenario or actual requirements, the electrode coating 60 may be a complete coating of the reflective electrode layer 50, as shown in fig. 8. Alternatively, the electrode coating layer 60 may be partially covering the reflective electrode layer 50, as shown in fig. 18. At this time, the projection of the electrode coating layer 60 onto the epitaxial structure 20 is located within the reflective electrode layer 50.

In some embodiments, as shown in fig. 18 and 19, and fig. 42 and 43, the electrode coating layer 60 is a metal extension layer 60 having a current conducting effect, whereby an edge of the lower surface of the electrode coating layer 60 has a certain distance D5 from an edge of the lower surface of the reflective electrode layer 50, and the total area of the electrode coating layer 60 is smaller than the total area of the reflective electrode layer 50. It is understood that the projection of the electrode cladding layer 60 onto the epitaxial structure 20 is within the reflective electrode layer 50. At this time, the electrode coating layer 60 has a current spreading function, and especially for a high-current product element, the overall brightness of the chip, such as an LED for a vehicle, can be improved. Further, the electrode coating 60 can be arranged to laterally spread the current to achieve a uniform current distribution.

In an embodiment, the distance D5 between the edge of the lower surface of the electrode coating layer 60 and the edge of the lower surface of the reflective electrode layer 50 may be greater than 2 μm and less than or equal to 6 μm. In this structure, the reflective electrode layer 50 is provided with a protective layer to prevent diffusion of Ag in the reflective electrode layer 50. Thus, the area of the reflective electrode layer 50 can be increased as much as possible under the premise of ensuring that Ag is not diffused, and the escape efficiency of light can be improved, thereby increasing the light extraction effect of the light emitting diode 1. The electrode coating 60 is arranged to function primarily as a current conductor.

In the examples of fig. 18 and 19, the reflective electrode layer 50 is formed by stacking Ag reflective layers and a plurality of pairs (Ni/TiW) in a preferred example. The total Ni/TiW thickness in the structure of the reflective electrode layer 50 is greater than 200nm. At this time, the reflective electrode layer 50 is structured with cladding and protection of Ag, so that the total area of the electrode cladding layer 60 is smaller than the total area of the reflective electrode layer 50. Thus, the area of the reflective electrode layer 50 can be increased, and the brightness of the light emitting diode 1 can be improved. The light emitting diode 1 with the structural design can be applied to high-current products, such as automotive products and backlight products, and also can be applied to low-current products, such as plant illumination products.

As can be appreciated with reference to fig. 42 and 43 in comparison to fig. 18 and 19. In other embodiments, as shown in fig. 42, the reflective electrode layer 50 is stacked by Ti, ag, tiWTi. Meanwhile, the reflective electrode layer 50 is partially in contact with the transparent conductive layer 40 through the second via 320 on the first insulating layer 32. The lowermost layer of the reflective electrode layer 50 includes Ti as an adhesion layer between the reflective electrode layer 50 and the transparent conductive layer 40 to enhance adhesion between the reflective electrode layer 50 and the transparent conductive layer 40. The bottom layer (containing Ti) of the reflective electrode layer 50 is stacked by Ag and TiWTi, so that the reflective electrode layer 50 is provided with a protective layer to prevent the diffusion of Ag in the reflective electrode layer 50.

In some embodiments, as shown in fig. 18 and 20, and fig. 42 and 44, a space D6 is provided between an edge of the lower surface of the reflective electrode layer 50 and an edge of the upper surface of the second conductive type semiconductor layer 23. The pitch D6 may be 5 μm or more and 13 μm or less, and may be 7 μm or 10 μm or 13 μm, for example. The distance D6 is 5 μm or more, and thus, ag in the reflective electrode layer 50 is prevented from diffusing to the sidewall of the epitaxial structure 20 to cause leakage and ESD abnormality at the time of etching. The interval D6 is less than or equal to 13 μm, which can leave enough space for the electrode coating layer 60, ensure that the electrode coating layer 60 has a certain interval with the mesa on the epitaxial structure 20, and simultaneously ensure that the electrode coating layer 60 maintains a certain interval with the reflective electrode layer 50, so as to reduce the risk of electrostatic discharge.

In some embodiments, as shown in fig. 8 and 14, the distance D8 between the first connection electrode 211 and the second connection electrode 231 may be 10 μm or more and 50 μm or less. In an embodiment, the distance D8 between the first connection electrode 211 and the second connection electrode 231 may be 15 μm or more. When the first connection electrode 211 and the second connection electrode 231 are subjected to photolithography using negative photoresist, a suspended structure (undercut) is formed after the photolithography, as shown by the arrow in fig. 60. The suspended structure is approximately in an inverted trapezoid shape, and the distance between two sides of the inverted trapezoid suspended structure is generally 2-6 μm. When the distance D8 between the first connection electrode 211 and the second connection electrode 231 is smaller than 10 μm, there is a risk of photoresist falling off or an abnormal phenomenon of photoresist falling off during vapor deposition of the first connection electrode 211 and the second connection electrode 231. The distance D8 between the first connection electrode 211 and the second connection electrode 231 is 50 μm or less, so that the area of the electrode connection layer can be increased as much as possible, which is advantageous for current spreading and heat transfer in the light emitting diode 1.

In some embodiments, the reflectivity of the first connection electrode 211 is greater than 70%. The first connection electrode 211 may be made of a highly reflective metal, such as Al, ag, mg, ru, rh. The reflectivity of the second connection electrode 231 is greater than 70%. The second connection electrode 231 may be made of a highly reflective metal, such as Al, ag, mg, ru, rh. As shown in fig. 15, an inner angle a5 formed by the sidewall of the first connection electrode 211 and the lower surface thereof is not greater than (or equal to) 60 °. The inner angle a6 formed by the sidewall of the second connection electrode 231 and the lower surface thereof is not more than (or equal to) 60 °. The thicknesses of the first connection electrode 211 and the second connection electrode 231 are both greater than 500nm.

As shown in fig. 16, the inner angle a7 formed by the sidewall of the first pad electrode 212 and the lower surface thereof may be not more than 70 °. The inner angle a8 formed by the sidewall of the second pad electrode 232 and the lower surface thereof may be not more than 70 °.

In some embodiments, as shown in fig. 5, 8 and 18 or fig. 25, 28 and 42, the lower surface of the second pad electrode 232 is entirely connected to the second connection electrode 231, and the lower surface of the first pad electrode 212 is entirely connected to the first connection electrode 211, achieving a separate interval between the P electrode and the N electrode. That is, a positive contact electrode is provided under the P electrode, and a negative contact electrode is provided under the N electrode. Thus, the capacitance effect of the light emitting diode 1 can be reduced to improve the reliability and yield of the light emitting diode 1.

In some embodiments, as shown in fig. 22 and 46, a plurality of first openings 71 and a plurality of second openings 72 are formed on the third insulating layer 70. The first pad electrode 212 may be connected to the first connection electrode 211 through the first opening 71, and the second pad electrode 232 may be connected to the second connection electrode 231 through the second opening 72. The area of the first opening 71 is larger than the area of the first pad electrode 212, and the area of the second opening 72 is larger than the area of the second pad electrode 232. It is understood that the projection of the second pad electrode 232 onto the epitaxial structure 20 is located within the second connection electrode 231, and the projection of the first pad electrode 212 onto the epitaxial structure 20 is located within the first connection electrode 211. As shown in fig. 23 and 24, and fig. 47 and 48, a distance D10 between an edge of the first opening 71 and an edge of the first pad electrode 212 may be less than 10 μm. The distance D11 between the edge of the second opening 72 and the edge of the second pad electrode 232 may be less than 10 μm. In some embodiments, the distance D10 between the edge of the first opening 71 and the edge of the first pad electrode 212 may be less than 5 μm. The distance D11 between the edge of the second opening 72 and the edge of the second pad electrode 232 may be less than 5 μm. By the arrangement, the first pad electrode 212 and the second pad electrode 232 are arranged on the same horizontal plane, so that the cavity rate of the package end crystal of the light-emitting diode 1 is reduced, and the heat dissipation performance is enhanced.

In some embodiments, as shown in fig. 16, the distance D12 between adjacent first and

second pad electrodes

212 and 232 may be 100 μm or more and 300 μm or less. The limitation of the size of the space D12 can ensure the packaging yield of the light emitting diode 1, for example, when the space D12 is too small, the space D can cause electric leakage due to the problem of die bonding precision, and meanwhile, the area of the bonding pad can be increased as much as possible, the adhesion between the bonding pad and the substrate is increased, and the heat dissipation is enhanced.

In some embodiments, as shown in fig. 8 and 22, and fig. 28 and 46, the first pad electrode 212 and the second pad electrode 232 have a certain distance D13 from the edge of the light emitting diode 1. In the drawings, the pitch D13 between the first pad electrode 212, the second pad electrode 232 and the edge of the substrate 10 (which may be understood as the edge of the chip of the light emitting diode 1) may be 50 μm or more and 100 μm or less. The arrangement and the size limitation of the interval D13 can reduce the area of the cutting channel and the area of the bonding pad as much as possible, increase the area of the light-emitting area to improve the brightness, and increase the area of the bonding pad as much as possible, increase the adhesion between the bonding pad and the substrate and enhance the heat dissipation.

The total area of the first pad electrode 212 is preferably greater than 20% of the total area of the epitaxial structure 20, and the total area of the second pad electrode 232 is preferably greater than 20% of the total area of the epitaxial structure 20. Referring again to fig. 16, the inner angle a7 formed by the sidewall of the first pad electrode 212 and the lower surface thereof may be not more than (or equal to) 70 °. The inner angle a8 formed by the sidewall of the second pad electrode 232 and the lower surface thereof may be not more than (or equal to) 70 °.

In some embodiments, the refractive index of the third insulating layer 70 is greater than 1.4. The third insulating layer 70 may include SiO ₂ 、 SiN、Al ₂ O ₃ Etc. The third insulating layer 70 may be a multi-layered film structure such as a bragg reflector (DBR) formed by alternately stacking dielectric films of high refractive index and dielectric films of low refractive index. Wherein the material of the dielectric film with high refractive index can be TiO ₂ 、 NB ₂ O ₅ 、TA ₂ O ₅ 、HfO ₂ 、ZrO ₂ Etc.; the material of the low-refraction dielectric film can be SiO ₂ 、MgF ₂ 、Al ₂ O ₅ SiON, etc. The thickness of the third insulating layer 70 is between 500nm and 1500 nm. The total area of the first openings 71 and the second openings 72 in the third insulating layer 70 is preferably greater than 20% of the total area of the epitaxial structure 20. Referring to fig. 23 and 24, and fig. 47 and 48, an inner angle a9 formed between a sidewall of the third insulating layer 70 and a lower surface thereof may be not more than (or not more than) 50 °. By this arrangement, the third insulating layer 70 can have good photoelectric properties.

In some embodiments, in the light emitting diode 1, a certain distance D14 is provided between the edge of the upper surface of the electrode coating layer 60 and the edge of the upper surface of the second conductivity type semiconductor layer 23 in the epitaxial structure 20. The distance D14 may be 5 μm or more and 15 μm or less. In some embodiments, as shown in fig. 8 and 17, and fig. 28 and 41, the electrode coating layer 60 covers the upper surface and a portion of the sidewall region of the reflective electrode layer 50. At this time, the distance D14 between the edge of the upper surface of the electrode coating layer 60 and the edge of the upper surface of the second conductivity type semiconductor layer 23 in the epitaxial structure 20 is 5 μm or more and 10 μm or less. Such a spacing setting ensures that there is sufficient spacing between the electrode coating layer 60 and the sidewall of the epitaxial structure 20 to prevent leakage or ESD damage.

In some embodiments, as shown in fig. 18 and 21, 42 and 45, the electrode coating layer 60 covers a portion of the upper surface of the reflective electrode layer 50, and the distance D14 between the edge of the upper surface of the electrode coating layer 60 and the edge of the upper surface of the second conductive type semiconductor layer 23 may be 7 μm or more and 15 μm or less. Such a pitch setting can ensure that the contact area between the electrode coating layer 60 and the reflective electrode layer 50 is increased as much as possible on the premise of the maximum area of the reflective electrode layer 50, and current spreading and heat dissipation are enhanced, thereby improving the luminance of the light emitting diode 1.

As shown in fig. 18 and 21, and fig. 42 and 45, it is further explained that the electrode coating layer 60 covers a part of the upper surface of the reflective electrode layer 50 at this time. In other words, the electrode coating layer 60 does not completely coat the reflective electrode layer 50 in this case, and does not play a role in preventing Ag diffusion in the reflective electrode layer 50, which is a role in enhancing current spreading. It is understood that in such embodiments, the electrode coating 60 is a metal extension layer 60. The metal extension layer 60 may be one of Cr, al, ti, pt, au, ni, tiW, W or an alloy of any combination thereof or a stack of any combination thereof. The total thickness of the metal extension layer 60 is between 500nm and 2000 nm. The arrangement ensures that the metal extension layer 60 has good current conduction effect, thereby enhancing the current extension effect of the light emitting diode 1 and improving the brightness.

Please refer to fig. 28 to 51 in conjunction with fig. 25 to 27. Fig. 25 is a schematic top view of a third embodiment of the led according to the present invention, and fig. 26 and 27 are respectively enlarged schematic views of a region F, G in fig. 25. Fig. 28 to 41 are schematic cross-sectional views of the led shown in fig. 25 taken along the Y-Y direction and associated enlarged schematic views. Fig. 42 to 45, fig. 46 to 48, and fig. 49 to 51 are respectively schematic cross-sectional views and enlarged schematic views of different variants of the led shown in fig. 28. Further, fig. 52 to 57 are cross-sectional views of the led shown in fig. 25 taken along different directions in fig. 52, so as to show different detailed structural features of the led 1 from different perspectives for further reference.

Fig. 25, fig. 28 and their modified embodiments will be described below with reference to fig. 5, fig. 8 and their modified embodiments corresponding to the reference numerals. The same reference numerals refer to the foregoing descriptions of fig. 5 and 8 and the modified embodiments thereof, and mainly focus on the differences between fig. 25 and 28 and the modified embodiments thereof.

As will be appreciated with reference to fig. 25 and 28 in conjunction with fig. 5 and 8. In opposite embodiments, the transparent conductive layer 40 is formed on the upper surface of the second conductive type semiconductor layer 23 of the epitaxial structure 20 and has a certain distance from the edge of the upper surface of the second conductive type semiconductor layer 23. The first insulating layer 32 is formed on the transparent conductive layer 40 to cover the upper surface and the sidewall of the transparent conductive layer 40, the edge region N of the second conductive type semiconductor layer 23 (the portion not covered by the transparent conductive layer 40 in the drawing), and the edge region M and the sidewall of the epitaxial structure 20. The reflective electrode layer 50 is formed on the first insulating layer 32 and may not contact the transparent conductive layer 40. An electrode coating layer 60 is formed on the reflective electrode layer 50, covering the upper surface and sidewalls of the reflective electrode layer 50 and a portion of the upper surface of the first insulating layer 32. Specifically, in the plan view 25, the distribution of the conductive openings 31, the second conductivity type semiconductor layer 23, the transparent conductive layer 40, the reflective electrode layer 50, and the electrode coating layer 60 is shown in fig. 26.

As will be appreciated with reference to fig. 28, in some embodiments, the distance of the transparent conductive layer 40 from the edge of the epitaxial structure 20 (also known as the edge of the upper surface of the second conductivity type semiconductor layer 23) is less than the distance of the reflective electrode layer 50 from the edge of the epitaxial structure 20 (also known as the edge of the upper surface of the second conductivity type semiconductor layer 23). In other words, the projection of the reflective electrode layer 50 onto the epitaxial structure 20 is located in the transparent conductive layer 40 (see fig. 26). In this way, the area of the transparent conductive layer 40 covered on the semiconductor light emitting stack (the second conductivity type semiconductor layer 23 in the drawing) may be larger than the area of the reflective electrode layer 50. This can increase the contact area of the second conductive type semiconductor layer 23 and the transparent conductive layer 40, thereby contributing to a reduction in the operating voltage of the device.

As shown in fig. 28 and 30, in the led 1, the connection between the first insulating layer 32 and the conductive opening 31 has an inclined side 321, and an internal angle a1 formed by the side 321 is not greater than (or equal to) 50 °. The connection between the second insulating layer 33 and the conductive opening 31 has an inclined side 331, and an internal angle a2 formed by the side 331 is not greater than (or equal to) 50 °. In this way, the first insulating layer 32 and the second insulating layer 33 in the region of the conductive opening 31 can be ensured to have a sufficient thickness after etching, so that the epitaxial structure 20 has a sufficient insulation protection and anti-leakage performance. In some embodiments, the inner angle a1 formed by the inclined side surface of the first insulating layer 32 may be 30 ° or less.

Referring to fig. 31 in conjunction with fig. 28, in some embodiments, a distance D2 between an edge of the upper surface of the transparent conductive layer 40 and an edge of the upper surface of the second conductive type semiconductor layer 23 may be 2 μm or more and 10 μm or less, for example, 4 μm or more. In the example of fig. 31, when the distance D2 between the edge of the upper surface of the transparent conductive layer 40 and the edge of the upper surface of the second conductivity type semiconductor layer 23 is 2 μm or more, a certain distance between the transparent conductive layer 40 and the mesa on the epitaxial structure 20 can be ensured. When the pitch D2 is 10 μm or less, the area of the transparent conductive layer 40 can be increased as much as possible, the P-plane ohmic contact can be increased, and the voltage can be reduced. Thus, the light emitting diode 1 can be prevented from generating leakage and abnormal electrostatic discharge.

As shown in fig. 28, in some embodiments, the first insulating layer 32 covers the transparent conductive layer 40 and has a plurality of through holes 320 exposing a portion of the surface of the transparent conductive layer 40. The reflective electrode layer 50 covers the first insulating layer 32 and may be electrically connected to the transparent conductive layer 40 through the through holes 320. The through holes 320 may serve as current through holes between the transparent conductive layer 40 and the reflective electrode layer 50, so that a current applied to the reflective layer may be diffused or spread through the transparent conductive layer 40. In the illustrated embodiment, ag may be included in the reflective electrode layer 50 to increase the reflectivity of the reflective electrode layer 50 to light, thereby improving the overall optoelectronic performance of the light emitting diode 1.

As shown in fig. 25-28 and 53, 53 and 56. The through holes 320 may be distributed at regular intervals. The spacing pitch may be an equal pitch arrangement. The interval pitch may be set in an arithmetic series or an arithmetic series. However, the through holes 320 may be distributed at irregular intervals according to the application scenario of the product or other design requirements. Alternatively, the regular interval pitch may be other pitch rules. That is, the arrangement of the through holes 320 can be adjusted and designed according to the actual requirements. The vias 320 may be distributed over all or a portion of the first insulating layer 32. The second through-hole 320 may have various shapes including regular shapes or irregular shapes, such as a circle, a regular polygon, and an irregular polygon.

As will be understood with reference to fig. 49 to 51, in some embodiments, in the light emitting diode 1, the transparent conductive layer 40 is located on the second conductive type semiconductor layer 23 of the epitaxial structure 20, and a plurality of first through holes 41 are provided on the transparent conductive layer 40. The first insulating layer 32 may contact the second conductive type semiconductor layer 23 through the first through holes 41 on the transparent conductive layer 40, and the first insulating layer 32 covers the transparent conductive layer 40 and has a plurality of second through holes 320 exposing a portion of the surface of the transparent conductive layer 40. The first through holes 41 and the second through holes 320 on the first insulating layer 32 are not mutually communicated with each other along the stacking direction 41. That is, the first through holes 41 and the second through holes 320 are staggered with each other along the stacking direction, and have no overlap.

Indium Tin Oxide (ITO) may be included in the transparent conductive layer 40 in the illustrated example. In view of the light absorption effect of the transparent conductive layer 40 made of Indium Tin Oxide (ITO), the arrangement of the first through holes 41 can reduce the amount of light absorbed by the transparent conductive layer 40, thereby improving the luminous flux of the transparent conductive layer 40. At the same time, a current spreading effect or a current spreading effect of the transparent conductive layer 40 can be ensured. Specifically, the first insulating layer 32 may be a light-transmissive insulating layer, and may form an omnidirectional reflector with the reflective electrode layer 50 to enhance the light reflection effect. The first insulating layer 32 is filled in the first through hole 41 so that light emitted from the light emitting layer 22 may be reflected without being absorbed into the transparent conductive layer 40, thereby improving reflectivity as a whole to increase external light extraction efficiency.

As shown in fig. 50 and 51. The first through holes 41 may be distributed at regular intervals. The spacing pitch may be an equal pitch arrangement. The interval pitch may be set in an arithmetic series or an arithmetic series. However, the first through holes 41 may be distributed at irregular intervals according to the application scenario of the product or other design requirements. Alternatively, the regular interval pitch may be other pitch regularity. That is, the arrangement of the first through holes 41 can be adjusted and designed according to the actual requirements. The first through holes 41 may be distributed over all or a portion of the transparent conductive layer 40. The first through holes 41 may have various shapes including regular shapes or irregular shapes, such as circles, regular polygons, irregular polygons. The interval between the second through holes 320 and the interval between the first through holes 41 may or may not be the same.

In some embodiments, the diameter of the first through holes 41 is 2 μm or more. Preferably, the total area of the first through holes 41 accounts for 0.2% -20% of the total area of the epitaxial structure 20. In practical production and design, the ratio of the total area of the first vias 41 to the total area of the epitaxial structure 20 can be adjusted according to the driving current density of the product (generally known in product design).

In some embodiments, the diameter of the second through holes 320 is 2 μm or more. Preferably, the total area of the second through holes 320 is 0.2% -20% of the total area of the epitaxial structure 20. In practical production and design, the ratio of the total area of the second vias 320 to the total area of the epitaxial structure 20 can be adjusted according to the driving current density of the product (generally known in product design).

As shown in fig. 51, in some embodiments, the area of the single first via 41 is smaller than the area of the single second via 320, which is advantageous for both voltage and brightness of the LED chip. In some embodiments, the total area of the first vias 41 is smaller than the total area of the second vias 320. The LED 1 has the advantages of reduced voltage, high luminous efficiency, low electric power and the like.

Since the transparent conductive layer 40 has a light absorption effect, the light absorption effect affects the overall light emitting effect of the light emitting diode 1. The thinner the transparent conductive layer 40 is, the less light is absorbed, and the voltage of the light emitting diode 1 is increased. In order to make the light absorption effect of the transparent conductive layer 40 and the voltage of the light emitting diode 1 in a balanced state, the thickness of the transparent conductive layer 40 may be between 5nm and 150 nm. In one embodiment, the thickness of the transparent conductive layer 40 may be 15-30 nm. In other embodiments, the thickness of the transparent conductive layer 40 may be 4-5 nm. The first insulating layer 32 serves both for insulation and to help increase the brightness of the light emitting diode 1. The thickness of the first insulating layer 32 is between 300nm and 1500 nm. At this time, the first insulating layer 32 is advantageous to improve light efficiency, thereby improving the brightness of the light emitting diode 1. In one embodiment, the thickness of the first insulating layer 32 may be 400nm or more.

Reference is made to fig. 34 to 35 in conjunction with fig. 25 and 26. In some embodiments, as shown in fig. 25, the first insulating layer 32 has a plurality of second through holes 320 thereon. As shown in fig. 34, another second through hole 320 closest to the edge of the lower surface of the other end (left side end) of the reflective electrode layer 50 is located at a distance D4 from the edge of the upper surface of the first insulating layer 32 to the edge of the lower surface of the reflective electrode layer 50. As shown in fig. 35, one second via 320 closest to the edge of the lower surface of one end (right side end) of the reflective electrode layer 50 is located at a distance D4 from the edge of the upper surface of the first insulating layer 32 and the edge of the lower surface of the reflective electrode layer 50.

As shown in the figure, the pitch D4 is preferably 5 μm or more and 50 μm or less. The second via 320 on the first insulating layer 32 expands during BOE wet etching and the reflective electrode layer 50 expands during sputtering. In addition, the second via 320 and the reflective electrode layer 50 may be offset at the time of exposure. When the distance D4 is too small, the edges of the second via 320 and the reflective electrode layer 50 are liable to cross. In general, positive photoresist is used for photolithography, and if the cross phenomenon is equivalent to that of plating metal with positive photoresist, the reflective electrode layer 50 is not completely stripped when photoresist is removed by a stripping photoresist method, so that the subsequent metal coverage and insulating layer coverage are abnormal to cause leakage or electrostatic discharge (ESD) loss.

In one embodiment, the distance D4 may be greater than 10 μm. In one embodiment, the distance D4 may be 15 μm or more. Thus, the edges of the second via hole 320 and the reflective electrode layer 50 are not crossed, and the edges of the reflective electrode layer 50 are not plated inside the second via hole 320 in the first insulating layer 32, so that the problem of electric leakage or electrostatic discharge (ESD) damage is solved.

In some embodiments, as shown in fig. 33, the reflectivity of the reflective electrode layer 50 is 93% or more, the internal angle a3 formed by the sidewall of the reflective electrode layer 50 and the lower surface thereof is not more than (or equal to) 30 °, the reflectivity of the electrode coating layer 60 is 60% or more, and the internal angle a4 formed by the sidewall of the electrode coating layer 60 and the lower surface thereof is not more than (or equal to) 60 °.

In some embodiments, as shown in fig. 28 and 36, the distance D7 between the edge of the lower surface of the reflective electrode layer 50 and the edge of the lower surface of the transparent conductive layer 40 may be 2 μm or more and 9 μm or less, and the total area of the transparent conductive layer 40 is greater than the total area of the reflective electrode layer 50, so that the area of the reflective electrode layer 50 is increased as much as possible while the electrode coating layer 60 is coated and protected, thereby improving the light efficiency and the chip brightness. In some embodiments, the total area of the reflective electrode layer 50 is preferably greater than 80% of the total area of the epitaxial structure 20, and the area removed when the first conductivity type semiconductor layer 21 is etched is preferably less than 10% of the total area of the epitaxial structure 20. In this way, the total area of the reflective electrode layer 50 is increased as much as possible by controlling the process of the light emitting diode 1, thereby improving the brightness of the light emitting diode 1.

As shown in fig. 25 and 27, 28 and 37, the distance D8 between the first connection electrode 211 and the second connection electrode 231 may be 10 μm or more and 50 μm or less. In an embodiment, the distance D8 between the first connection electrode 211 and the second connection electrode 231 may be 15 μm or more. When the first connection electrode 211 and the second connection electrode 231 are subjected to photolithography using negative photoresist, a suspended structure (undercut) is formed after the photolithography, as shown by the arrow in fig. 60. The suspended structure is approximately in an inverted trapezoid shape, and the distance between two sides of the inverted trapezoid suspended structure is generally 2-6 mu m. When the distance D8 between the first connection electrode 211 and the second connection electrode 231 is smaller than 10 μm, there is a risk of photoresist falling off or an abnormal phenomenon of photoresist falling off during vapor deposition of the first connection electrode 211 and the second connection electrode 231. When the distance D8 between the first connection electrode 211 and the second connection electrode 231 is 50 μm or less, the area of the electrode connection layer can be increased as much as possible, which is advantageous for current spreading and heat transfer in the light emitting diode 1.

As shown in fig. 28 and 29, an edge of the first connection electrode 211 contacting the first conductive type semiconductor layer 21 and an edge of the upper surface of the second conductive type semiconductor layer 23 have a certain distance D1. This spacing D1 shown in fig. 28 and 29 can be understood as a spacing D1 between the edge of the electric opening 31 and the edge of the upper surface of the second conductivity type semiconductor layer 23. Referring to fig. 29 in conjunction with fig. 6, 7 and 9, in this example, a distance D1 between an edge of the conductive opening 31 and an edge of the upper surface of the second conductive type semiconductor layer 23 may be 1 μm or more, for example, may be 2 to 12 μm or 1 to 8 μm. In an embodiment, a distance D1 between an edge of the conductive opening 31 and an edge of the upper surface of the second conductive type semiconductor layer 23 may be 4 μm or more. The arrangement of the distance D1 can ensure that the insulating layer covered by the sidewall area of the epitaxial structure 20 has a certain thickness, so as to achieve sufficient insulation protection for the epitaxial structure 20, thereby enabling the light emitting diode 1 to have better insulation protection, water vapor resistance and anti-leakage performance.

In some embodiments, the reflectivity of the first connection electrode 211 is greater than 70%. The first connection electrode 211 may be made of a highly reflective metal, such as Al, ag, mg, ru, rh. The reflectivity of the second connection electrode 231 is greater than 70%. The second connection electrode 231 may be made of a highly reflective metal, such as Al, ag, mg, ru, rh. As shown in fig. 15 and 38, an inner angle a5 formed between the sidewall of the first connection electrode 211 and the lower surface thereof is not greater than (or equal to) 60 °. The inner angle a6 formed by the sidewall of the second connection electrode 231 and the lower surface thereof is not more than (or equal to) 60 °. The thicknesses of the first connection electrode 211 and the second connection electrode 231 are both greater than 500nm.

As shown in fig. 28 and 39, the distance D9 between the edge of the lower surface of the first connection electrode 211 and the chip edge of the light emitting diode 1 may be 10 μm or more and 50 μm or less. Therefore, the area of the welding plate can be increased as much as possible, the adhesion force between the welding plate and the substrate is increased, and the heat dissipation is enhanced, so that the overall photoelectric performance of the light-emitting diode 1 is improved.

As shown in fig. 40, the inner angle a7 formed by the sidewall of the first pad electrode 212 and the lower surface thereof may be not more than (or equal to or less than) 70 °. The inner angle a8 formed by the sidewall of the second pad electrode 232 and the lower surface thereof may be not more than (or equal to) 70 °.

In some embodiments, as shown in fig. 40, the distance D12 between adjacent first and

second pad electrodes

212 and 232 may be 100 μm or more and 300 μm or less. The limitation of the size of the space D12 can ensure the packaging yield of the light emitting diode 1, for example, when the space D12 is too small, the space D can cause electric leakage due to the problem of die bonding precision, and meanwhile, the area of the bonding pad can be increased as much as possible, the adhesion between the bonding pad and the substrate is increased, and the heat dissipation is enhanced. As shown in fig. 28, the first pad electrode 212 and the second pad electrode 232 have a certain distance D13 from the edge of the light emitting diode 1. In the drawings, the pitch D13 between the first pad electrode 212, the second pad electrode 232 and the edge of the substrate 10 (which may be understood as the edge of the chip of the light emitting diode 1) may be 50 μm or more and 100 μm or less. The arrangement and the size limitation of the interval D13 can reduce the area of the cutting track and the area of the bonding pad as much as possible, increase the area of the light-emitting area to improve the brightness, and increase the area of the bonding pad as much as possible, increase the adhesion between the bonding pad and the substrate and enhance the heat dissipation.

The total area of the first pad electrode 212 is preferably greater than 20% of the total area of the epitaxial structure 20, and the total area of the second pad electrode 232 is preferably greater than 20% of the total area of the epitaxial structure 20. Referring again to fig. 40, the inner angle a7 formed by the sidewall of the first pad electrode 212 and the lower surface thereof may be not more than (or equal to) 70 °. The inner angle a8 formed by the sidewall of the second pad electrode 232 and the lower surface thereof may be not more than (or equal to) 70 °. Referring again to fig. 47 and 48, the inner angle a9 formed by the sidewall of the third insulating layer 70 and the lower surface thereof may be not more than (or equal to) 50 °. By this arrangement, the third insulating layer 70 can have good photoelectric properties.

In general, the materials of the pad electrodes (e.g., the first pad electrode 212, the second pad electrode 232) include Ti, al, ni, pt, au, wherein the outermost layer is Au. To facilitate packaging and use of the light emitting diode 1, in some embodiments, a solder layer may be added to the pad electrodes (e.g., the first pad electrode 212 and the second pad electrode 232). The solder layer is a material containing Sn, and may be, for example, sn-Ag-Cu alloy or Sn-Sb alloy. The liquid phase melting point of the solder layer is 200-250 ℃. The thickness of the solder layer may be 60-100 μm, ensuring that the light emitting diode 1 has sufficient solder at the package end for soldering. In some embodiments, the thickness of the solder layer may be 80±10 μm. The arrangement of the solder layer can facilitate the die bonding packaging of the subsequent light-emitting diode 1, and reduce the risk of electric leakage.

The solder layer is disposed over the pad electrode. As shown in fig. 58, the upper surfaces of the first pad electrode 212 and the second pad electrode 232 are respectively provided with

solder layers

214 and 234, and the solder layers 214 and 234 are respectively protruded upward from the upper surfaces of the first pad electrode 212 and the second pad electrode 232 to form an arc convex surface. The arc convex surface has an apex farthest from the upper surfaces of the first pad electrode 212 and the second pad electrode 232. As shown in fig. 59, the upper surfaces of the first pad electrode 212 and the second pad electrode 232 are respectively provided with

solder layers

214 and 234, and the solder layers 214 and 234 are respectively protruded upward from the upper surfaces of the first pad electrode 212 and the second pad electrode 232 to form an arc convex surface. The end surface of the arc-shaped convex surface farthest from the upper surfaces of the first pad electrode 212 and the second pad electrode 232 is a plane. In the example of fig. 59, the top surfaces of the solder layers 214 and 234 are planarized to form flat surfaces, so that the surfaces of the solder layers 214 and 234 are easier to be inverted, the void ratio is reduced, and the die bonding and packaging of the light emitting diode 1 are facilitated.

To achieve at least one of the advantages and other advantages, an embodiment of the present invention provides a light emitting module, which is made of the light emitting diode as described above. The light-emitting module has good photoelectric performance.

In summary, compared with the prior art, the light emitting diode, the light emitting module and the display device provided by the invention have good photoelectric characteristics.

In addition, it should be understood by those skilled in the art that although many problems exist in the prior art, each embodiment or technical solution of the present invention may be modified in only one or several respects, without having to solve all technical problems listed in the prior art or the background art at the same time. Those skilled in the art will understand that nothing in one claim should be taken as a limitation on that claim.

Although terms such as light emitting diode, epitaxial structure, transparent conductive layer, insulating layer, reflective layer, protective layer, contact electrode, pad electrode, etc. are more used herein, the possibility of using other terms is not excluded. These terms are used merely for convenience in describing and explaining the nature of the invention; they are to be interpreted as any additional limitation that is not inconsistent with the spirit of the present invention. The terms "upper", "lower", "vertical", "horizontal", "top", "bottom", "upper surface", "left", "right", "side wall", "directly above", and the like in the description and the claims of embodiments of the present invention and in the above drawings, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments may be modified or some or all of the technical features may be replaced with equivalents; such modifications and substitutions do not depart from the spirit of the technical solutions of the embodiments of the present invention.

Claims

1. A light emitting diode, comprising:

an epitaxial structure including a first conductivity type semiconductor layer, a light emitting layer, and a second conductivity type semiconductor layer stacked in order;

the transparent conductive layer is positioned on the second conductive type semiconductor layer and provided with a plurality of first through holes;

the first insulating layer at least covers the edge area and the side wall of the epitaxial structure and is provided with a plurality of second through holes; the first insulating layer is formed on the transparent conductive layer and is in contact with the second conductive type semiconductor layer through the first via hole; and

a reflective electrode layer formed on the first insulating layer and in contact with the transparent conductive layer through the second via hole;

Wherein a distance between an edge of the upper surface of the first insulating layer and an edge of the lower surface of the reflective electrode layer is 5 μm or more and 50 μm or less; the area of the single second through hole is larger than that of the single first through hole.

2. A light emitting diode according to claim 1 wherein: and the second through hole nearest to the edge of the lower surface of the side wall of the reflective electrode layer, and the interval between the edge of the upper surface of the first insulating layer and the edge of the lower surface of the reflective electrode layer is more than 10 μm or more than 15 μm.

3. A light emitting diode according to claim 1 wherein: the light emitting diode further comprises at least one mesa which is positioned in the epitaxial structure and/or at the edge area, at least part of the upper surface of the first conductive type semiconductor layer is exposed, and the light emitting diode is provided with a conductive opening; the spacing is between the second via and an edge of a lower surface of a sidewall of the reflective electrode layer nearest the conductive opening located inside or in an edge region of the epitaxial structure.

4. A light emitting diode according to claim 1 wherein: the first through holes and the second through holes are alternately arranged at intervals which are not communicated along the stacking direction.

5. A light emitting diode according to claim 4 wherein: the diameter of the second through hole is more than or equal to 2 mu m, and the diameter of the first through hole is more than or equal to 2 mu m.

6. A light emitting diode according to claim 4 wherein: the total area of the first through holes is more than or equal to 0.2% of the total area of the epitaxial structure and less than or equal to 20% of the total area of the epitaxial structure.

7. A light emitting diode according to claim 1 wherein: the transparent conductive layer has a thickness between 5nm and 150 nm.

8. A light emitting diode according to claim 1 wherein: a distance between an edge of an upper surface of the transparent conductive layer and an edge of an upper surface of the second conductive type semiconductor layer is greater than 2 μm.

9. A light emitting diode according to claim 1 wherein: the total area of the plurality of second through holes is more than or equal to 0.2% of the total area of the epitaxial structure and less than or equal to 20% of the total area of the epitaxial structure.

10. A light emitting diode according to claim 1 wherein: the first insulating layer has a thickness between 300nm and 1500 nm.

11. A light emitting diode according to claim 1 wherein: the first insulating layer comprises at least SiO ₂ 、SiN、Al ₂ O ₃ One or a combination thereof.

12. A light emitting diode according to claim 1 wherein: the first insulating layer covers an edge region of the epitaxial structure, and the distance from the reflective electrode layer to the edge of the epitaxial structure is smaller than the distance from the transparent conductive layer to the edge of the epitaxial structure.

13. A light emitting diode according to claim 1 wherein: the first insulating layer is provided with a conductive opening, and the distance between the edge of the conductive opening and the edge of the upper surface of the transparent conductive layer is more than or equal to 4 mu m.

14. A light emitting diode according to claim 1 wherein: the light emitting diode further includes:

an electrode coating layer on the reflective electrode layer, at least covering a part of the reflective electrode layer or a part of the upper surfaces of the reflective electrode layer and the first insulating layer;

a second insulating layer which is positioned above the first insulating layer and covers the first insulating layer and the electrode coating layer;

A first connection electrode disposed above the second insulating layer and partially penetrating the second insulating layer to be electrically connected with the first conductive type semiconductor layer; and

the second connecting electrode is arranged above the second insulating layer and partially penetrates through the second insulating layer to be electrically connected with the electrode coating layer.

15. A light emitting diode according to claim 14 wherein: the distance between the second connection electrode and the first connection electrode is 10 μm or more and 50 μm or less.

16. A light emitting diode according to claim 14 wherein: a distance between an edge of the first connection electrode contacting the first conductive type semiconductor layer to an edge of an upper surface of the second conductive type semiconductor layer is greater than 2 μm.

17. A light emitting diode according to claim 14 wherein: the thicknesses of the first connecting electrode and the second connecting electrode are both larger than 500nm.

18. A light emitting diode according to claim 14 wherein: the first connecting electrode is provided with an inclined side surface, and the inclination angle of the side surface is not more than 60 degrees; the second connection electrode has an inclined side face with an inclination angle of not more than 60 °.

19. A light emitting diode according to claim 14 wherein: the interval between the edge of the lower surface of the first connecting electrode and the chip edge of the light emitting diode is more than or equal to 10 mu m.

20. A light emitting diode according to claim 14 wherein: the light emitting diode further includes:

a third insulating layer located above the second insulating layer and at least covering part of the second insulating layer, the first connecting electrode and the second connecting electrode;

the first pad electrode is positioned above the third insulating layer and is electrically connected with the first connecting electrode through a first opening in the third insulating layer; and

and the second bonding pad electrode is positioned above the third insulating layer and is electrically connected with the electrode coating layer through a second opening in the third insulating layer.

21. A light emitting diode according to claim 20 wherein: the area of the first opening is larger than the area of the first pad electrode, and the area of the second opening is larger than the area of the second pad electrode.

22. A light emitting diode according to claim 20 wherein: a pitch between an edge of the first opening and an edge of the first pad electrode is less than 10 μm, and a pitch between an edge of the second opening and an edge of the second pad electrode is less than 10 μm.

23. A light emitting diode according to claim 20 wherein: the total area of the first openings and the second openings is greater than 20% of the total area of the epitaxial structure.

24. A light emitting diode according to claim 20 wherein: a pitch between the adjacent first pad electrode and second pad electrode is greater than 100 μm.

25. A light emitting diode according to claim 20 wherein: the first pad electrode and the second pad electrode are spaced apart from edges of the chip of the light emitting diode by more than 50 μm, respectively.

26. A light emitting diode according to claim 20 wherein: the total area of the first pad electrode is greater than 20% of the total area of the epitaxial structure, and the total area of the second pad electrode is greater than 20% of the total area of the epitaxial structure.

27. A light emitting diode according to claim 20 wherein: the first pad electrode has an inclined side surface, and the inclination angle of the side surface is 70 degrees or less; the second pad electrode has an inclined side face having an inclination angle of not more than 70 °.

28. A light emitting module, characterized in that: use of a light emitting diode according to any one of claims 1-27.